clk-provider.h 5.7 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2019 DENX Software Engineering
  4. * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
  5. *
  6. * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
  7. * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
  8. */
  9. #ifndef __LINUX_CLK_PROVIDER_H
  10. #define __LINUX_CLK_PROVIDER_H
  11. #include <linux/bitops.h>
  12. #include <linux/err.h>
  13. #include <clk-uclass.h>
  14. #include <linux/err.h>
  15. struct udevice;
  16. static inline void clk_dm(ulong id, struct clk *clk)
  17. {
  18. if (!IS_ERR(clk))
  19. clk->id = id;
  20. }
  21. /*
  22. * flags used across common struct clk. these flags should only affect the
  23. * top-level framework. custom flags for dealing with hardware specifics
  24. * belong in struct clk_foo
  25. *
  26. * Please update clk_flags[] in drivers/clk/clk.c when making changes here!
  27. */
  28. #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */
  29. #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
  30. #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
  31. #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */
  32. /* unused */
  33. #define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */
  34. #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
  35. #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
  36. #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
  37. #define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */
  38. #define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */
  39. #define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */
  40. /* parents need enable during gate/ungate, set rate and re-parent */
  41. #define CLK_OPS_PARENT_ENABLE BIT(12)
  42. /* duty cycle call may be forwarded to the parent clock */
  43. #define CLK_DUTY_CYCLE_PARENT BIT(13)
  44. #define CLK_MUX_INDEX_ONE BIT(0)
  45. #define CLK_MUX_INDEX_BIT BIT(1)
  46. #define CLK_MUX_HIWORD_MASK BIT(2)
  47. #define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */
  48. #define CLK_MUX_ROUND_CLOSEST BIT(4)
  49. struct clk_mux {
  50. struct clk clk;
  51. void __iomem *reg;
  52. u32 *table;
  53. u32 mask;
  54. u8 shift;
  55. u8 flags;
  56. /*
  57. * Fields from struct clk_init_data - this struct has been
  58. * omitted to avoid too deep level of CCF for bootloader
  59. */
  60. const char * const *parent_names;
  61. u8 num_parents;
  62. #if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
  63. u32 io_mux_val;
  64. #endif
  65. };
  66. #define to_clk_mux(_clk) container_of(_clk, struct clk_mux, clk)
  67. extern const struct clk_ops clk_mux_ops;
  68. u8 clk_mux_get_parent(struct clk *clk);
  69. struct clk_gate {
  70. struct clk clk;
  71. void __iomem *reg;
  72. u8 bit_idx;
  73. u8 flags;
  74. #if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
  75. u32 io_gate_val;
  76. #endif
  77. };
  78. #define to_clk_gate(_clk) container_of(_clk, struct clk_gate, clk)
  79. #define CLK_GATE_SET_TO_DISABLE BIT(0)
  80. #define CLK_GATE_HIWORD_MASK BIT(1)
  81. extern const struct clk_ops clk_gate_ops;
  82. struct clk *clk_register_gate(struct device *dev, const char *name,
  83. const char *parent_name, unsigned long flags,
  84. void __iomem *reg, u8 bit_idx,
  85. u8 clk_gate_flags, spinlock_t *lock);
  86. struct clk_div_table {
  87. unsigned int val;
  88. unsigned int div;
  89. };
  90. struct clk_divider {
  91. struct clk clk;
  92. void __iomem *reg;
  93. u8 shift;
  94. u8 width;
  95. u8 flags;
  96. const struct clk_div_table *table;
  97. #if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
  98. u32 io_divider_val;
  99. #endif
  100. };
  101. #define clk_div_mask(width) ((1 << (width)) - 1)
  102. #define to_clk_divider(_clk) container_of(_clk, struct clk_divider, clk)
  103. #define CLK_DIVIDER_ONE_BASED BIT(0)
  104. #define CLK_DIVIDER_POWER_OF_TWO BIT(1)
  105. #define CLK_DIVIDER_ALLOW_ZERO BIT(2)
  106. #define CLK_DIVIDER_HIWORD_MASK BIT(3)
  107. #define CLK_DIVIDER_ROUND_CLOSEST BIT(4)
  108. #define CLK_DIVIDER_READ_ONLY BIT(5)
  109. #define CLK_DIVIDER_MAX_AT_ZERO BIT(6)
  110. extern const struct clk_ops clk_divider_ops;
  111. unsigned long divider_recalc_rate(struct clk *hw, unsigned long parent_rate,
  112. unsigned int val,
  113. const struct clk_div_table *table,
  114. unsigned long flags, unsigned long width);
  115. struct clk_fixed_factor {
  116. struct clk clk;
  117. unsigned int mult;
  118. unsigned int div;
  119. };
  120. #define to_clk_fixed_factor(_clk) container_of(_clk, struct clk_fixed_factor,\
  121. clk)
  122. struct clk_fixed_rate {
  123. struct clk clk;
  124. unsigned long fixed_rate;
  125. };
  126. #define to_clk_fixed_rate(dev) ((struct clk_fixed_rate *)dev_get_platdata(dev))
  127. struct clk_composite {
  128. struct clk clk;
  129. struct clk_ops ops;
  130. struct clk *mux;
  131. struct clk *rate;
  132. struct clk *gate;
  133. const struct clk_ops *mux_ops;
  134. const struct clk_ops *rate_ops;
  135. const struct clk_ops *gate_ops;
  136. };
  137. #define to_clk_composite(_clk) container_of(_clk, struct clk_composite, clk)
  138. struct clk *clk_register_composite(struct device *dev, const char *name,
  139. const char * const *parent_names, int num_parents,
  140. struct clk *mux_clk, const struct clk_ops *mux_ops,
  141. struct clk *rate_clk, const struct clk_ops *rate_ops,
  142. struct clk *gate_clk, const struct clk_ops *gate_ops,
  143. unsigned long flags);
  144. int clk_register(struct clk *clk, const char *drv_name, const char *name,
  145. const char *parent_name);
  146. struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
  147. const char *parent_name, unsigned long flags,
  148. unsigned int mult, unsigned int div);
  149. struct clk *clk_register_divider(struct device *dev, const char *name,
  150. const char *parent_name, unsigned long flags,
  151. void __iomem *reg, u8 shift, u8 width,
  152. u8 clk_divider_flags);
  153. struct clk *clk_register_mux(struct device *dev, const char *name,
  154. const char * const *parent_names, u8 num_parents,
  155. unsigned long flags,
  156. void __iomem *reg, u8 shift, u8 width,
  157. u8 clk_mux_flags);
  158. const char *clk_hw_get_name(const struct clk *hw);
  159. ulong clk_generic_get_rate(struct clk *clk);
  160. struct clk *dev_get_clk_ptr(struct udevice *dev);
  161. #endif /* __LINUX_CLK_PROVIDER_H */