fsl_ifc.h 29 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2010-2011 Freescale Semiconductor, Inc.
  4. * Author: Dipen Dudhat <dipen.dudhat@freescale.com>
  5. */
  6. #ifndef __FSL_IFC_H
  7. #define __FSL_IFC_H
  8. #ifdef CONFIG_FSL_IFC
  9. #include <config.h>
  10. #include <common.h>
  11. #include <part.h>
  12. #ifdef CONFIG_ARM
  13. #include <asm/arch/soc.h>
  14. #endif
  15. #define FSL_IFC_V1_1_0 0x01010000
  16. #define FSL_IFC_V2_0_0 0x02000000
  17. #ifdef CONFIG_SYS_FSL_IFC_LE
  18. #define ifc_in32(a) in_le32(a)
  19. #define ifc_out32(a, v) out_le32(a, v)
  20. #define ifc_in16(a) in_le16(a)
  21. #define ifc_out16(a, v) out_le16(a, v)
  22. #elif defined(CONFIG_SYS_FSL_IFC_BE)
  23. #define ifc_in32(a) in_be32(a)
  24. #define ifc_out32(a, v) out_be32(a, v)
  25. #define ifc_in16(a) in_be16(a)
  26. #define ifc_out16(a, v) out_be16(a, v)
  27. #else
  28. #error Neither CONFIG_SYS_FSL_IFC_LE nor CONFIG_SYS_FSL_IFC_BE is defined
  29. #endif
  30. /*
  31. * CSPR - Chip Select Property Register
  32. */
  33. #define CSPR_BA 0xFFFF0000
  34. #define CSPR_BA_SHIFT 16
  35. #define CSPR_PORT_SIZE 0x00000180
  36. #define CSPR_PORT_SIZE_SHIFT 7
  37. /* Port Size 8 bit */
  38. #define CSPR_PORT_SIZE_8 0x00000080
  39. /* Port Size 16 bit */
  40. #define CSPR_PORT_SIZE_16 0x00000100
  41. /* Port Size 32 bit */
  42. #define CSPR_PORT_SIZE_32 0x00000180
  43. /* Write Protect */
  44. #define CSPR_WP 0x00000040
  45. #define CSPR_WP_SHIFT 6
  46. /* Machine Select */
  47. #define CSPR_MSEL 0x00000006
  48. #define CSPR_MSEL_SHIFT 1
  49. /* NOR */
  50. #define CSPR_MSEL_NOR 0x00000000
  51. /* NAND */
  52. #define CSPR_MSEL_NAND 0x00000002
  53. /* GPCM */
  54. #define CSPR_MSEL_GPCM 0x00000004
  55. /* Bank Valid */
  56. #define CSPR_V 0x00000001
  57. #define CSPR_V_SHIFT 0
  58. /* Convert an address into the right format for the CSPR Registers */
  59. #define CSPR_PHYS_ADDR(x) (((uint64_t)x) & 0xffff0000)
  60. /*
  61. * Address Mask Register
  62. */
  63. #define IFC_AMASK_MASK 0xFFFF0000
  64. #define IFC_AMASK_SHIFT 16
  65. #define IFC_AMASK(n) (IFC_AMASK_MASK << \
  66. (LOG2(n) - IFC_AMASK_SHIFT))
  67. /*
  68. * Chip Select Option Register IFC_NAND Machine
  69. */
  70. /* Enable ECC Encoder */
  71. #define CSOR_NAND_ECC_ENC_EN 0x80000000
  72. #define CSOR_NAND_ECC_MODE_MASK 0x30000000
  73. /* 4 bit correction per 520 Byte sector */
  74. #define CSOR_NAND_ECC_MODE_4 0x00000000
  75. /* 8 bit correction per 528 Byte sector */
  76. #define CSOR_NAND_ECC_MODE_8 0x10000000
  77. /* Enable ECC Decoder */
  78. #define CSOR_NAND_ECC_DEC_EN 0x04000000
  79. /* Row Address Length */
  80. #define CSOR_NAND_RAL_MASK 0x01800000
  81. #define CSOR_NAND_RAL_SHIFT 20
  82. #define CSOR_NAND_RAL_1 0x00000000
  83. #define CSOR_NAND_RAL_2 0x00800000
  84. #define CSOR_NAND_RAL_3 0x01000000
  85. #define CSOR_NAND_RAL_4 0x01800000
  86. /* Page Size 512b, 2k, 4k */
  87. #define CSOR_NAND_PGS_MASK 0x00180000
  88. #define CSOR_NAND_PGS_SHIFT 16
  89. #define CSOR_NAND_PGS_512 0x00000000
  90. #define CSOR_NAND_PGS_2K 0x00080000
  91. #define CSOR_NAND_PGS_4K 0x00100000
  92. #define CSOR_NAND_PGS_8K 0x00180000
  93. /* Spare region Size */
  94. #define CSOR_NAND_SPRZ_MASK 0x0000E000
  95. #define CSOR_NAND_SPRZ_SHIFT 13
  96. #define CSOR_NAND_SPRZ_16 0x00000000
  97. #define CSOR_NAND_SPRZ_64 0x00002000
  98. #define CSOR_NAND_SPRZ_128 0x00004000
  99. #define CSOR_NAND_SPRZ_210 0x00006000
  100. #define CSOR_NAND_SPRZ_218 0x00008000
  101. #define CSOR_NAND_SPRZ_224 0x0000A000
  102. #define CSOR_NAND_SPRZ_CSOR_EXT 0x0000C000
  103. /* Pages Per Block */
  104. #define CSOR_NAND_PB_MASK 0x00000700
  105. #define CSOR_NAND_PB_SHIFT 8
  106. #define CSOR_NAND_PB(n) ((LOG2(n) - 5) << CSOR_NAND_PB_SHIFT)
  107. /* Time for Read Enable High to Output High Impedance */
  108. #define CSOR_NAND_TRHZ_MASK 0x0000001C
  109. #define CSOR_NAND_TRHZ_SHIFT 2
  110. #define CSOR_NAND_TRHZ_20 0x00000000
  111. #define CSOR_NAND_TRHZ_40 0x00000004
  112. #define CSOR_NAND_TRHZ_60 0x00000008
  113. #define CSOR_NAND_TRHZ_80 0x0000000C
  114. #define CSOR_NAND_TRHZ_100 0x00000010
  115. /* Buffer control disable */
  116. #define CSOR_NAND_BCTLD 0x00000001
  117. /*
  118. * Chip Select Option Register - NOR Flash Mode
  119. */
  120. /* Enable Address shift Mode */
  121. #define CSOR_NOR_ADM_SHFT_MODE_EN 0x80000000
  122. /* Page Read Enable from NOR device */
  123. #define CSOR_NOR_PGRD_EN 0x10000000
  124. /* AVD Toggle Enable during Burst Program */
  125. #define CSOR_NOR_AVD_TGL_PGM_EN 0x01000000
  126. /* Address Data Multiplexing Shift */
  127. #define CSOR_NOR_ADM_MASK 0x0003E000
  128. #define CSOR_NOR_ADM_SHIFT_SHIFT 13
  129. #define CSOR_NOR_ADM_SHIFT(n) ((n) << CSOR_NOR_ADM_SHIFT_SHIFT)
  130. /* Type of the NOR device hooked */
  131. #define CSOR_NOR_NOR_MODE_AYSNC_NOR 0x00000000
  132. #define CSOR_NOR_NOR_MODE_AVD_NOR 0x00000020
  133. /* Time for Read Enable High to Output High Impedance */
  134. #define CSOR_NOR_TRHZ_MASK 0x0000001C
  135. #define CSOR_NOR_TRHZ_SHIFT 2
  136. #define CSOR_NOR_TRHZ_20 0x00000000
  137. #define CSOR_NOR_TRHZ_40 0x00000004
  138. #define CSOR_NOR_TRHZ_60 0x00000008
  139. #define CSOR_NOR_TRHZ_80 0x0000000C
  140. #define CSOR_NOR_TRHZ_100 0x00000010
  141. /* Buffer control disable */
  142. #define CSOR_NOR_BCTLD 0x00000001
  143. /*
  144. * Chip Select Option Register - GPCM Mode
  145. */
  146. /* GPCM Mode - Normal */
  147. #define CSOR_GPCM_GPMODE_NORMAL 0x00000000
  148. /* GPCM Mode - GenericASIC */
  149. #define CSOR_GPCM_GPMODE_ASIC 0x80000000
  150. /* Parity Mode odd/even */
  151. #define CSOR_GPCM_PARITY_EVEN 0x40000000
  152. /* Parity Checking enable/disable */
  153. #define CSOR_GPCM_PAR_EN 0x20000000
  154. /* GPCM Timeout Count */
  155. #define CSOR_GPCM_GPTO_MASK 0x0F000000
  156. #define CSOR_GPCM_GPTO_SHIFT 24
  157. #define CSOR_GPCM_GPTO(n) ((LOG2(n) - 8) << CSOR_GPCM_GPTO_SHIFT)
  158. /* GPCM External Access Termination mode for read access */
  159. #define CSOR_GPCM_RGETA_EXT 0x00080000
  160. /* GPCM External Access Termination mode for write access */
  161. #define CSOR_GPCM_WGETA_EXT 0x00040000
  162. /* Address Data Multiplexing Shift */
  163. #define CSOR_GPCM_ADM_MASK 0x0003E000
  164. #define CSOR_GPCM_ADM_SHIFT_SHIFT 13
  165. #define CSOR_GPCM_ADM_SHIFT(n) ((n) << CSOR_GPCM_ADM_SHIFT_SHIFT)
  166. /* Generic ASIC Parity error indication delay */
  167. #define CSOR_GPCM_GAPERRD_MASK 0x00000180
  168. #define CSOR_GPCM_GAPERRD_SHIFT 7
  169. #define CSOR_GPCM_GAPERRD(n) (((n) - 1) << CSOR_GPCM_GAPERRD_SHIFT)
  170. /* Time for Read Enable High to Output High Impedance */
  171. #define CSOR_GPCM_TRHZ_MASK 0x0000001C
  172. #define CSOR_GPCM_TRHZ_20 0x00000000
  173. #define CSOR_GPCM_TRHZ_40 0x00000004
  174. #define CSOR_GPCM_TRHZ_60 0x00000008
  175. #define CSOR_GPCM_TRHZ_80 0x0000000C
  176. #define CSOR_GPCM_TRHZ_100 0x00000010
  177. /* Buffer control disable */
  178. #define CSOR_GPCM_BCTLD 0x00000001
  179. /*
  180. * Flash Timing Registers (FTIM0 - FTIM2_CSn)
  181. */
  182. /*
  183. * FTIM0 - NAND Flash Mode
  184. */
  185. #define FTIM0_NAND 0x7EFF3F3F
  186. #define FTIM0_NAND_TCCST_SHIFT 25
  187. #define FTIM0_NAND_TCCST(n) ((n) << FTIM0_NAND_TCCST_SHIFT)
  188. #define FTIM0_NAND_TWP_SHIFT 16
  189. #define FTIM0_NAND_TWP(n) ((n) << FTIM0_NAND_TWP_SHIFT)
  190. #define FTIM0_NAND_TWCHT_SHIFT 8
  191. #define FTIM0_NAND_TWCHT(n) ((n) << FTIM0_NAND_TWCHT_SHIFT)
  192. #define FTIM0_NAND_TWH_SHIFT 0
  193. #define FTIM0_NAND_TWH(n) ((n) << FTIM0_NAND_TWH_SHIFT)
  194. /*
  195. * FTIM1 - NAND Flash Mode
  196. */
  197. #define FTIM1_NAND 0xFFFF3FFF
  198. #define FTIM1_NAND_TADLE_SHIFT 24
  199. #define FTIM1_NAND_TADLE(n) ((n) << FTIM1_NAND_TADLE_SHIFT)
  200. #define FTIM1_NAND_TWBE_SHIFT 16
  201. #define FTIM1_NAND_TWBE(n) ((n) << FTIM1_NAND_TWBE_SHIFT)
  202. #define FTIM1_NAND_TRR_SHIFT 8
  203. #define FTIM1_NAND_TRR(n) ((n) << FTIM1_NAND_TRR_SHIFT)
  204. #define FTIM1_NAND_TRP_SHIFT 0
  205. #define FTIM1_NAND_TRP(n) ((n) << FTIM1_NAND_TRP_SHIFT)
  206. /*
  207. * FTIM2 - NAND Flash Mode
  208. */
  209. #define FTIM2_NAND 0x1FE1F8FF
  210. #define FTIM2_NAND_TRAD_SHIFT 21
  211. #define FTIM2_NAND_TRAD(n) ((n) << FTIM2_NAND_TRAD_SHIFT)
  212. #define FTIM2_NAND_TREH_SHIFT 11
  213. #define FTIM2_NAND_TREH(n) ((n) << FTIM2_NAND_TREH_SHIFT)
  214. #define FTIM2_NAND_TWHRE_SHIFT 0
  215. #define FTIM2_NAND_TWHRE(n) ((n) << FTIM2_NAND_TWHRE_SHIFT)
  216. /*
  217. * FTIM3 - NAND Flash Mode
  218. */
  219. #define FTIM3_NAND 0xFF000000
  220. #define FTIM3_NAND_TWW_SHIFT 24
  221. #define FTIM3_NAND_TWW(n) ((n) << FTIM3_NAND_TWW_SHIFT)
  222. /*
  223. * FTIM0 - NOR Flash Mode
  224. */
  225. #define FTIM0_NOR 0xF03F3F3F
  226. #define FTIM0_NOR_TACSE_SHIFT 28
  227. #define FTIM0_NOR_TACSE(n) ((n) << FTIM0_NOR_TACSE_SHIFT)
  228. #define FTIM0_NOR_TEADC_SHIFT 16
  229. #define FTIM0_NOR_TEADC(n) ((n) << FTIM0_NOR_TEADC_SHIFT)
  230. #define FTIM0_NOR_TAVDS_SHIFT 8
  231. #define FTIM0_NOR_TAVDS(n) ((n) << FTIM0_NOR_TAVDS_SHIFT)
  232. #define FTIM0_NOR_TEAHC_SHIFT 0
  233. #define FTIM0_NOR_TEAHC(n) ((n) << FTIM0_NOR_TEAHC_SHIFT)
  234. /*
  235. * FTIM1 - NOR Flash Mode
  236. */
  237. #define FTIM1_NOR 0xFF003F3F
  238. #define FTIM1_NOR_TACO_SHIFT 24
  239. #define FTIM1_NOR_TACO(n) ((n) << FTIM1_NOR_TACO_SHIFT)
  240. #define FTIM1_NOR_TRAD_NOR_SHIFT 8
  241. #define FTIM1_NOR_TRAD_NOR(n) ((n) << FTIM1_NOR_TRAD_NOR_SHIFT)
  242. #define FTIM1_NOR_TSEQRAD_NOR_SHIFT 0
  243. #define FTIM1_NOR_TSEQRAD_NOR(n) ((n) << FTIM1_NOR_TSEQRAD_NOR_SHIFT)
  244. /*
  245. * FTIM2 - NOR Flash Mode
  246. */
  247. #define FTIM2_NOR 0x0F3CFCFF
  248. #define FTIM2_NOR_TCS_SHIFT 24
  249. #define FTIM2_NOR_TCS(n) ((n) << FTIM2_NOR_TCS_SHIFT)
  250. #define FTIM2_NOR_TCH_SHIFT 18
  251. #define FTIM2_NOR_TCH(n) ((n) << FTIM2_NOR_TCH_SHIFT)
  252. #define FTIM2_NOR_TWPH_SHIFT 10
  253. #define FTIM2_NOR_TWPH(n) ((n) << FTIM2_NOR_TWPH_SHIFT)
  254. #define FTIM2_NOR_TWP_SHIFT 0
  255. #define FTIM2_NOR_TWP(n) ((n) << FTIM2_NOR_TWP_SHIFT)
  256. /*
  257. * FTIM0 - Normal GPCM Mode
  258. */
  259. #define FTIM0_GPCM 0xF03F3F3F
  260. #define FTIM0_GPCM_TACSE_SHIFT 28
  261. #define FTIM0_GPCM_TACSE(n) ((n) << FTIM0_GPCM_TACSE_SHIFT)
  262. #define FTIM0_GPCM_TEADC_SHIFT 16
  263. #define FTIM0_GPCM_TEADC(n) ((n) << FTIM0_GPCM_TEADC_SHIFT)
  264. #define FTIM0_GPCM_TAVDS_SHIFT 8
  265. #define FTIM0_GPCM_TAVDS(n) ((n) << FTIM0_GPCM_TAVDS_SHIFT)
  266. #define FTIM0_GPCM_TEAHC_SHIFT 0
  267. #define FTIM0_GPCM_TEAHC(n) ((n) << FTIM0_GPCM_TEAHC_SHIFT)
  268. /*
  269. * FTIM1 - Normal GPCM Mode
  270. */
  271. #define FTIM1_GPCM 0xFF003F00
  272. #define FTIM1_GPCM_TACO_SHIFT 24
  273. #define FTIM1_GPCM_TACO(n) ((n) << FTIM1_GPCM_TACO_SHIFT)
  274. #define FTIM1_GPCM_TRAD_SHIFT 8
  275. #define FTIM1_GPCM_TRAD(n) ((n) << FTIM1_GPCM_TRAD_SHIFT)
  276. /*
  277. * FTIM2 - Normal GPCM Mode
  278. */
  279. #define FTIM2_GPCM 0x0F3C00FF
  280. #define FTIM2_GPCM_TCS_SHIFT 24
  281. #define FTIM2_GPCM_TCS(n) ((n) << FTIM2_GPCM_TCS_SHIFT)
  282. #define FTIM2_GPCM_TCH_SHIFT 18
  283. #define FTIM2_GPCM_TCH(n) ((n) << FTIM2_GPCM_TCH_SHIFT)
  284. #define FTIM2_GPCM_TWP_SHIFT 0
  285. #define FTIM2_GPCM_TWP(n) ((n) << FTIM2_GPCM_TWP_SHIFT)
  286. /*
  287. * Ready Busy Status Register (RB_STAT)
  288. */
  289. /* CSn is READY */
  290. #define IFC_RB_STAT_READY_CS0 0x80000000
  291. #define IFC_RB_STAT_READY_CS1 0x40000000
  292. #define IFC_RB_STAT_READY_CS2 0x20000000
  293. #define IFC_RB_STAT_READY_CS3 0x10000000
  294. /*
  295. * General Control Register (GCR)
  296. */
  297. #define IFC_GCR_MASK 0x8000F800
  298. /* reset all IFC hardware */
  299. #define IFC_GCR_SOFT_RST_ALL 0x80000000
  300. /* Turnaroud Time of external buffer */
  301. #define IFC_GCR_TBCTL_TRN_TIME 0x0000F800
  302. #define IFC_GCR_TBCTL_TRN_TIME_SHIFT 11
  303. /*
  304. * Common Event and Error Status Register (CM_EVTER_STAT)
  305. */
  306. /* Chip select error */
  307. #define IFC_CM_EVTER_STAT_CSER 0x80000000
  308. /*
  309. * Common Event and Error Enable Register (CM_EVTER_EN)
  310. */
  311. /* Chip select error checking enable */
  312. #define IFC_CM_EVTER_EN_CSEREN 0x80000000
  313. /*
  314. * Common Event and Error Interrupt Enable Register (CM_EVTER_INTR_EN)
  315. */
  316. /* Chip select error interrupt enable */
  317. #define IFC_CM_EVTER_INTR_EN_CSERIREN 0x80000000
  318. /*
  319. * Common Transfer Error Attribute Register-0 (CM_ERATTR0)
  320. */
  321. /* transaction type of error Read/Write */
  322. #define IFC_CM_ERATTR0_ERTYP_READ 0x80000000
  323. #define IFC_CM_ERATTR0_ERAID 0x0FF00000
  324. #define IFC_CM_ERATTR0_ESRCID 0x0000FF00
  325. /*
  326. * Clock Control Register (CCR)
  327. */
  328. #define IFC_CCR_MASK 0x0F0F8800
  329. /* Clock division ratio */
  330. #define IFC_CCR_CLK_DIV_MASK 0x0F000000
  331. #define IFC_CCR_CLK_DIV_SHIFT 24
  332. #define IFC_CCR_CLK_DIV(n) ((n-1) << IFC_CCR_CLK_DIV_SHIFT)
  333. /* IFC Clock Delay */
  334. #define IFC_CCR_CLK_DLY_MASK 0x000F0000
  335. #define IFC_CCR_CLK_DLY_SHIFT 16
  336. #define IFC_CCR_CLK_DLY(n) ((n) << IFC_CCR_CLK_DLY_SHIFT)
  337. /* Invert IFC clock before sending out */
  338. #define IFC_CCR_INV_CLK_EN 0x00008000
  339. /* Fedback IFC Clock */
  340. #define IFC_CCR_FB_IFC_CLK_SEL 0x00000800
  341. /*
  342. * Clock Status Register (CSR)
  343. */
  344. /* Clk is stable */
  345. #define IFC_CSR_CLK_STAT_STABLE 0x80000000
  346. /*
  347. * IFC_NAND Machine Specific Registers
  348. */
  349. /*
  350. * NAND Configuration Register (NCFGR)
  351. */
  352. /* Auto Boot Mode */
  353. #define IFC_NAND_NCFGR_BOOT 0x80000000
  354. /* SRAM INIT EN */
  355. #define IFC_NAND_SRAM_INIT_EN 0x20000000
  356. /* Addressing Mode-ROW0+n/COL0 */
  357. #define IFC_NAND_NCFGR_ADDR_MODE_RC0 0x00000000
  358. /* Addressing Mode-ROW0+n/COL0+n */
  359. #define IFC_NAND_NCFGR_ADDR_MODE_RC1 0x00400000
  360. /* Number of loop iterations of FIR sequences for multi page operations */
  361. #define IFC_NAND_NCFGR_NUM_LOOP_MASK 0x0000F000
  362. #define IFC_NAND_NCFGR_NUM_LOOP_SHIFT 12
  363. #define IFC_NAND_NCFGR_NUM_LOOP(n) ((n) << IFC_NAND_NCFGR_NUM_LOOP_SHIFT)
  364. /* Number of wait cycles */
  365. #define IFC_NAND_NCFGR_NUM_WAIT_MASK 0x000000FF
  366. #define IFC_NAND_NCFGR_NUM_WAIT_SHIFT 0
  367. /*
  368. * NAND Flash Command Registers (NAND_FCR0/NAND_FCR1)
  369. */
  370. /* General purpose FCM flash command bytes CMD0-CMD7 */
  371. #define IFC_NAND_FCR0_CMD0 0xFF000000
  372. #define IFC_NAND_FCR0_CMD0_SHIFT 24
  373. #define IFC_NAND_FCR0_CMD1 0x00FF0000
  374. #define IFC_NAND_FCR0_CMD1_SHIFT 16
  375. #define IFC_NAND_FCR0_CMD2 0x0000FF00
  376. #define IFC_NAND_FCR0_CMD2_SHIFT 8
  377. #define IFC_NAND_FCR0_CMD3 0x000000FF
  378. #define IFC_NAND_FCR0_CMD3_SHIFT 0
  379. #define IFC_NAND_FCR1_CMD4 0xFF000000
  380. #define IFC_NAND_FCR1_CMD4_SHIFT 24
  381. #define IFC_NAND_FCR1_CMD5 0x00FF0000
  382. #define IFC_NAND_FCR1_CMD5_SHIFT 16
  383. #define IFC_NAND_FCR1_CMD6 0x0000FF00
  384. #define IFC_NAND_FCR1_CMD6_SHIFT 8
  385. #define IFC_NAND_FCR1_CMD7 0x000000FF
  386. #define IFC_NAND_FCR1_CMD7_SHIFT 0
  387. /*
  388. * Flash ROW and COL Address Register (ROWn, COLn)
  389. */
  390. /* Main/spare region locator */
  391. #define IFC_NAND_COL_MS 0x80000000
  392. /* Column Address */
  393. #define IFC_NAND_COL_CA_MASK 0x00000FFF
  394. /*
  395. * NAND Flash Byte Count Register (NAND_BC)
  396. */
  397. /* Byte Count for read/Write */
  398. #define IFC_NAND_BC 0x000001FF
  399. /*
  400. * NAND Flash Instruction Registers (NAND_FIR0/NAND_FIR1/NAND_FIR2)
  401. */
  402. /* NAND Machine specific opcodes OP0-OP14*/
  403. #define IFC_NAND_FIR0_OP0 0xFC000000
  404. #define IFC_NAND_FIR0_OP0_SHIFT 26
  405. #define IFC_NAND_FIR0_OP1 0x03F00000
  406. #define IFC_NAND_FIR0_OP1_SHIFT 20
  407. #define IFC_NAND_FIR0_OP2 0x000FC000
  408. #define IFC_NAND_FIR0_OP2_SHIFT 14
  409. #define IFC_NAND_FIR0_OP3 0x00003F00
  410. #define IFC_NAND_FIR0_OP3_SHIFT 8
  411. #define IFC_NAND_FIR0_OP4 0x000000FC
  412. #define IFC_NAND_FIR0_OP4_SHIFT 2
  413. #define IFC_NAND_FIR1_OP5 0xFC000000
  414. #define IFC_NAND_FIR1_OP5_SHIFT 26
  415. #define IFC_NAND_FIR1_OP6 0x03F00000
  416. #define IFC_NAND_FIR1_OP6_SHIFT 20
  417. #define IFC_NAND_FIR1_OP7 0x000FC000
  418. #define IFC_NAND_FIR1_OP7_SHIFT 14
  419. #define IFC_NAND_FIR1_OP8 0x00003F00
  420. #define IFC_NAND_FIR1_OP8_SHIFT 8
  421. #define IFC_NAND_FIR1_OP9 0x000000FC
  422. #define IFC_NAND_FIR1_OP9_SHIFT 2
  423. #define IFC_NAND_FIR2_OP10 0xFC000000
  424. #define IFC_NAND_FIR2_OP10_SHIFT 26
  425. #define IFC_NAND_FIR2_OP11 0x03F00000
  426. #define IFC_NAND_FIR2_OP11_SHIFT 20
  427. #define IFC_NAND_FIR2_OP12 0x000FC000
  428. #define IFC_NAND_FIR2_OP12_SHIFT 14
  429. #define IFC_NAND_FIR2_OP13 0x00003F00
  430. #define IFC_NAND_FIR2_OP13_SHIFT 8
  431. #define IFC_NAND_FIR2_OP14 0x000000FC
  432. #define IFC_NAND_FIR2_OP14_SHIFT 2
  433. /*
  434. * Instruction opcodes to be programmed
  435. * in FIR registers- 6bits
  436. */
  437. enum ifc_nand_fir_opcodes {
  438. IFC_FIR_OP_NOP,
  439. IFC_FIR_OP_CA0,
  440. IFC_FIR_OP_CA1,
  441. IFC_FIR_OP_CA2,
  442. IFC_FIR_OP_CA3,
  443. IFC_FIR_OP_RA0,
  444. IFC_FIR_OP_RA1,
  445. IFC_FIR_OP_RA2,
  446. IFC_FIR_OP_RA3,
  447. IFC_FIR_OP_CMD0,
  448. IFC_FIR_OP_CMD1,
  449. IFC_FIR_OP_CMD2,
  450. IFC_FIR_OP_CMD3,
  451. IFC_FIR_OP_CMD4,
  452. IFC_FIR_OP_CMD5,
  453. IFC_FIR_OP_CMD6,
  454. IFC_FIR_OP_CMD7,
  455. IFC_FIR_OP_CW0,
  456. IFC_FIR_OP_CW1,
  457. IFC_FIR_OP_CW2,
  458. IFC_FIR_OP_CW3,
  459. IFC_FIR_OP_CW4,
  460. IFC_FIR_OP_CW5,
  461. IFC_FIR_OP_CW6,
  462. IFC_FIR_OP_CW7,
  463. IFC_FIR_OP_WBCD,
  464. IFC_FIR_OP_RBCD,
  465. IFC_FIR_OP_BTRD,
  466. IFC_FIR_OP_RDSTAT,
  467. IFC_FIR_OP_NWAIT,
  468. IFC_FIR_OP_WFR,
  469. IFC_FIR_OP_SBRD,
  470. IFC_FIR_OP_UA,
  471. IFC_FIR_OP_RB,
  472. };
  473. /*
  474. * NAND Chip Select Register (NAND_CSEL)
  475. */
  476. #define IFC_NAND_CSEL 0x0C000000
  477. #define IFC_NAND_CSEL_SHIFT 26
  478. #define IFC_NAND_CSEL_CS0 0x00000000
  479. #define IFC_NAND_CSEL_CS1 0x04000000
  480. #define IFC_NAND_CSEL_CS2 0x08000000
  481. #define IFC_NAND_CSEL_CS3 0x0C000000
  482. /*
  483. * NAND Operation Sequence Start (NANDSEQ_STRT)
  484. */
  485. /* NAND Flash Operation Start */
  486. #define IFC_NAND_SEQ_STRT_FIR_STRT 0x80000000
  487. /* Automatic Erase */
  488. #define IFC_NAND_SEQ_STRT_AUTO_ERS 0x00800000
  489. /* Automatic Program */
  490. #define IFC_NAND_SEQ_STRT_AUTO_PGM 0x00100000
  491. /* Automatic Copyback */
  492. #define IFC_NAND_SEQ_STRT_AUTO_CPB 0x00020000
  493. /* Automatic Read Operation */
  494. #define IFC_NAND_SEQ_STRT_AUTO_RD 0x00004000
  495. /* Automatic Status Read */
  496. #define IFC_NAND_SEQ_STRT_AUTO_STAT_RD 0x00000800
  497. /*
  498. * NAND Event and Error Status Register (NAND_EVTER_STAT)
  499. */
  500. /* Operation Complete */
  501. #define IFC_NAND_EVTER_STAT_OPC 0x80000000
  502. /* Flash Timeout Error */
  503. #define IFC_NAND_EVTER_STAT_FTOER 0x08000000
  504. /* Write Protect Error */
  505. #define IFC_NAND_EVTER_STAT_WPER 0x04000000
  506. /* ECC Error */
  507. #define IFC_NAND_EVTER_STAT_ECCER 0x02000000
  508. /* RCW Load Done */
  509. #define IFC_NAND_EVTER_STAT_RCW_DN 0x00008000
  510. /* Boot Loadr Done */
  511. #define IFC_NAND_EVTER_STAT_BOOT_DN 0x00004000
  512. /* Bad Block Indicator search select */
  513. #define IFC_NAND_EVTER_STAT_BBI_SRCH_SE 0x00000800
  514. /*
  515. * NAND Flash Page Read Completion Event Status Register
  516. * (PGRDCMPL_EVT_STAT)
  517. */
  518. #define PGRDCMPL_EVT_STAT_MASK 0xFFFF0000
  519. /* Small Page 0-15 Done */
  520. #define PGRDCMPL_EVT_STAT_SECTION_SP(n) (1 << (31 - (n)))
  521. /* Large Page(2K) 0-3 Done */
  522. #define PGRDCMPL_EVT_STAT_LP_2K(n) (0xF << (28 - (n)*4))
  523. /* Large Page(4K) 0-1 Done */
  524. #define PGRDCMPL_EVT_STAT_LP_4K(n) (0xFF << (24 - (n)*8))
  525. /*
  526. * NAND Event and Error Enable Register (NAND_EVTER_EN)
  527. */
  528. /* Operation complete event enable */
  529. #define IFC_NAND_EVTER_EN_OPC_EN 0x80000000
  530. /* Page read complete event enable */
  531. #define IFC_NAND_EVTER_EN_PGRDCMPL_EN 0x20000000
  532. /* Flash Timeout error enable */
  533. #define IFC_NAND_EVTER_EN_FTOER_EN 0x08000000
  534. /* Write Protect error enable */
  535. #define IFC_NAND_EVTER_EN_WPER_EN 0x04000000
  536. /* ECC error logging enable */
  537. #define IFC_NAND_EVTER_EN_ECCER_EN 0x02000000
  538. /*
  539. * NAND Event and Error Interrupt Enable Register (NAND_EVTER_INTR_EN)
  540. */
  541. /* Enable interrupt for operation complete */
  542. #define IFC_NAND_EVTER_INTR_OPCIR_EN 0x80000000
  543. /* Enable interrupt for Page read complete */
  544. #define IFC_NAND_EVTER_INTR_PGRDCMPLIR_EN 0x20000000
  545. /* Enable interrupt for Flash timeout error */
  546. #define IFC_NAND_EVTER_INTR_FTOERIR_EN 0x08000000
  547. /* Enable interrupt for Write protect error */
  548. #define IFC_NAND_EVTER_INTR_WPERIR_EN 0x04000000
  549. /* Enable interrupt for ECC error*/
  550. #define IFC_NAND_EVTER_INTR_ECCERIR_EN 0x02000000
  551. /*
  552. * NAND Transfer Error Attribute Register-0 (NAND_ERATTR0)
  553. */
  554. #define IFC_NAND_ERATTR0_MASK 0x0C080000
  555. /* Error on CS0-3 for NAND */
  556. #define IFC_NAND_ERATTR0_ERCS_CS0 0x00000000
  557. #define IFC_NAND_ERATTR0_ERCS_CS1 0x04000000
  558. #define IFC_NAND_ERATTR0_ERCS_CS2 0x08000000
  559. #define IFC_NAND_ERATTR0_ERCS_CS3 0x0C000000
  560. /* Transaction type of error Read/Write */
  561. #define IFC_NAND_ERATTR0_ERTTYPE_READ 0x00080000
  562. /*
  563. * NAND Flash Status Register (NAND_FSR)
  564. */
  565. /* First byte of data read from read status op */
  566. #define IFC_NAND_NFSR_RS0 0xFF000000
  567. /* Second byte of data read from read status op */
  568. #define IFC_NAND_NFSR_RS1 0x00FF0000
  569. /*
  570. * ECC Error Status Registers (ECCSTAT0-ECCSTAT3)
  571. */
  572. /* Number of ECC errors on sector n (n = 0-15) */
  573. #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_MASK 0x0F000000
  574. #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_SHIFT 24
  575. #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_MASK 0x000F0000
  576. #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_SHIFT 16
  577. #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_MASK 0x00000F00
  578. #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_SHIFT 8
  579. #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_MASK 0x0000000F
  580. #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_SHIFT 0
  581. #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_MASK 0x0F000000
  582. #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_SHIFT 24
  583. #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_MASK 0x000F0000
  584. #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_SHIFT 16
  585. #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_MASK 0x00000F00
  586. #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_SHIFT 8
  587. #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_MASK 0x0000000F
  588. #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_SHIFT 0
  589. #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_MASK 0x0F000000
  590. #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_SHIFT 24
  591. #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_MASK 0x000F0000
  592. #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_SHIFT 16
  593. #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_MASK 0x00000F00
  594. #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_SHIFT 8
  595. #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_MASK 0x0000000F
  596. #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_SHIFT 0
  597. #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_MASK 0x0F000000
  598. #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_SHIFT 24
  599. #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_MASK 0x000F0000
  600. #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_SHIFT 16
  601. #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_MASK 0x00000F00
  602. #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_SHIFT 8
  603. #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_MASK 0x0000000F
  604. #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_SHIFT 0
  605. /*
  606. * NAND Control Register (NANDCR)
  607. */
  608. #define IFC_NAND_NCR_FTOCNT_MASK 0x1E000000
  609. #define IFC_NAND_NCR_FTOCNT_SHIFT 25
  610. #define IFC_NAND_NCR_FTOCNT(n) ((LOG2(n) - 8) << IFC_NAND_NCR_FTOCNT_SHIFT)
  611. /*
  612. * NAND_AUTOBOOT_TRGR
  613. */
  614. /* Trigger RCW load */
  615. #define IFC_NAND_AUTOBOOT_TRGR_RCW_LD 0x80000000
  616. /* Trigget Auto Boot */
  617. #define IFC_NAND_AUTOBOOT_TRGR_BOOT_LD 0x20000000
  618. /*
  619. * NAND_MDR
  620. */
  621. /* 1st read data byte when opcode SBRD */
  622. #define IFC_NAND_MDR_RDATA0 0xFF000000
  623. /* 2nd read data byte when opcode SBRD */
  624. #define IFC_NAND_MDR_RDATA1 0x00FF0000
  625. /*
  626. * NOR Machine Specific Registers
  627. */
  628. /*
  629. * NOR Event and Error Status Register (NOR_EVTER_STAT)
  630. */
  631. /* NOR Command Sequence Operation Complete */
  632. #define IFC_NOR_EVTER_STAT_OPC_NOR 0x80000000
  633. /* Write Protect Error */
  634. #define IFC_NOR_EVTER_STAT_WPER 0x04000000
  635. /* Command Sequence Timeout Error */
  636. #define IFC_NOR_EVTER_STAT_STOER 0x01000000
  637. /*
  638. * NOR Event and Error Enable Register (NOR_EVTER_EN)
  639. */
  640. /* NOR Command Seq complete event enable */
  641. #define IFC_NOR_EVTER_EN_OPCEN_NOR 0x80000000
  642. /* Write Protect Error Checking Enable */
  643. #define IFC_NOR_EVTER_EN_WPEREN 0x04000000
  644. /* Timeout Error Enable */
  645. #define IFC_NOR_EVTER_EN_STOEREN 0x01000000
  646. /*
  647. * NOR Event and Error Interrupt Enable Register (NOR_EVTER_INTR_EN)
  648. */
  649. /* Enable interrupt for OPC complete */
  650. #define IFC_NOR_EVTER_INTR_OPCEN_NOR 0x80000000
  651. /* Enable interrupt for write protect error */
  652. #define IFC_NOR_EVTER_INTR_WPEREN 0x04000000
  653. /* Enable interrupt for timeout error */
  654. #define IFC_NOR_EVTER_INTR_STOEREN 0x01000000
  655. /*
  656. * NOR Transfer Error Attribute Register-0 (NOR_ERATTR0)
  657. */
  658. /* Source ID for error transaction */
  659. #define IFC_NOR_ERATTR0_ERSRCID 0xFF000000
  660. /* AXI ID for error transation */
  661. #define IFC_NOR_ERATTR0_ERAID 0x000FF000
  662. /* Chip select corresponds to NOR error */
  663. #define IFC_NOR_ERATTR0_ERCS_CS0 0x00000000
  664. #define IFC_NOR_ERATTR0_ERCS_CS1 0x00000010
  665. #define IFC_NOR_ERATTR0_ERCS_CS2 0x00000020
  666. #define IFC_NOR_ERATTR0_ERCS_CS3 0x00000030
  667. /* Type of transaction read/write */
  668. #define IFC_NOR_ERATTR0_ERTYPE_READ 0x00000001
  669. /*
  670. * NOR Transfer Error Attribute Register-2 (NOR_ERATTR2)
  671. */
  672. #define IFC_NOR_ERATTR2_ER_NUM_PHASE_EXP 0x000F0000
  673. #define IFC_NOR_ERATTR2_ER_NUM_PHASE_PER 0x00000F00
  674. /*
  675. * NOR Control Register (NORCR)
  676. */
  677. #define IFC_NORCR_MASK 0x0F0F0000
  678. /* No. of Address/Data Phase */
  679. #define IFC_NORCR_NUM_PHASE_MASK 0x0F000000
  680. #define IFC_NORCR_NUM_PHASE_SHIFT 24
  681. #define IFC_NORCR_NUM_PHASE(n) ((n-1) << IFC_NORCR_NUM_PHASE_SHIFT)
  682. /* Sequence Timeout Count */
  683. #define IFC_NORCR_STOCNT_MASK 0x000F0000
  684. #define IFC_NORCR_STOCNT_SHIFT 16
  685. #define IFC_NORCR_STOCNT(n) ((LOG2(n) - 8) << IFC_NORCR_STOCNT_SHIFT)
  686. /*
  687. * GPCM Machine specific registers
  688. */
  689. /*
  690. * GPCM Event and Error Status Register (GPCM_EVTER_STAT)
  691. */
  692. /* Timeout error */
  693. #define IFC_GPCM_EVTER_STAT_TOER 0x04000000
  694. /* Parity error */
  695. #define IFC_GPCM_EVTER_STAT_PER 0x01000000
  696. /*
  697. * GPCM Event and Error Enable Register (GPCM_EVTER_EN)
  698. */
  699. /* Timeout error enable */
  700. #define IFC_GPCM_EVTER_EN_TOER_EN 0x04000000
  701. /* Parity error enable */
  702. #define IFC_GPCM_EVTER_EN_PER_EN 0x01000000
  703. /*
  704. * GPCM Event and Error Interrupt Enable Register (GPCM_EVTER_INTR_EN)
  705. */
  706. /* Enable Interrupt for timeout error */
  707. #define IFC_GPCM_EEIER_TOERIR_EN 0x04000000
  708. /* Enable Interrupt for Parity error */
  709. #define IFC_GPCM_EEIER_PERIR_EN 0x01000000
  710. /*
  711. * GPCM Transfer Error Attribute Register-0 (GPCM_ERATTR0)
  712. */
  713. /* Source ID for error transaction */
  714. #define IFC_GPCM_ERATTR0_ERSRCID 0xFF000000
  715. /* AXI ID for error transaction */
  716. #define IFC_GPCM_ERATTR0_ERAID 0x000FF000
  717. /* Chip select corresponds to GPCM error */
  718. #define IFC_GPCM_ERATTR0_ERCS_CS0 0x00000000
  719. #define IFC_GPCM_ERATTR0_ERCS_CS1 0x00000040
  720. #define IFC_GPCM_ERATTR0_ERCS_CS2 0x00000080
  721. #define IFC_GPCM_ERATTR0_ERCS_CS3 0x000000C0
  722. /* Type of transaction read/Write */
  723. #define IFC_GPCM_ERATTR0_ERTYPE_READ 0x00000001
  724. /*
  725. * GPCM Transfer Error Attribute Register-2 (GPCM_ERATTR2)
  726. */
  727. /* On which beat of address/data parity error is observed */
  728. #define IFC_GPCM_ERATTR2_PERR_BEAT 0x00000C00
  729. /* Parity Error on byte */
  730. #define IFC_GPCM_ERATTR2_PERR_BYTE 0x000000F0
  731. /* Parity Error reported in addr or data phase */
  732. #define IFC_GPCM_ERATTR2_PERR_DATA_PHASE 0x00000001
  733. /*
  734. * GPCM Status Register (GPCM_STAT)
  735. */
  736. #define IFC_GPCM_STAT_BSY 0x80000000 /* GPCM is busy */
  737. #ifndef __ASSEMBLY__
  738. #include <asm/io.h>
  739. extern void print_ifc_regs(void);
  740. extern void init_early_memctl_regs(void);
  741. void init_final_memctl_regs(void);
  742. #define IFC_RREGS_4KOFFSET (4*1024)
  743. #define IFC_RREGS_64KOFFSET (64*1024)
  744. #define IFC_FCM_BASE_ADDR \
  745. ((struct fsl_ifc_fcm *)CONFIG_SYS_IFC_ADDR)
  746. #define get_ifc_cspr_ext(i) \
  747. (ifc_in32(&(IFC_FCM_BASE_ADDR)->cspr_cs[i].cspr_ext))
  748. #define get_ifc_cspr(i) \
  749. (ifc_in32(&(IFC_FCM_BASE_ADDR)->cspr_cs[i].cspr))
  750. #define get_ifc_csor_ext(i) \
  751. (ifc_in32(&(IFC_FCM_BASE_ADDR)->csor_cs[i].csor_ext))
  752. #define get_ifc_csor(i) \
  753. (ifc_in32(&(IFC_FCM_BASE_ADDR)->csor_cs[i].csor))
  754. #define get_ifc_amask(i) \
  755. (ifc_in32(&(IFC_FCM_BASE_ADDR)->amask_cs[i].amask))
  756. #define get_ifc_ftim(i, j) \
  757. (ifc_in32(&(IFC_FCM_BASE_ADDR)->ftim_cs[i].ftim[j]))
  758. #define set_ifc_cspr_ext(i, v) \
  759. (ifc_out32(&(IFC_FCM_BASE_ADDR)->cspr_cs[i].cspr_ext, v))
  760. #define set_ifc_cspr(i, v) \
  761. (ifc_out32(&(IFC_FCM_BASE_ADDR)->cspr_cs[i].cspr, v))
  762. #define set_ifc_csor_ext(i, v) \
  763. (ifc_out32(&(IFC_FCM_BASE_ADDR)->csor_cs[i].csor_ext, v))
  764. #define set_ifc_csor(i, v) \
  765. (ifc_out32(&(IFC_FCM_BASE_ADDR)->csor_cs[i].csor, v))
  766. #define set_ifc_amask(i, v) \
  767. (ifc_out32(&(IFC_FCM_BASE_ADDR)->amask_cs[i].amask, v))
  768. #define set_ifc_ftim(i, j, v) \
  769. (ifc_out32(&(IFC_FCM_BASE_ADDR)->ftim_cs[i].ftim[j], v))
  770. enum ifc_chip_sel {
  771. IFC_CS0,
  772. IFC_CS1,
  773. IFC_CS2,
  774. IFC_CS3,
  775. IFC_CS4,
  776. IFC_CS5,
  777. IFC_CS6,
  778. IFC_CS7,
  779. };
  780. enum ifc_ftims {
  781. IFC_FTIM0,
  782. IFC_FTIM1,
  783. IFC_FTIM2,
  784. IFC_FTIM3,
  785. };
  786. /*
  787. * IFC Controller NAND Machine registers
  788. */
  789. struct fsl_ifc_nand {
  790. u32 ncfgr;
  791. u32 res1[0x4];
  792. u32 nand_fcr0;
  793. u32 nand_fcr1;
  794. u32 res2[0x8];
  795. u32 row0;
  796. u32 res3;
  797. u32 col0;
  798. u32 res4;
  799. u32 row1;
  800. u32 res5;
  801. u32 col1;
  802. u32 res6;
  803. u32 row2;
  804. u32 res7;
  805. u32 col2;
  806. u32 res8;
  807. u32 row3;
  808. u32 res9;
  809. u32 col3;
  810. u32 res10[0x24];
  811. u32 nand_fbcr;
  812. u32 res11;
  813. u32 nand_fir0;
  814. u32 nand_fir1;
  815. u32 nand_fir2;
  816. u32 res12[0x10];
  817. u32 nand_csel;
  818. u32 res13;
  819. u32 nandseq_strt;
  820. u32 res14;
  821. u32 nand_evter_stat;
  822. u32 res15;
  823. u32 pgrdcmpl_evt_stat;
  824. u32 res16[0x2];
  825. u32 nand_evter_en;
  826. u32 res17[0x2];
  827. u32 nand_evter_intr_en;
  828. u32 nand_vol_addr_stat;
  829. u32 res18;
  830. u32 nand_erattr0;
  831. u32 nand_erattr1;
  832. u32 res19[0x10];
  833. u32 nand_fsr;
  834. u32 res20[0x1];
  835. u32 nand_eccstat[8];
  836. u32 res21[0x1c];
  837. u32 nanndcr;
  838. u32 res22[0x2];
  839. u32 nand_autoboot_trgr;
  840. u32 res23;
  841. u32 nand_mdr;
  842. u32 res24[0x1c];
  843. u32 nand_dll_lowcfg0;
  844. u32 nand_dll_lowcfg1;
  845. u32 res25;
  846. u32 nand_dll_lowstat;
  847. u32 res26[0x3C];
  848. };
  849. /*
  850. * IFC controller NOR Machine registers
  851. */
  852. struct fsl_ifc_nor {
  853. u32 nor_evter_stat;
  854. u32 res1[0x2];
  855. u32 nor_evter_en;
  856. u32 res2[0x2];
  857. u32 nor_evter_intr_en;
  858. u32 res3[0x2];
  859. u32 nor_erattr0;
  860. u32 nor_erattr1;
  861. u32 nor_erattr2;
  862. u32 res4[0x4];
  863. u32 norcr;
  864. u32 res5[0xEF];
  865. };
  866. /*
  867. * IFC controller GPCM Machine registers
  868. */
  869. struct fsl_ifc_gpcm {
  870. u32 gpcm_evter_stat;
  871. u32 res1[0x2];
  872. u32 gpcm_evter_en;
  873. u32 res2[0x2];
  874. u32 gpcm_evter_intr_en;
  875. u32 res3[0x2];
  876. u32 gpcm_erattr0;
  877. u32 gpcm_erattr1;
  878. u32 gpcm_erattr2;
  879. u32 gpcm_stat;
  880. };
  881. #ifdef CONFIG_SYS_FSL_IFC_BANK_COUNT
  882. #if (CONFIG_SYS_FSL_IFC_BANK_COUNT <= 8)
  883. #define IFC_CSPR_REG_LEN 148
  884. #define IFC_AMASK_REG_LEN 144
  885. #define IFC_CSOR_REG_LEN 144
  886. #define IFC_FTIM_REG_LEN 576
  887. #define IFC_CSPR_USED_LEN sizeof(struct fsl_ifc_cspr) * \
  888. CONFIG_SYS_FSL_IFC_BANK_COUNT
  889. #define IFC_AMASK_USED_LEN sizeof(struct fsl_ifc_amask) * \
  890. CONFIG_SYS_FSL_IFC_BANK_COUNT
  891. #define IFC_CSOR_USED_LEN sizeof(struct fsl_ifc_csor) * \
  892. CONFIG_SYS_FSL_IFC_BANK_COUNT
  893. #define IFC_FTIM_USED_LEN sizeof(struct fsl_ifc_ftim) * \
  894. CONFIG_SYS_FSL_IFC_BANK_COUNT
  895. #else
  896. #error IFC BANK count not vaild
  897. #endif
  898. #else
  899. #error IFC BANK count not defined
  900. #endif
  901. struct fsl_ifc_cspr {
  902. u32 cspr_ext;
  903. u32 cspr;
  904. u32 res;
  905. };
  906. struct fsl_ifc_amask {
  907. u32 amask;
  908. u32 res[0x2];
  909. };
  910. struct fsl_ifc_csor {
  911. u32 csor;
  912. u32 csor_ext;
  913. u32 res;
  914. };
  915. struct fsl_ifc_ftim {
  916. u32 ftim[4];
  917. u32 res[0x8];
  918. };
  919. /*
  920. * IFC Controller Global Registers
  921. * FCM - Flash control machine
  922. */
  923. struct fsl_ifc_fcm {
  924. u32 ifc_rev;
  925. u32 res1[0x2];
  926. struct fsl_ifc_cspr cspr_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
  927. u8 res2[IFC_CSPR_REG_LEN - IFC_CSPR_USED_LEN];
  928. struct fsl_ifc_amask amask_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
  929. u8 res3[IFC_AMASK_REG_LEN - IFC_AMASK_USED_LEN];
  930. struct fsl_ifc_csor csor_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
  931. u8 res4[IFC_CSOR_REG_LEN - IFC_CSOR_USED_LEN];
  932. struct fsl_ifc_ftim ftim_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
  933. u8 res5[IFC_FTIM_REG_LEN - IFC_FTIM_USED_LEN];
  934. u32 rb_stat;
  935. u32 rb_map;
  936. u32 wp_map;
  937. u32 ifc_gcr;
  938. u32 res7[0x2];
  939. u32 cm_evter_stat;
  940. u32 res8[0x2];
  941. u32 cm_evter_en;
  942. u32 res9[0x2];
  943. u32 cm_evter_intr_en;
  944. u32 res10[0x2];
  945. u32 cm_erattr0;
  946. u32 cm_erattr1;
  947. u32 res11[0x2];
  948. u32 ifc_ccr;
  949. u32 ifc_csr;
  950. u32 ddr_ccr_low;
  951. };
  952. struct fsl_ifc_runtime {
  953. struct fsl_ifc_nand ifc_nand;
  954. struct fsl_ifc_nor ifc_nor;
  955. struct fsl_ifc_gpcm ifc_gpcm;
  956. };
  957. struct fsl_ifc {
  958. struct fsl_ifc_fcm *gregs;
  959. struct fsl_ifc_runtime *rregs;
  960. };
  961. struct ifc_regs {
  962. const char *name;
  963. u32 pr;
  964. u32 pr_ext;
  965. u32 amask;
  966. u32 or;
  967. u32 ftim[4];
  968. u32 or_ext;
  969. u32 pr_final;
  970. u32 amask_final;
  971. };
  972. struct ifc_regs_info {
  973. struct ifc_regs *regs;
  974. u32 cs_size;
  975. };
  976. #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A002769
  977. #undef CSPR_MSEL_NOR
  978. #define CSPR_MSEL_NOR CSPR_MSEL_GPCM
  979. #endif
  980. #endif /* CONFIG_FSL_IFC */
  981. #endif /* __ASSEMBLY__ */
  982. #endif /* __FSL_IFC_H */