ftwdt010_wdt.h 3.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Watchdog driver for the FTWDT010 Watch Dog Driver
  4. *
  5. * (c) Copyright 2004 Faraday Technology Corp. (www.faraday-tech.com)
  6. * Based on sa1100_wdt.c by Oleg Drokin <green@crimea.edu>
  7. * Based on SoftDog driver by Alan Cox <alan@redhat.com>
  8. *
  9. * Copyright (C) 2011 Andes Technology Corporation
  10. * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
  11. *
  12. * 27/11/2004 Initial release, Faraday.
  13. * 12/01/2011 Port to u-boot, Macpaul Lin.
  14. */
  15. #ifndef __FTWDT010_H
  16. #define __FTWDT010_H
  17. struct ftwdt010_wdt {
  18. unsigned int wdcounter; /* Counter Reg - 0x00 */
  19. unsigned int wdload; /* Counter Auto Reload Reg - 0x04 */
  20. unsigned int wdrestart; /* Counter Restart Reg - 0x08 */
  21. unsigned int wdcr; /* Control Reg - 0x0c */
  22. unsigned int wdstatus; /* Status Reg - 0x10 */
  23. unsigned int wdclear; /* Timer Clear - 0x14 */
  24. unsigned int wdintrlen; /* Interrupt Length - 0x18 */
  25. };
  26. /*
  27. * WDLOAD - Counter Auto Reload Register
  28. * The Auto Reload Register is set to 0x03EF1480 (66Mhz) by default.
  29. * Which means in a 66MHz system, the period of Watch Dog timer reset is
  30. * one second.
  31. */
  32. #define FTWDT010_WDLOAD(x) ((x) & 0xffffffff)
  33. /*
  34. * WDRESTART - Watch Dog Timer Counter Restart Register
  35. * If writing 0x5AB9 to WDRESTART register, Watch Dog timer will
  36. * automatically reload WDLOAD to WDCOUNTER and restart counting.
  37. */
  38. #define FTWDT010_WDRESTART_MAGIC 0x5AB9
  39. /* WDCR - Watch Dog Timer Control Register */
  40. #define FTWDT010_WDCR_ENABLE (1 << 0)
  41. #define FTWDT010_WDCR_RST (1 << 1)
  42. #define FTWDT010_WDCR_INTR (1 << 2)
  43. /* FTWDT010_WDCR_EXT bit: Watch Dog Timer External Signal Enable */
  44. #define FTWDT010_WDCR_EXT (1 << 3)
  45. /* FTWDT010_WDCR_CLOCK bit: Clock Source: 0: PCLK, 1: EXTCLK.
  46. * The clock source PCLK cannot be gated when system sleeps, even if
  47. * WDCLOCK bit is turned on.
  48. *
  49. * Faraday's Watch Dog timer can be driven by an external clock. The
  50. * programmer just needs to write one to WdCR[WdClock] bit.
  51. *
  52. * Note: There is a limitation between EXTCLK and PCLK:
  53. * EXTCLK cycle time / PCLK cycle time > 2.
  54. * If the system does not need an external clock,
  55. * just keep WdCR[WdClock] bit in its default value.
  56. */
  57. #define FTWDT010_WDCR_CLOCK (1 << 4)
  58. /*
  59. * WDSTATUS - Watch Dog Timer Status Register
  60. * This bit is set when the counter reaches Zero
  61. */
  62. #define FTWDT010_WDSTATUS(x) ((x) & 0x1)
  63. /*
  64. * WDCLEAR - Watch Dog Timer Clear Register
  65. * Writing one to this register will clear WDSTATUS.
  66. */
  67. #define FTWDT010_WDCLEAR (1 << 0)
  68. /*
  69. * WDINTRLEN - Watch Dog Timer Interrupt Length
  70. * This register controls the duration length of wd_rst, wd_intr and wd_ext.
  71. * The default value is 0xFF.
  72. */
  73. #define FTWDT010_WDINTRLEN(x) ((x) & 0xff)
  74. /*
  75. * Variable timeout should be set in ms.
  76. * (CONFIG_SYS_CLK_FREQ/1000) equals 1 ms.
  77. * WDLOAD = timeout * TIMEOUT_FACTOR.
  78. */
  79. #define FTWDT010_TIMEOUT_FACTOR (CONFIG_SYS_CLK_FREQ / 1000) /* 1 ms */
  80. void ftwdt010_wdt_reset(void);
  81. void ftwdt010_wdt_disable(void);
  82. #endif /* __FTWDT010_H */