ftsdmc021.h 5.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2009 Faraday Technology
  4. * Po-Yu Chuang <ratbert@faraday-tech.com>
  5. *
  6. * (C) Copyright 2011 Andes Technology Corp
  7. * Macpaul Lin <macpaul@andestech.com>
  8. */
  9. /*
  10. * FTSDMC021 - SDRAM Controller
  11. */
  12. #ifndef __FTSDMC021_H
  13. #define __FTSDMC021_H
  14. #ifndef __ASSEMBLY__
  15. #include <linux/bitops.h>
  16. struct ftsdmc021 {
  17. unsigned int tp1; /* 0x00 - SDRAM Timing Parameter 1 */
  18. unsigned int tp2; /* 0x04 - SDRAM Timing Parameter 2 */
  19. unsigned int cr1; /* 0x08 - SDRAM Configuration Reg 1 */
  20. unsigned int cr2; /* 0x0c - SDRAM Configuration Reg 2 */
  21. unsigned int bank0_bsr; /* 0x10 - Ext. Bank Base/Size Reg 0 */
  22. unsigned int bank1_bsr; /* 0x14 - Ext. Bank Base/Size Reg 1 */
  23. unsigned int bank2_bsr; /* 0x18 - Ext. Bank Base/Size Reg 2 */
  24. unsigned int bank3_bsr; /* 0x1c - Ext. Bank Base/Size Reg 3 */
  25. unsigned int bank4_bsr; /* 0x20 - Ext. Bank Base/Size Reg 4 */
  26. unsigned int bank5_bsr; /* 0x24 - Ext. Bank Base/Size Reg 5 */
  27. unsigned int bank6_bsr; /* 0x28 - Ext. Bank Base/Size Reg 6 */
  28. unsigned int bank7_bsr; /* 0x2c - Ext. Bank Base/Size Reg 7 */
  29. unsigned int ragr; /* 0x30 - Read Arbitration Group Reg */
  30. unsigned int frr; /* 0x34 - Flush Request Register */
  31. unsigned int ebisr; /* 0x38 - EBI Support Register */
  32. unsigned int rsved[25]; /* 0x3c-0x9c - Reserved */
  33. unsigned int crr; /* 0x100 - Controller Revision Reg */
  34. unsigned int cfr; /* 0x104 - Controller Feature Reg */
  35. };
  36. #endif /* __ASSEMBLY__ */
  37. /*
  38. * Timing Parameter 1 Register
  39. */
  40. #define FTSDMC021_TP1_TCL(x) ((x) & 0x3) /* CAS Latency */
  41. #define FTSDMC021_TP1_TWR(x) (((x) & 0x3) << 4) /* W-Recovery Time */
  42. #define FTSDMC021_TP1_TRF(x) (((x) & 0xf) << 8) /* Auto-Refresh Cycle */
  43. #define FTSDMC021_TP1_TRCD(x) (((x) & 0x7) << 12) /* RAS-to-CAS Delay */
  44. #define FTSDMC021_TP1_TRP(x) (((x) & 0xf) << 16) /* Precharge Cycle */
  45. #define FTSDMC021_TP1_TRAS(x) (((x) & 0xf) << 20)
  46. /*
  47. * Timing Parameter 2 Register
  48. */
  49. #define FTSDMC021_TP2_REF_INTV(x) ((x) & 0xffff) /* Refresh interval */
  50. /* b(16:19) - Initial Refresh Times */
  51. #define FTSDMC021_TP2_INI_REFT(x) (((x) & 0xf) << 16)
  52. /* b(20:23) - Initial Pre-Charge Times */
  53. #define FTSDMC021_TP2_INI_PREC(x) (((x) & 0xf) << 20)
  54. /*
  55. * SDRAM Configuration Register 1
  56. */
  57. #define FTSDMC021_CR1_BNKSIZE(x) ((x) & 0xf) /* Bank Size */
  58. #define FTSDMC021_CR1_MBW(x) (((x) & 0x3) << 4) /* Bus Width */
  59. #define FTSDMC021_CR1_DSZ(x) (((x) & 0x7) << 8) /* SDRAM Size */
  60. #define FTSDMC021_CR1_DDW(x) (((x) & 0x3) << 12) /* Data Width */
  61. /* b(16) MA2T: Double Memory Address Cycle Enable */
  62. #define FTSDMC021_CR1_MA2T(x) (1 << 16)
  63. /* The value of b(0:3)CR1: 1M-512M, must be power of 2 */
  64. #define FTSDMC021_BANK_SIZE(x) (ffs(x) - 1)
  65. /*
  66. * Configuration Register 2
  67. */
  68. #define FTSDMC021_CR2_SREF (1 << 0) /* Self-Refresh Mode */
  69. #define FTSDMC021_CR2_PWDN (1 << 1) /* Power Down Operation Mode */
  70. #define FTSDMC021_CR2_ISMR (1 << 2) /* Start Set-Mode-Register */
  71. #define FTSDMC021_CR2_IREF (1 << 3) /* Init Refresh Start Flag */
  72. #define FTSDMC021_CR2_IPREC (1 << 4) /* Init Pre-Charge Start Flag */
  73. #define FTSDMC021_CR2_REFTYPE (1 << 5)
  74. /*
  75. * SDRAM External Bank Base/Size Register
  76. */
  77. #define FTSDMC021_BANK_ENABLE (1 << 12)
  78. /* 12-bit base address of external bank.
  79. * Default value is 0x800.
  80. * The 12-bit equals to the haddr[31:20] of AHB address bus. */
  81. #define FTSDMC021_BANK_BASE(x) ((x) & 0xfff)
  82. /*
  83. * Read Arbitration Grant Window Register
  84. */
  85. #define FTSDMC021_RAGR_CH1GW(x) (((x) & 0xff) << 0)
  86. #define FTSDMC021_RAGR_CH2GW(x) (((x) & 0xff) << 4)
  87. #define FTSDMC021_RAGR_CH3GW(x) (((x) & 0xff) << 8)
  88. #define FTSDMC021_RAGR_CH4GW(x) (((x) & 0xff) << 12)
  89. #define FTSDMC021_RAGR_CH5GW(x) (((x) & 0xff) << 16)
  90. #define FTSDMC021_RAGR_CH6GW(x) (((x) & 0xff) << 20)
  91. #define FTSDMC021_RAGR_CH7GW(x) (((x) & 0xff) << 24)
  92. #define FTSDMC021_RAGR_CH8GW(x) (((x) & 0xff) << 28)
  93. /*
  94. * Flush Request Register
  95. */
  96. #define FTSDMC021_FRR_FLUSHCHN(x) (((x) & 0x7) << 0)
  97. #define FTSDMC021_FRR_FLUSHCMPLT (1 << 3) /* Flush Req Flag */
  98. /*
  99. * External Bus Interface Support Register (EBISR)
  100. */
  101. #define FTSDMC021_EBISR_MR(x) ((x) & 0xfff) /* Far-end mode */
  102. #define FTSDMC021_EBISR_PRSMR (1 << 12) /* Pre-SMR */
  103. #define FTSDMC021_EBISR_POPREC (1 << 13)
  104. #define FTSDMC021_EBISR_POSMR (1 << 14) /* Post-SMR */
  105. /*
  106. * Controller Revision Register (CRR, Read Only)
  107. */
  108. #define FTSDMC021_CRR_REV_VER (((x) >> 0) & 0xff)
  109. #define FTSDMC021_CRR_MINOR_VER (((x) >> 8) & 0xff)
  110. #define FTSDMC021_CRR_MAJOR_VER (((x) >> 16) & 0xff)
  111. /*
  112. * Controller Feature Register (CFR, Read Only)
  113. */
  114. #define FTSDMC021_CFR_EBNK (((x) >> 0) & 0xf)
  115. #define FTSDMC021_CFR_CHN (((x) >> 8) & 0xf)
  116. #define FTSDMC021_CFR_EBI (((x) >> 16) & 0x1)
  117. #define FTSDMC021_CFR_CH1_FDEPTH (((x) >> 24) & 0x1)
  118. #define FTSDMC021_CFR_CH2_FDEPTH (((x) >> 25) & 0x1)
  119. #define FTSDMC021_CFR_CH3_FDEPTH (((x) >> 26) & 0x1)
  120. #define FTSDMC021_CFR_CH4_FDEPTH (((x) >> 27) & 0x1)
  121. #define FTSDMC021_CFR_CH5_FDEPTH (((x) >> 28) & 0x1)
  122. #define FTSDMC021_CFR_CH6_FDEPTH (((x) >> 29) & 0x1)
  123. #define FTSDMC021_CFR_CH7_FDEPTH (((x) >> 30) & 0x1)
  124. #define FTSDMC021_CFR_CH8_FDEPTH (((x) >> 31) & 0x1)
  125. #endif /* __FTSDMC021_H */