ftsdmc020.h 2.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2009 Faraday Technology
  4. * Po-Yu Chuang <ratbert@faraday-tech.com>
  5. */
  6. /*
  7. * SDRAM Controller
  8. */
  9. #ifndef __FTSDMC020_H
  10. #define __FTSDMC020_H
  11. #define FTSDMC020_OFFSET_TP0 0x00
  12. #define FTSDMC020_OFFSET_TP1 0x04
  13. #define FTSDMC020_OFFSET_CR 0x08
  14. #define FTSDMC020_OFFSET_BANK0_BSR 0x0C
  15. #define FTSDMC020_OFFSET_BANK1_BSR 0x10
  16. #define FTSDMC020_OFFSET_BANK2_BSR 0x14
  17. #define FTSDMC020_OFFSET_BANK3_BSR 0x18
  18. #define FTSDMC020_OFFSET_BANK4_BSR 0x1C
  19. #define FTSDMC020_OFFSET_BANK5_BSR 0x20
  20. #define FTSDMC020_OFFSET_BANK6_BSR 0x24
  21. #define FTSDMC020_OFFSET_BANK7_BSR 0x28
  22. #define FTSDMC020_OFFSET_ACR 0x34
  23. /*
  24. * Timing Parametet 0 Register
  25. */
  26. #define FTSDMC020_TP0_TCL(x) ((x) & 0x3)
  27. #define FTSDMC020_TP0_TWR(x) (((x) & 0x3) << 4)
  28. #define FTSDMC020_TP0_TRF(x) (((x) & 0xf) << 8)
  29. #define FTSDMC020_TP0_TRCD(x) (((x) & 0x7) << 12)
  30. #define FTSDMC020_TP0_TRP(x) (((x) & 0xf) << 16)
  31. #define FTSDMC020_TP0_TRAS(x) (((x) & 0xf) << 20)
  32. /*
  33. * Timing Parametet 1 Register
  34. */
  35. #define FTSDMC020_TP1_REF_INTV(x) ((x) & 0xffff)
  36. #define FTSDMC020_TP1_INI_REFT(x) (((x) & 0xf) << 16)
  37. #define FTSDMC020_TP1_INI_PREC(x) (((x) & 0xf) << 20)
  38. /*
  39. * Configuration Register
  40. */
  41. #define FTSDMC020_CR_SREF (1 << 0)
  42. #define FTSDMC020_CR_PWDN (1 << 1)
  43. #define FTSDMC020_CR_ISMR (1 << 2)
  44. #define FTSDMC020_CR_IREF (1 << 3)
  45. #define FTSDMC020_CR_IPREC (1 << 4)
  46. #define FTSDMC020_CR_REFTYPE (1 << 5)
  47. /*
  48. * SDRAM External Bank Base/Size Register
  49. */
  50. #define FTSDMC020_BANK_ENABLE (1 << 28)
  51. #define FTSDMC020_BANK_BASE(addr) (((addr) >> 20) << 16)
  52. #define FTSDMC020_BANK_DDW_X4 (0 << 12)
  53. #define FTSDMC020_BANK_DDW_X8 (1 << 12)
  54. #define FTSDMC020_BANK_DDW_X16 (2 << 12)
  55. #define FTSDMC020_BANK_DDW_X32 (3 << 12)
  56. #define FTSDMC020_BANK_DSZ_16M (0 << 8)
  57. #define FTSDMC020_BANK_DSZ_64M (1 << 8)
  58. #define FTSDMC020_BANK_DSZ_128M (2 << 8)
  59. #define FTSDMC020_BANK_DSZ_256M (3 << 8)
  60. #define FTSDMC020_BANK_MBW_8 (0 << 4)
  61. #define FTSDMC020_BANK_MBW_16 (1 << 4)
  62. #define FTSDMC020_BANK_MBW_32 (2 << 4)
  63. #define FTSDMC020_BANK_SIZE_1M 0x0
  64. #define FTSDMC020_BANK_SIZE_2M 0x1
  65. #define FTSDMC020_BANK_SIZE_4M 0x2
  66. #define FTSDMC020_BANK_SIZE_8M 0x3
  67. #define FTSDMC020_BANK_SIZE_16M 0x4
  68. #define FTSDMC020_BANK_SIZE_32M 0x5
  69. #define FTSDMC020_BANK_SIZE_64M 0x6
  70. #define FTSDMC020_BANK_SIZE_128M 0x7
  71. #define FTSDMC020_BANK_SIZE_256M 0x8
  72. /*
  73. * Arbiter Control Register
  74. */
  75. #define FTSDMC020_ACR_TOC(x) ((x) & 0x1f)
  76. #define FTSDMC020_ACR_TOE (1 << 8)
  77. #endif /* __FTSDMC020_H */