ti-dp83867.h 1.7 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * TI DP83867 PHY drivers
  4. *
  5. */
  6. #ifndef _DT_BINDINGS_TI_DP83867_H
  7. #define _DT_BINDINGS_TI_DP83867_H
  8. /* PHY CTRL bits */
  9. #define DP83867_PHYCR_FIFO_DEPTH_3_B_NIB 0x00
  10. #define DP83867_PHYCR_FIFO_DEPTH_4_B_NIB 0x01
  11. #define DP83867_PHYCR_FIFO_DEPTH_6_B_NIB 0x02
  12. #define DP83867_PHYCR_FIFO_DEPTH_8_B_NIB 0x03
  13. /* RGMIIDCTL internal delay for rx and tx */
  14. #define DP83867_RGMIIDCTL_250_PS 0x0
  15. #define DP83867_RGMIIDCTL_500_PS 0x1
  16. #define DP83867_RGMIIDCTL_750_PS 0x2
  17. #define DP83867_RGMIIDCTL_1_NS 0x3
  18. #define DP83867_RGMIIDCTL_1_25_NS 0x4
  19. #define DP83867_RGMIIDCTL_1_50_NS 0x5
  20. #define DP83867_RGMIIDCTL_1_75_NS 0x6
  21. #define DP83867_RGMIIDCTL_2_00_NS 0x7
  22. #define DP83867_RGMIIDCTL_2_25_NS 0x8
  23. #define DP83867_RGMIIDCTL_2_50_NS 0x9
  24. #define DP83867_RGMIIDCTL_2_75_NS 0xa
  25. #define DP83867_RGMIIDCTL_3_00_NS 0xb
  26. #define DP83867_RGMIIDCTL_3_25_NS 0xc
  27. #define DP83867_RGMIIDCTL_3_50_NS 0xd
  28. #define DP83867_RGMIIDCTL_3_75_NS 0xe
  29. #define DP83867_RGMIIDCTL_4_00_NS 0xf
  30. /* IO_MUX_CFG - Clock output selection */
  31. #define DP83867_CLK_O_SEL_CHN_A_RCLK 0x0
  32. #define DP83867_CLK_O_SEL_CHN_B_RCLK 0x1
  33. #define DP83867_CLK_O_SEL_CHN_C_RCLK 0x2
  34. #define DP83867_CLK_O_SEL_CHN_D_RCLK 0x3
  35. #define DP83867_CLK_O_SEL_CHN_A_RCLK_DIV5 0x4
  36. #define DP83867_CLK_O_SEL_CHN_B_RCLK_DIV5 0x5
  37. #define DP83867_CLK_O_SEL_CHN_C_RCLK_DIV5 0x6
  38. #define DP83867_CLK_O_SEL_CHN_D_RCLK_DIV5 0x7
  39. #define DP83867_CLK_O_SEL_CHN_A_TCLK 0x8
  40. #define DP83867_CLK_O_SEL_CHN_B_TCLK 0x9
  41. #define DP83867_CLK_O_SEL_CHN_C_TCLK 0xA
  42. #define DP83867_CLK_O_SEL_CHN_D_TCLK 0xB
  43. #define DP83867_CLK_O_SEL_REF_CLK 0xC
  44. /* Special flag to indicate clock should be off */
  45. #define DP83867_CLK_O_SEL_OFF 0xFFFFFFFF
  46. #endif