quark.h 2.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
  4. *
  5. * Intel Quark MRC bindings include several properties
  6. * as part of an Intel Quark MRC node. In most cases,
  7. * the value of these properties uses the standard values
  8. * defined in this header.
  9. */
  10. #ifndef _DT_BINDINGS_QRK_MRC_H_
  11. #define _DT_BINDINGS_QRK_MRC_H_
  12. /* MRC platform data flags */
  13. #define MRC_FLAG_ECC_EN 0x00000001
  14. #define MRC_FLAG_SCRAMBLE_EN 0x00000002
  15. #define MRC_FLAG_MEMTEST_EN 0x00000004
  16. /* 0b DDR "fly-by" topology else 1b DDR "tree" topology */
  17. #define MRC_FLAG_TOP_TREE_EN 0x00000008
  18. /* If set ODR signal is asserted to DRAM devices on writes */
  19. #define MRC_FLAG_WR_ODT_EN 0x00000010
  20. /* DRAM width */
  21. #define DRAM_WIDTH_X8 0
  22. #define DRAM_WIDTH_X16 1
  23. #define DRAM_WIDTH_X32 2
  24. /* DRAM speed */
  25. #define DRAM_FREQ_800 0
  26. #define DRAM_FREQ_1066 1
  27. /* DRAM type */
  28. #define DRAM_TYPE_DDR3 0
  29. #define DRAM_TYPE_DDR3L 1
  30. /* DRAM rank mask */
  31. #define DRAM_RANK(n) (1 << (n))
  32. /* DRAM channel mask */
  33. #define DRAM_CHANNEL(n) (1 << (n))
  34. /* DRAM channel width */
  35. #define DRAM_CHANNEL_WIDTH_X8 0
  36. #define DRAM_CHANNEL_WIDTH_X16 1
  37. #define DRAM_CHANNEL_WIDTH_X32 2
  38. /* DRAM address mode */
  39. #define DRAM_ADDR_MODE0 0
  40. #define DRAM_ADDR_MODE1 1
  41. #define DRAM_ADDR_MODE2 2
  42. /* DRAM refresh rate */
  43. #define DRAM_REFRESH_RATE_195US 1
  44. #define DRAM_REFRESH_RATE_39US 2
  45. #define DRAM_REFRESH_RATE_785US 3
  46. /* DRAM SR temprature range */
  47. #define DRAM_SRT_RANGE_NORMAL 0
  48. #define DRAM_SRT_RANGE_EXTENDED 1
  49. /* DRAM ron value */
  50. #define DRAM_RON_34OHM 0
  51. #define DRAM_RON_40OHM 1
  52. /* DRAM rtt nom value */
  53. #define DRAM_RTT_NOM_40OHM 0
  54. #define DRAM_RTT_NOM_60OHM 1
  55. #define DRAM_RTT_NOM_120OHM 2
  56. /* DRAM rd odt value */
  57. #define DRAM_RD_ODT_OFF 0
  58. #define DRAM_RD_ODT_60OHM 1
  59. #define DRAM_RD_ODT_120OHM 2
  60. #define DRAM_RD_ODT_180OHM 3
  61. /* DRAM density */
  62. #define DRAM_DENSITY_512M 0
  63. #define DRAM_DENSITY_1G 1
  64. #define DRAM_DENSITY_2G 2
  65. #define DRAM_DENSITY_4G 3
  66. #endif /* _DT_BINDINGS_QRK_MRC_H_ */