work_92105.h 3.1 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * WORK Microwave work_92105 board configuration file
  4. *
  5. * (C) Copyright 2014 DENX Software Engineering GmbH
  6. * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
  7. */
  8. #ifndef __CONFIG_WORK_92105_H__
  9. #define __CONFIG_WORK_92105_H__
  10. /* SoC and board defines */
  11. #include <linux/sizes.h>
  12. #include <asm/arch/cpu.h>
  13. /*
  14. * Define work_92105 machine type by hand -- done only for compatibility
  15. * with original board code
  16. */
  17. #define CONFIG_MACH_TYPE 736
  18. #if !defined(CONFIG_SPL_BUILD)
  19. #define CONFIG_SKIP_LOWLEVEL_INIT
  20. #endif
  21. /*
  22. * Memory configurations
  23. */
  24. #define CONFIG_SYS_MALLOC_LEN SZ_1M
  25. #define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE
  26. #define CONFIG_SYS_SDRAM_SIZE SZ_128M
  27. #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32K)
  28. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_512K \
  29. - GENERATED_GBL_DATA_SIZE)
  30. /*
  31. * Serial Driver
  32. */
  33. #define CONFIG_SYS_LPC32XX_UART 5 /* UART5 - NS16550 */
  34. /*
  35. * Ethernet Driver
  36. */
  37. #define CONFIG_LPC32XX_ETH
  38. #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  39. /* FIXME: remove "Waiting for PHY auto negotiation to complete..." message */
  40. /*
  41. * I2C driver
  42. */
  43. #define CONFIG_SYS_I2C_LPC32XX
  44. #define CONFIG_SYS_I2C
  45. #define CONFIG_SYS_I2C_SPEED 350000
  46. /*
  47. * I2C EEPROM
  48. */
  49. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x56
  50. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
  51. /*
  52. * I2C RTC
  53. */
  54. #define CONFIG_RTC_DS1374
  55. /*
  56. * U-Boot General Configurations
  57. */
  58. #define CONFIG_SYS_CBSIZE 1024
  59. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  60. /*
  61. * NAND chip timings for FIXME: which one?
  62. */
  63. #define CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY 333333333
  64. #define CONFIG_LPC32XX_NAND_MLC_BUSY_DELAY 10000000
  65. #define CONFIG_LPC32XX_NAND_MLC_NAND_TA 18181818
  66. #define CONFIG_LPC32XX_NAND_MLC_RD_HIGH 31250000
  67. #define CONFIG_LPC32XX_NAND_MLC_RD_LOW 45454545
  68. #define CONFIG_LPC32XX_NAND_MLC_WR_HIGH 40000000
  69. #define CONFIG_LPC32XX_NAND_MLC_WR_LOW 83333333
  70. /*
  71. * NAND
  72. */
  73. /* driver configuration */
  74. #define CONFIG_SYS_NAND_SELF_INIT
  75. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  76. #define CONFIG_SYS_MAX_NAND_CHIPS 1
  77. #define CONFIG_SYS_NAND_BASE MLC_NAND_BASE
  78. #define CONFIG_NAND_LPC32XX_MLC
  79. /*
  80. * GPIO
  81. */
  82. #define CONFIG_LPC32XX_GPIO
  83. /*
  84. * Environment
  85. */
  86. /*
  87. * Boot Linux
  88. */
  89. #define CONFIG_CMDLINE_TAG
  90. #define CONFIG_SETUP_MEMORY_TAGS
  91. #define CONFIG_INITRD_TAG
  92. #define CONFIG_BOOTFILE "uImage"
  93. #define CONFIG_LOADADDR 0x80008000
  94. /*
  95. * SPL
  96. */
  97. /* SPL will be executed at offset 0 */
  98. /* SPL will use SRAM as stack */
  99. #define CONFIG_SPL_STACK 0x0000FFF8
  100. /* Use the framework and generic lib */
  101. /* SPL will use serial */
  102. /* SPL will load U-Boot from NAND offset 0x40000 */
  103. #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x00040000
  104. #define CONFIG_SPL_PAD_TO 0x20000
  105. /* U-Boot will be 0x40000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */
  106. #define CONFIG_SYS_MONITOR_LEN 0x40000 /* actually, MAX size */
  107. #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
  108. #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
  109. /*
  110. * Include SoC specific configuration
  111. */
  112. #include <asm/arch/config.h>
  113. #endif /* __CONFIG_WORK_92105_H__*/