tricorder.h 6.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2006-2008
  4. * Texas Instruments.
  5. * Richard Woodruff <r-woodruff2@ti.com>
  6. * Syed Mohammed Khasim <x0khasim@ti.com>
  7. *
  8. * (C) Copyright 2012
  9. * Corscience GmbH & Co. KG
  10. * Thomas Weber <weber@corscience.de>
  11. *
  12. * Configuration settings for the Tricorder board.
  13. */
  14. #ifndef __CONFIG_H
  15. #define __CONFIG_H
  16. #define CONFIG_MACH_TYPE MACH_TYPE_TRICORDER
  17. /*
  18. * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
  19. * 64 bytes before this address should be set aside for u-boot.img's
  20. * header. That is 0x800FFFC0--0x80100000 should not be used for any
  21. * other needs.
  22. */
  23. #include <asm/arch/cpu.h> /* get chip and board defs */
  24. #include <asm/arch/omap.h>
  25. /* Clock Defines */
  26. #define V_OSCK 26000000 /* Clock output from T2 */
  27. #define V_SCLK (V_OSCK >> 1)
  28. #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
  29. #define CONFIG_SETUP_MEMORY_TAGS
  30. #define CONFIG_INITRD_TAG
  31. #define CONFIG_REVISION_TAG
  32. /* Size of malloc() pool */
  33. #define CONFIG_SYS_MALLOC_LEN (1024*1024)
  34. /* Hardware drivers */
  35. /* NS16550 Configuration */
  36. #define CONFIG_SYS_NS16550_SERIAL
  37. #define CONFIG_SYS_NS16550_REG_SIZE (-4)
  38. #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
  39. /* select serial console configuration */
  40. #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
  41. #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
  42. 115200}
  43. /* I2C */
  44. #define CONFIG_SYS_I2C
  45. /* EEPROM */
  46. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
  47. #define CONFIG_SYS_EEPROM_BUS_NUM 1
  48. /* TWL4030 */
  49. /* Board NAND Info */
  50. #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
  51. /* to access nand at */
  52. /* CS0 */
  53. #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
  54. /* devices */
  55. #define CONFIG_SYS_NAND_MAX_OOBFREE 2
  56. #define CONFIG_SYS_NAND_MAX_ECCPOS 56
  57. /* needed for ubi */
  58. /* Environment information (this is the common part) */
  59. /* hang() the board on panic() */
  60. /* environment placement (for NAND), is different for FLASHCARD but does not
  61. * harm there */
  62. #define CONFIG_ENV_RANGE (384 << 10) /* allow badblocks in env */
  63. /* the loadaddr is the same as CONFIG_SYS_LOAD_ADDR, unfortunately the defiend
  64. * value can not be used here! */
  65. #define CONFIG_LOADADDR 0x82000000
  66. #define CONFIG_COMMON_ENV_SETTINGS \
  67. "console=ttyO2,115200n8\0" \
  68. "mmcdev=0\0" \
  69. "vram=3M\0" \
  70. "defaultdisplay=lcd\0" \
  71. "kernelopts=mtdoops.mtddev=3\0" \
  72. "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
  73. "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
  74. "commonargs=" \
  75. "setenv bootargs console=${console} " \
  76. "${mtdparts} " \
  77. "${kernelopts} " \
  78. "vt.global_cursor_default=0 " \
  79. "vram=${vram} " \
  80. "omapdss.def_disp=${defaultdisplay}\0"
  81. #define CONFIG_BOOTCOMMAND "run autoboot"
  82. /* specific environment settings for different use cases
  83. * FLASHCARD: used to run a rdimage from sdcard to program the device
  84. * 'NORMAL': used to boot kernel from sdcard, nand, ...
  85. *
  86. * The main aim for the FLASHCARD skin is to have an embedded environment
  87. * which will not be influenced by any data already on the device.
  88. */
  89. #ifdef CONFIG_FLASHCARD
  90. /* the rdaddr is 16 MiB before the loadaddr */
  91. #define CONFIG_ENV_RDADDR "rdaddr=0x81000000\0"
  92. #define CONFIG_EXTRA_ENV_SETTINGS \
  93. CONFIG_COMMON_ENV_SETTINGS \
  94. CONFIG_ENV_RDADDR \
  95. "autoboot=" \
  96. "run commonargs; " \
  97. "setenv bootargs ${bootargs} " \
  98. "flashy_updateimg=/dev/mmcblk0p1:corscience_update.img " \
  99. "rdinit=/sbin/init; " \
  100. "mmc dev ${mmcdev}; mmc rescan; " \
  101. "fatload mmc ${mmcdev} ${loadaddr} uImage; " \
  102. "fatload mmc ${mmcdev} ${rdaddr} uRamdisk; " \
  103. "bootm ${loadaddr} ${rdaddr}\0"
  104. #else /* CONFIG_FLASHCARD */
  105. #define CONFIG_EXTRA_ENV_SETTINGS \
  106. CONFIG_COMMON_ENV_SETTINGS \
  107. "mmcargs=" \
  108. "run commonargs; " \
  109. "setenv bootargs ${bootargs} " \
  110. "root=/dev/mmcblk0p2 " \
  111. "rootwait " \
  112. "rw\0" \
  113. "nandargs=" \
  114. "run commonargs; " \
  115. "setenv bootargs ${bootargs} " \
  116. "root=ubi0:root " \
  117. "ubi.mtd=7 " \
  118. "rootfstype=ubifs " \
  119. "ro\0" \
  120. "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
  121. "bootscript=echo Running bootscript from mmc ...; " \
  122. "source ${loadaddr}\0" \
  123. "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
  124. "mmcboot=echo Booting from mmc ...; " \
  125. "run mmcargs; " \
  126. "bootm ${loadaddr}\0" \
  127. "loaduimage_ubi=ubi part ubi; " \
  128. "ubifsmount ubi:root; " \
  129. "ubifsload ${loadaddr} /boot/uImage\0" \
  130. "loaduimage_nand=nand read ${loadaddr} kernel 0x500000\0" \
  131. "nandboot=echo Booting from nand ...; " \
  132. "run nandargs; " \
  133. "run loaduimage_nand; " \
  134. "bootm ${loadaddr}\0" \
  135. "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
  136. "if run loadbootscript; then " \
  137. "run bootscript; " \
  138. "else " \
  139. "if run loaduimage; then " \
  140. "run mmcboot; " \
  141. "else run nandboot; " \
  142. "fi; " \
  143. "fi; " \
  144. "else run nandboot; fi\0"
  145. #endif /* CONFIG_FLASHCARD */
  146. /* Miscellaneous configurable options */
  147. #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
  148. #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000)
  149. /*
  150. * OMAP3 has 12 GP timers, they can be driven by the system clock
  151. * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
  152. * This rate is divided by a local divisor.
  153. */
  154. #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
  155. #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
  156. /* Physical Memory Map */
  157. #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
  158. #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
  159. /* NAND and environment organization */
  160. #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
  161. #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
  162. #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
  163. #define CONFIG_SYS_INIT_RAM_SIZE 0x800
  164. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
  165. CONFIG_SYS_INIT_RAM_SIZE - \
  166. GENERATED_GBL_DATA_SIZE)
  167. /* Defines for SPL */
  168. #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
  169. #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
  170. CONFIG_SPL_TEXT_BASE)
  171. #define CONFIG_SPL_BSS_START_ADDR 0x80000000 /*CONFIG_SYS_SDRAM_BASE*/
  172. #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
  173. /* NAND boot config */
  174. #define CONFIG_SYS_NAND_5_ADDR_CYCLE
  175. #define CONFIG_SYS_NAND_PAGE_COUNT 64
  176. #define CONFIG_SYS_NAND_PAGE_SIZE 2048
  177. #define CONFIG_SYS_NAND_OOBSIZE 64
  178. #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
  179. #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
  180. #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \
  181. 13, 14, 16, 17, 18, 19, 20, 21, 22, \
  182. 23, 24, 25, 26, 27, 28, 30, 31, 32, \
  183. 33, 34, 35, 36, 37, 38, 39, 40, 41, \
  184. 42, 44, 45, 46, 47, 48, 49, 50, 51, \
  185. 52, 53, 54, 55, 56}
  186. #define CONFIG_SYS_NAND_ECCSIZE 512
  187. #define CONFIG_SYS_NAND_ECCBYTES 13
  188. #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
  189. #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
  190. #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
  191. #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x100000
  192. #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
  193. #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */
  194. #endif /* __CONFIG_H */