sh7757lcr.h 2.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Configuation settings for the sh7757lcr board
  4. *
  5. * Copyright (C) 2011 Renesas Solutions Corp.
  6. */
  7. #ifndef __SH7757LCR_H
  8. #define __SH7757LCR_H
  9. #define CONFIG_CPU_SH7757 1
  10. #define CONFIG_SH7757LCR_DDR_ECC 1
  11. #define CONFIG_DISPLAY_BOARDINFO
  12. /* MEMORY */
  13. #define SH7757LCR_SDRAM_BASE (0x80000000)
  14. #define SH7757LCR_SDRAM_SIZE (240 * 1024 * 1024)
  15. #define SH7757LCR_SDRAM_ECC_SETTING 0x0f000000 /* 240MByte */
  16. #define SH7757LCR_SDRAM_DVC_SIZE (16 * 1024 * 1024)
  17. #define CONFIG_SYS_PBSIZE 256
  18. #define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
  19. /* SCIF */
  20. #define CONFIG_CONS_SCIF2 1
  21. #undef CONFIG_SYS_LOADS_BAUD_CHANGE
  22. #define CONFIG_SYS_SDRAM_BASE (SH7757LCR_SDRAM_BASE)
  23. #define CONFIG_SYS_SDRAM_SIZE (SH7757LCR_SDRAM_SIZE)
  24. #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \
  25. (128 + 16) * 1024 * 1024)
  26. #define CONFIG_SYS_MONITOR_BASE 0x00000000
  27. #define CONFIG_SYS_MONITOR_LEN (256 * 1024)
  28. #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
  29. #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
  30. /* Ether */
  31. #define CONFIG_SH_ETHER_USE_PORT 0
  32. #define CONFIG_SH_ETHER_PHY_ADDR 1
  33. #define CONFIG_SH_ETHER_CACHE_WRITEBACK 1
  34. #define CONFIG_BITBANGMII_MULTI
  35. #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
  36. #define SH7757LCR_ETHERNET_MAC_BASE_SPI 0x000b0000
  37. #define SH7757LCR_SPI_SECTOR_SIZE (64 * 1024)
  38. #define SH7757LCR_ETHERNET_MAC_BASE SH7757LCR_ETHERNET_MAC_BASE_SPI
  39. #define SH7757LCR_ETHERNET_MAC_SIZE 17
  40. #define SH7757LCR_ETHERNET_NUM_CH 2
  41. /* Gigabit Ether */
  42. #define SH7757LCR_GIGA_ETHERNET_NUM_CH 2
  43. /* SPI */
  44. #define CONFIG_SH_SPI_BASE 0xfe002000
  45. /* MMCIF */
  46. #define CONFIG_SH_MMCIF_ADDR 0xffcb0000
  47. #define CONFIG_SH_MMCIF_CLK 48000000
  48. /* SH7757 board */
  49. #define SH7757LCR_SDRAM_PHYS_TOP 0x40000000
  50. #define SH7757LCR_GRA_OFFSET 0x1f000000
  51. #define SH7757LCR_PCIEBRG_ADDR_B0 0x000a0000
  52. #define SH7757LCR_PCIEBRG_SIZE_B0 (64 * 1024)
  53. #define SH7757LCR_PCIEBRG_ADDR 0x00090000
  54. #define SH7757LCR_PCIEBRG_SIZE (96 * 1024)
  55. /* ENV setting */
  56. #define CONFIG_EXTRA_ENV_SETTINGS \
  57. "netboot=bootp; bootm\0"
  58. /* Board Clock */
  59. #define CONFIG_SYS_CLK_FREQ 48000000
  60. #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
  61. #endif /* __SH7757LCR_H */