mx6sabreauto.h 2.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2012 Freescale Semiconductor, Inc.
  4. *
  5. * Configuration settings for the Freescale i.MX6Q SabreAuto board.
  6. */
  7. #ifndef __MX6SABREAUTO_CONFIG_H
  8. #define __MX6SABREAUTO_CONFIG_H
  9. #ifdef CONFIG_SPL
  10. #include "imx6_spl.h"
  11. #endif
  12. #define CONFIG_MACH_TYPE 3529
  13. #define CONFIG_MXC_UART_BASE UART4_BASE
  14. #define CONSOLE_DEV "ttymxc3"
  15. /* USB Configs */
  16. #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  17. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */
  18. #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
  19. #define CONFIG_MXC_USB_FLAGS 0
  20. #define CONFIG_PCA953X
  21. #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34, 8} }
  22. #include "mx6sabre_common.h"
  23. /* Falcon Mode */
  24. #ifdef CONFIG_SPL_OS_BOOT
  25. #define CONFIG_SPL_FS_LOAD_ARGS_NAME "args"
  26. #define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage"
  27. #define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000
  28. /* Falcon Mode - MMC support: args@1MB kernel@2MB */
  29. #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */
  30. #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512)
  31. #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 /* 2MB */
  32. #endif
  33. #ifdef CONFIG_MTD_NOR_FLASH
  34. #define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR
  35. #define CONFIG_SYS_FLASH_SECT_SIZE (128 * 1024)
  36. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
  37. #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
  38. #define CONFIG_SYS_FLASH_EMPTY_INFO
  39. #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
  40. #endif
  41. #define CONFIG_SYS_FSL_USDHC_NUM 2
  42. /* I2C Configs */
  43. #define CONFIG_SYS_I2C
  44. #define CONFIG_SYS_I2C_MXC
  45. #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
  46. #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
  47. #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
  48. #define CONFIG_SYS_I2C_SPEED 100000
  49. /* NAND stuff */
  50. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  51. #define CONFIG_SYS_NAND_BASE 0x40000000
  52. #define CONFIG_SYS_NAND_5_ADDR_CYCLE
  53. #define CONFIG_SYS_NAND_ONFI_DETECTION
  54. /* DMA stuff, needed for GPMI/MXS NAND support */
  55. /* PMIC */
  56. #define CONFIG_POWER
  57. #define CONFIG_POWER_I2C
  58. #define CONFIG_POWER_PFUZE100
  59. #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
  60. #endif /* __MX6SABREAUTO_CONFIG_H */