lx2160aqds.h 4.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2018-2020 NXP
  4. */
  5. #ifndef __LX2_QDS_H
  6. #define __LX2_QDS_H
  7. #include "lx2160a_common.h"
  8. /* Qixis */
  9. #define QIXIS_XMAP_MASK 0x07
  10. #define QIXIS_XMAP_SHIFT 5
  11. #define QIXIS_RST_CTL_RESET_EN 0x30
  12. #define QIXIS_LBMAP_DFLTBANK 0x00
  13. #define QIXIS_LBMAP_ALTBANK 0x20
  14. #define QIXIS_LBMAP_QSPI 0x00
  15. #define QIXIS_RCW_SRC_QSPI 0xff
  16. #define QIXIS_RST_CTL_RESET 0x31
  17. #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
  18. #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
  19. #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
  20. #define QIXIS_LBMAP_MASK 0x0f
  21. #define QIXIS_LBMAP_SD
  22. #define QIXIS_LBMAP_EMMC
  23. #define QIXIS_RCW_SRC_SD 0x08
  24. #define QIXIS_RCW_SRC_EMMC 0x09
  25. #define NON_EXTENDED_DUTCFG
  26. #define QIXIS_SDID_MASK 0x07
  27. #define QIXIS_ESDHC_NO_ADAPTER 0x7
  28. /* SYSCLK */
  29. #define QIXIS_SYSCLK_100 0x0
  30. #define QIXIS_SYSCLK_125 0x1
  31. #define QIXIS_SYSCLK_133 0x2
  32. /* DDRCLK */
  33. #define QIXIS_DDRCLK_100 0x0
  34. #define QIXIS_DDRCLK_125 0x1
  35. #define QIXIS_DDRCLK_133 0x2
  36. #define BRDCFG4_EMI1SEL_MASK 0xF8
  37. #define BRDCFG4_EMI1SEL_SHIFT 3
  38. #define BRDCFG4_EMI2SEL_MASK 0x07
  39. #define BRDCFG4_EMI2SEL_SHIFT 0
  40. /* VID */
  41. #define I2C_MUX_CH_VOL_MONITOR 0xA
  42. /* Voltage monitor on channel 2*/
  43. #define I2C_VOL_MONITOR_ADDR 0x63
  44. #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
  45. #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
  46. #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
  47. #define CONFIG_VID_FLS_ENV "lx2160aqds_vdd_mv"
  48. #define CONFIG_VID
  49. /* The lowest and highest voltage allowed*/
  50. #define VDD_MV_MIN 775
  51. #define VDD_MV_MAX 925
  52. /* PM Bus commands code for LTC3882*/
  53. #define PMBUS_CMD_PAGE 0x0
  54. #define PMBUS_CMD_READ_VOUT 0x8B
  55. #define PMBUS_CMD_PAGE_PLUS_WRITE 0x05
  56. #define PMBUS_CMD_VOUT_COMMAND 0x21
  57. #define PWM_CHANNEL0 0x0
  58. #define CONFIG_VOL_MONITOR_LTC3882_SET
  59. #define CONFIG_VOL_MONITOR_LTC3882_READ
  60. /* RTC */
  61. #define CONFIG_SYS_RTC_BUS_NUM 0
  62. #define I2C_MUX_CH_RTC 0xB
  63. /*
  64. * MMC
  65. */
  66. #ifdef CONFIG_MMC
  67. #ifndef __ASSEMBLY__
  68. u8 qixis_esdhc_detect_quirk(void);
  69. #endif
  70. #define CONFIG_ESDHC_DETECT_QUIRK qixis_esdhc_detect_quirk()
  71. #endif
  72. /* MAC/PHY configuration */
  73. #if defined(CONFIG_FSL_MC_ENET)
  74. #define CONFIG_MII
  75. #define CONFIG_ETHPRIME "DPMAC17@rgmii-id"
  76. #define AQ_PHY_ADDR1 0x00
  77. #define AQ_PHY_ADDR2 0x01
  78. #define AQ_PHY_ADDR3 0x02
  79. #define AQ_PHY_ADDR4 0x03
  80. #define CORTINA_NO_FW_UPLOAD
  81. #define CORTINA_PHY_ADDR1 0x0
  82. #define INPHI_PHY_ADDR1 0x0
  83. #define INPHI_PHY_ADDR2 0x1
  84. #define RGMII_PHY_ADDR1 0x01
  85. #define RGMII_PHY_ADDR2 0x02
  86. #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
  87. #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
  88. #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
  89. #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
  90. #endif
  91. /* EEPROM */
  92. #define CONFIG_ID_EEPROM
  93. #define CONFIG_SYS_I2C_EEPROM_NXID
  94. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  95. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  96. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  97. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
  98. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
  99. /* Initial environment variables */
  100. #define CONFIG_EXTRA_ENV_SETTINGS \
  101. EXTRA_ENV_SETTINGS \
  102. "boot_scripts=lx2160aqds_boot.scr\0" \
  103. "boot_script_hdr=hdr_lx2160aqds_bs.out\0" \
  104. "BOARD=lx2160aqds\0" \
  105. "xspi_bootcmd=echo Trying load from flexspi..;" \
  106. "sf probe 0:0 && sf read $load_addr " \
  107. "$kernel_start $kernel_size ; env exists secureboot &&" \
  108. "sf read $kernelheader_addr_r $kernelheader_start " \
  109. "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
  110. " bootm $load_addr#$BOARD\0" \
  111. "sd_bootcmd=echo Trying load from sd card..;" \
  112. "mmc dev 0; mmcinfo; mmc read $load_addr " \
  113. "$kernel_addr_sd $kernel_size_sd ;" \
  114. "env exists secureboot && mmc read $kernelheader_addr_r "\
  115. "$kernelhdr_addr_sd $kernelhdr_size_sd " \
  116. " && esbc_validate ${kernelheader_addr_r};" \
  117. "bootm $load_addr#$BOARD\0" \
  118. "sd2_bootcmd=echo Trying load from emmc card..;" \
  119. "mmc dev 1; mmcinfo; mmc read $load_addr " \
  120. "$kernel_addr_sd $kernel_size_sd ;" \
  121. "env exists secureboot && mmc read $kernelheader_addr_r "\
  122. "$kernelhdr_addr_sd $kernelhdr_size_sd " \
  123. " && esbc_validate ${kernelheader_addr_r};" \
  124. "bootm $load_addr#$BOARD\0"
  125. #include <asm/fsl_secure_boot.h>
  126. #endif /* __LX2_QDS_H */