ls1046aqds.h 15 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2016 Freescale Semiconductor, Inc.
  4. */
  5. #ifndef __LS1046AQDS_H__
  6. #define __LS1046AQDS_H__
  7. #include "ls1046a_common.h"
  8. #ifndef __ASSEMBLY__
  9. unsigned long get_board_sys_clk(void);
  10. unsigned long get_board_ddr_clk(void);
  11. #endif
  12. #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
  13. #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
  14. #define CONFIG_SKIP_LOWLEVEL_INIT
  15. #define CONFIG_LAYERSCAPE_NS_ACCESS
  16. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  17. /* Physical Memory Map */
  18. #define CONFIG_CHIP_SELECTS_PER_CTRL 4
  19. #define CONFIG_DDR_SPD
  20. #define SPD_EEPROM_ADDRESS 0x51
  21. #define CONFIG_SYS_SPD_BUS_NUM 0
  22. #define CONFIG_DDR_ECC
  23. #ifdef CONFIG_DDR_ECC
  24. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  25. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  26. #endif
  27. /* DSPI */
  28. #ifdef CONFIG_FSL_DSPI
  29. #define CONFIG_SPI_FLASH_STMICRO /* cs0 */
  30. #define CONFIG_SPI_FLASH_SST /* cs1 */
  31. #define CONFIG_SPI_FLASH_EON /* cs2 */
  32. #endif
  33. #ifdef CONFIG_SYS_DPAA_FMAN
  34. #define RGMII_PHY1_ADDR 0x1
  35. #define RGMII_PHY2_ADDR 0x2
  36. #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
  37. #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
  38. #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
  39. #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
  40. /* PHY address on QSGMII riser card on slot 2 */
  41. #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
  42. #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
  43. #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
  44. #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
  45. #endif
  46. #ifdef CONFIG_RAMBOOT_PBL
  47. #define CONFIG_SYS_FSL_PBL_PBI \
  48. board/freescale/ls1046aqds/ls1046aqds_pbi.cfg
  49. #endif
  50. #ifdef CONFIG_NAND_BOOT
  51. #define CONFIG_SYS_FSL_PBL_RCW \
  52. board/freescale/ls1046aqds/ls1046aqds_rcw_nand.cfg
  53. #endif
  54. #ifdef CONFIG_SD_BOOT
  55. #ifdef CONFIG_SD_BOOT_QSPI
  56. #define CONFIG_SYS_FSL_PBL_RCW \
  57. board/freescale/ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg
  58. #else
  59. #define CONFIG_SYS_FSL_PBL_RCW \
  60. board/freescale/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg
  61. #endif
  62. #endif
  63. /* IFC */
  64. #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  65. #define CONFIG_FSL_IFC
  66. /*
  67. * CONFIG_SYS_FLASH_BASE has the final address (core view)
  68. * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
  69. * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
  70. * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
  71. */
  72. #define CONFIG_SYS_FLASH_BASE 0x60000000
  73. #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
  74. #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
  75. #ifdef CONFIG_MTD_NOR_FLASH
  76. #define CONFIG_SYS_FLASH_QUIET_TEST
  77. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  78. #endif
  79. #endif
  80. /* LPUART */
  81. #ifdef CONFIG_LPUART
  82. #define CONFIG_LPUART_32B_REG
  83. #define CFG_UART_MUX_MASK 0x6
  84. #define CFG_UART_MUX_SHIFT 1
  85. #define CFG_LPUART_EN 0x2
  86. #endif
  87. /* EEPROM */
  88. #define CONFIG_ID_EEPROM
  89. #define CONFIG_SYS_I2C_EEPROM_NXID
  90. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  91. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  92. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  93. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
  94. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
  95. /*
  96. * IFC Definitions
  97. */
  98. #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  99. #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
  100. #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  101. CSPR_PORT_SIZE_16 | \
  102. CSPR_MSEL_NOR | \
  103. CSPR_V)
  104. #define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
  105. #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
  106. + 0x8000000) | \
  107. CSPR_PORT_SIZE_16 | \
  108. CSPR_MSEL_NOR | \
  109. CSPR_V)
  110. #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
  111. #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
  112. CSOR_NOR_TRHZ_80)
  113. #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
  114. FTIM0_NOR_TEADC(0x5) | \
  115. FTIM0_NOR_TAVDS(0x6) | \
  116. FTIM0_NOR_TEAHC(0x5))
  117. #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
  118. FTIM1_NOR_TRAD_NOR(0x1a) | \
  119. FTIM1_NOR_TSEQRAD_NOR(0x13))
  120. #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x8) | \
  121. FTIM2_NOR_TCH(0x8) | \
  122. FTIM2_NOR_TWPH(0xe) | \
  123. FTIM2_NOR_TWP(0x1c))
  124. #define CONFIG_SYS_NOR_FTIM3 0
  125. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  126. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  127. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  128. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  129. #define CONFIG_SYS_FLASH_EMPTY_INFO
  130. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
  131. CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
  132. #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
  133. #define CONFIG_SYS_WRITE_SWAPPED_DATA
  134. /*
  135. * NAND Flash Definitions
  136. */
  137. #define CONFIG_NAND_FSL_IFC
  138. #define CONFIG_SYS_NAND_BASE 0x7e800000
  139. #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
  140. #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
  141. #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  142. | CSPR_PORT_SIZE_8 \
  143. | CSPR_MSEL_NAND \
  144. | CSPR_V)
  145. #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
  146. #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  147. | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  148. | CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \
  149. | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
  150. | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
  151. | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
  152. | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
  153. #define CONFIG_SYS_NAND_ONFI_DETECTION
  154. #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
  155. FTIM0_NAND_TWP(0x18) | \
  156. FTIM0_NAND_TWCHT(0x7) | \
  157. FTIM0_NAND_TWH(0xa))
  158. #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
  159. FTIM1_NAND_TWBE(0x39) | \
  160. FTIM1_NAND_TRR(0xe) | \
  161. FTIM1_NAND_TRP(0x18))
  162. #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
  163. FTIM2_NAND_TREH(0xa) | \
  164. FTIM2_NAND_TWHRE(0x1e))
  165. #define CONFIG_SYS_NAND_FTIM3 0x0
  166. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  167. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  168. #define CONFIG_MTD_NAND_VERIFY_WRITE
  169. #define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024)
  170. #endif
  171. #ifdef CONFIG_NAND_BOOT
  172. #define CONFIG_SPL_PAD_TO 0x40000 /* block aligned */
  173. #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
  174. #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
  175. #endif
  176. #if defined(CONFIG_TFABOOT) || \
  177. defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  178. #define CONFIG_QIXIS_I2C_ACCESS
  179. #define CONFIG_SYS_I2C_EARLY_INIT
  180. #endif
  181. /*
  182. * QIXIS Definitions
  183. */
  184. #define CONFIG_FSL_QIXIS
  185. #ifdef CONFIG_FSL_QIXIS
  186. #define QIXIS_BASE 0x7fb00000
  187. #define QIXIS_BASE_PHYS QIXIS_BASE
  188. #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
  189. #define QIXIS_LBMAP_SWITCH 6
  190. #define QIXIS_LBMAP_MASK 0x0f
  191. #define QIXIS_LBMAP_SHIFT 0
  192. #define QIXIS_LBMAP_DFLTBANK 0x00
  193. #define QIXIS_LBMAP_ALTBANK 0x04
  194. #define QIXIS_LBMAP_NAND 0x09
  195. #define QIXIS_LBMAP_SD 0x00
  196. #define QIXIS_LBMAP_SD_QSPI 0xff
  197. #define QIXIS_LBMAP_QSPI 0xff
  198. #define QIXIS_RCW_SRC_NAND 0x110
  199. #define QIXIS_RCW_SRC_SD 0x040
  200. #define QIXIS_RCW_SRC_QSPI 0x045
  201. #define QIXIS_RST_CTL_RESET 0x41
  202. #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
  203. #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
  204. #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
  205. #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
  206. #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
  207. CSPR_PORT_SIZE_8 | \
  208. CSPR_MSEL_GPCM | \
  209. CSPR_V)
  210. #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
  211. #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
  212. CSOR_NOR_NOR_MODE_AVD_NOR | \
  213. CSOR_NOR_TRHZ_80)
  214. /*
  215. * QIXIS Timing parameters for IFC GPCM
  216. */
  217. #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \
  218. FTIM0_GPCM_TEADC(0x20) | \
  219. FTIM0_GPCM_TEAHC(0x10))
  220. #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \
  221. FTIM1_GPCM_TRAD(0x1f))
  222. #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \
  223. FTIM2_GPCM_TCH(0x8) | \
  224. FTIM2_GPCM_TWP(0xf0))
  225. #define CONFIG_SYS_FPGA_FTIM3 0x0
  226. #endif
  227. #ifdef CONFIG_TFABOOT
  228. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
  229. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
  230. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  231. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  232. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  233. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  234. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  235. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  236. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
  237. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
  238. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  239. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  240. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  241. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  242. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  243. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  244. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
  245. #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
  246. #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
  247. #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
  248. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
  249. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
  250. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
  251. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
  252. #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
  253. #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
  254. #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
  255. #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
  256. #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
  257. #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
  258. #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
  259. #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
  260. #else
  261. #ifdef CONFIG_NAND_BOOT
  262. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
  263. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
  264. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
  265. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
  266. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
  267. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
  268. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
  269. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
  270. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
  271. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
  272. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  273. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  274. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  275. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  276. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  277. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  278. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
  279. #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
  280. #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
  281. #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
  282. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
  283. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
  284. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
  285. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
  286. #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
  287. #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
  288. #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
  289. #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
  290. #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
  291. #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
  292. #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
  293. #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
  294. #else
  295. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
  296. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
  297. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  298. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  299. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  300. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  301. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  302. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  303. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
  304. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
  305. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  306. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  307. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  308. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  309. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  310. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  311. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
  312. #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
  313. #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
  314. #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
  315. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
  316. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
  317. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
  318. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
  319. #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
  320. #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
  321. #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
  322. #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
  323. #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
  324. #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
  325. #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
  326. #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
  327. #endif
  328. #endif
  329. /*
  330. * I2C bus multiplexer
  331. */
  332. #define I2C_MUX_PCA_ADDR_PRI 0x77
  333. #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
  334. #define I2C_RETIMER_ADDR 0x18
  335. #define I2C_MUX_CH_DEFAULT 0x8
  336. #define I2C_MUX_CH_CH7301 0xC
  337. #define I2C_MUX_CH5 0xD
  338. #define I2C_MUX_CH6 0xE
  339. #define I2C_MUX_CH7 0xF
  340. #define I2C_MUX_CH_VOL_MONITOR 0xa
  341. /* Voltage monitor on channel 2*/
  342. #define I2C_VOL_MONITOR_ADDR 0x40
  343. #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
  344. #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
  345. #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
  346. #define CONFIG_VID_FLS_ENV "ls1046aqds_vdd_mv"
  347. #ifndef CONFIG_SPL_BUILD
  348. #define CONFIG_VID
  349. #endif
  350. #define CONFIG_VOL_MONITOR_IR36021_SET
  351. #define CONFIG_VOL_MONITOR_INA220
  352. /* The lowest and highest voltage allowed for LS1046AQDS */
  353. #define VDD_MV_MIN 819
  354. #define VDD_MV_MAX 1212
  355. /*
  356. * Miscellaneous configurable options
  357. */
  358. #define CONFIG_SYS_HZ 1000
  359. #define CONFIG_SYS_INIT_SP_OFFSET \
  360. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  361. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  362. /*
  363. * Environment
  364. */
  365. #define CONFIG_CMDLINE_TAG
  366. #undef CONFIG_BOOTCOMMAND
  367. #ifdef CONFIG_TFABOOT
  368. #define IFC_NAND_BOOTCOMMAND "run distro_bootcmd; run nand_bootcmd; " \
  369. "env exists secureboot && esbc_halt;;"
  370. #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd" \
  371. "env exists secureboot && esbc_halt;;"
  372. #define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \
  373. "env exists secureboot && esbc_halt;;"
  374. #define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \
  375. "env exists secureboot && esbc_halt;;"
  376. #else
  377. #if defined(CONFIG_QSPI_BOOT)
  378. #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \
  379. "env exists secureboot && esbc_halt;;"
  380. #elif defined(CONFIG_NAND_BOOT)
  381. #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nand_bootcmd; " \
  382. "env exists secureboot && esbc_halt;;"
  383. #elif defined(CONFIG_SD_BOOT)
  384. #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \
  385. "env exists secureboot && esbc_halt;;"
  386. #else
  387. #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \
  388. "env exists secureboot && esbc_halt;;"
  389. #endif
  390. #endif
  391. #include <asm/fsl_secure_boot.h>
  392. #endif /* __LS1046AQDS_H__ */