ls1046a_common.h 9.6 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2016 Freescale Semiconductor
  4. * Copyright 2019-2020 NXP
  5. */
  6. #ifndef __LS1046A_COMMON_H
  7. #define __LS1046A_COMMON_H
  8. /* SPL build */
  9. #ifdef CONFIG_SPL_BUILD
  10. #define SPL_NO_QBMAN
  11. #define SPL_NO_FMAN
  12. #define SPL_NO_ENV
  13. #define SPL_NO_MISC
  14. #define SPL_NO_QSPI
  15. #define SPL_NO_USB
  16. #define SPL_NO_SATA
  17. #undef CONFIG_DM_I2C
  18. #endif
  19. #if defined(CONFIG_SPL_BUILD) && \
  20. (defined(CONFIG_NAND_BOOT) || defined(CONFIG_QSPI_BOOT))
  21. #define SPL_NO_MMC
  22. #endif
  23. #if defined(CONFIG_SPL_BUILD) && \
  24. !defined(CONFIG_SPL_FSL_LS_PPA)
  25. #define SPL_NO_IFC
  26. #endif
  27. #define CONFIG_REMAKE_ELF
  28. #define CONFIG_GICV2
  29. #include <asm/arch/config.h>
  30. #include <asm/arch/stream_id_lsch2.h>
  31. /* Link Definitions */
  32. #ifdef CONFIG_TFABOOT
  33. #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
  34. #else
  35. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
  36. #endif
  37. #define CONFIG_SKIP_LOWLEVEL_INIT
  38. #define CONFIG_VERY_BIG_RAM
  39. #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
  40. #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
  41. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  42. #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
  43. #define CPU_RELEASE_ADDR secondary_boot_addr
  44. /* Generic Timer Definitions */
  45. #define COUNTER_FREQUENCY 25000000 /* 25MHz */
  46. /* Size of malloc() pool */
  47. #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
  48. /* Serial Port */
  49. #define CONFIG_SYS_NS16550_SERIAL
  50. #define CONFIG_SYS_NS16550_REG_SIZE 1
  51. #define CONFIG_SYS_NS16550_CLK (get_serial_clock())
  52. #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
  53. /* SD boot SPL */
  54. #ifdef CONFIG_SD_BOOT
  55. #define CONFIG_SPL_MAX_SIZE 0x1f000 /* 124 KiB */
  56. #define CONFIG_SPL_STACK 0x10020000
  57. #define CONFIG_SPL_PAD_TO 0x21000 /* 132 KiB */
  58. #define CONFIG_SPL_BSS_START_ADDR 0x8f000000
  59. #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
  60. #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
  61. CONFIG_SPL_BSS_MAX_SIZE)
  62. #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
  63. #ifdef CONFIG_NXP_ESBC
  64. #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
  65. /*
  66. * HDR would be appended at end of image and copied to DDR along
  67. * with U-Boot image. Here u-boot max. size is 512K. So if binary
  68. * size increases then increase this size in case of secure boot as
  69. * it uses raw u-boot image instead of fit image.
  70. */
  71. #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
  72. #else
  73. #define CONFIG_SYS_MONITOR_LEN 0x100000
  74. #endif /* ifdef CONFIG_NXP_ESBC */
  75. #endif
  76. #if defined(CONFIG_QSPI_BOOT) && defined(CONFIG_SPL)
  77. #define CONFIG_SPL_TARGET "spl/u-boot-spl.pbl"
  78. #define CONFIG_SPL_MAX_SIZE 0x1f000
  79. #define CONFIG_SPL_STACK 0x10020000
  80. #define CONFIG_SPL_PAD_TO 0x20000
  81. #define CONFIG_SPL_BSS_START_ADDR 0x8f000000
  82. #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
  83. #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
  84. CONFIG_SPL_BSS_MAX_SIZE)
  85. #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
  86. #define CONFIG_SYS_MONITOR_LEN 0x100000
  87. #endif
  88. /* NAND SPL */
  89. #ifdef CONFIG_NAND_BOOT
  90. #define CONFIG_SPL_PBL_PAD
  91. #define CONFIG_SPL_LIBCOMMON_SUPPORT
  92. #define CONFIG_SPL_LIBGENERIC_SUPPORT
  93. #define CONFIG_SPL_ENV_SUPPORT
  94. #define CONFIG_SPL_WATCHDOG_SUPPORT
  95. #define CONFIG_SPL_I2C_SUPPORT
  96. #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
  97. #define CONFIG_SPL_NAND_SUPPORT
  98. #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
  99. #define CONFIG_SPL_MAX_SIZE 0x17000 /* 90 KiB */
  100. #define CONFIG_SPL_STACK 0x1001f000
  101. #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
  102. #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
  103. #define CONFIG_SPL_BSS_START_ADDR 0x8f000000
  104. #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
  105. #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
  106. CONFIG_SPL_BSS_MAX_SIZE)
  107. #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
  108. #define CONFIG_SYS_MONITOR_LEN 0xa0000
  109. #endif
  110. /* I2C */
  111. #ifndef CONFIG_DM_I2C
  112. #define CONFIG_SYS_I2C
  113. #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
  114. #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
  115. #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
  116. #define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */
  117. #else
  118. #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
  119. #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
  120. #endif
  121. /* PCIe */
  122. #define CONFIG_PCIE1 /* PCIE controller 1 */
  123. #define CONFIG_PCIE2 /* PCIE controller 2 */
  124. #define CONFIG_PCIE3 /* PCIE controller 3 */
  125. #ifdef CONFIG_PCI
  126. #define CONFIG_PCI_SCAN_SHOW
  127. #endif
  128. /* SATA */
  129. #ifndef SPL_NO_SATA
  130. #define CONFIG_SCSI_AHCI_PLAT
  131. #define CONFIG_SYS_SATA AHCI_BASE_ADDR
  132. #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
  133. #define CONFIG_SYS_SCSI_MAX_LUN 1
  134. #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
  135. CONFIG_SYS_SCSI_MAX_LUN)
  136. #endif
  137. /* MMC */
  138. #ifndef SPL_NO_MMC
  139. #ifdef CONFIG_MMC
  140. #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
  141. #endif
  142. #endif
  143. /* FMan ucode */
  144. #ifndef SPL_NO_FMAN
  145. #define CONFIG_SYS_DPAA_FMAN
  146. #ifdef CONFIG_SYS_DPAA_FMAN
  147. #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
  148. #endif
  149. #ifdef CONFIG_TFABOOT
  150. #define CONFIG_SYS_FMAN_FW_ADDR 0x900000
  151. #else
  152. #ifdef CONFIG_SD_BOOT
  153. /*
  154. * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
  155. * about 1MB (2048 blocks), Env is stored after the image, and the env size is
  156. * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 18432(0x4800).
  157. */
  158. #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x4800)
  159. #elif defined(CONFIG_QSPI_BOOT)
  160. #define CONFIG_SYS_FMAN_FW_ADDR 0x40900000
  161. #elif defined(CONFIG_NAND_BOOT)
  162. #define CONFIG_SYS_FMAN_FW_ADDR (36 * CONFIG_SYS_NAND_BLOCK_SIZE)
  163. #else
  164. #define CONFIG_SYS_FMAN_FW_ADDR 0x60900000
  165. #endif
  166. #endif
  167. #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
  168. #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
  169. #endif
  170. /* Miscellaneous configurable options */
  171. #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
  172. #define CONFIG_HWCONFIG
  173. #define HWCONFIG_BUFFER_SIZE 128
  174. #ifndef CONFIG_SPL_BUILD
  175. #define BOOT_TARGET_DEVICES(func) \
  176. func(SCSI, scsi, 0) \
  177. func(MMC, mmc, 0) \
  178. func(USB, usb, 0) \
  179. func(DHCP, dhcp, na)
  180. #include <config_distro_bootcmd.h>
  181. #endif
  182. #if defined(CONFIG_TARGET_LS1046AFRWY)
  183. #define LS1046A_BOOT_SRC_AND_HDR\
  184. "boot_scripts=ls1046afrwy_boot.scr\0" \
  185. "boot_script_hdr=hdr_ls1046afrwy_bs.out\0"
  186. #elif defined(CONFIG_TARGET_LS1046AQDS)
  187. #define LS1046A_BOOT_SRC_AND_HDR\
  188. "boot_scripts=ls1046aqds_boot.scr\0" \
  189. "boot_script_hdr=hdr_ls1046aqds_bs.out\0"
  190. #else
  191. #define LS1046A_BOOT_SRC_AND_HDR\
  192. "boot_scripts=ls1046ardb_boot.scr\0" \
  193. "boot_script_hdr=hdr_ls1046ardb_bs.out\0"
  194. #endif
  195. #ifndef SPL_NO_MISC
  196. /* Initial environment variables */
  197. #define CONFIG_EXTRA_ENV_SETTINGS \
  198. "hwconfig=fsl_ddr:bank_intlv=auto\0" \
  199. "ramdisk_addr=0x800000\0" \
  200. "ramdisk_size=0x2000000\0" \
  201. "bootm_size=0x10000000\0" \
  202. "fdt_addr=0x64f00000\0" \
  203. "kernel_addr=0x61000000\0" \
  204. "scriptaddr=0x80000000\0" \
  205. "scripthdraddr=0x80080000\0" \
  206. "fdtheader_addr_r=0x80100000\0" \
  207. "kernelheader_addr_r=0x80200000\0" \
  208. "load_addr=0xa0000000\0" \
  209. "kernel_addr_r=0x81000000\0" \
  210. "fdt_addr_r=0x90000000\0" \
  211. "ramdisk_addr_r=0xa0000000\0" \
  212. "kernel_start=0x1000000\0" \
  213. "kernelheader_start=0x600000\0" \
  214. "kernel_load=0xa0000000\0" \
  215. "kernel_size=0x2800000\0" \
  216. "kernelheader_size=0x40000\0" \
  217. "kernel_addr_sd=0x8000\0" \
  218. "kernel_size_sd=0x14000\0" \
  219. "kernelhdr_addr_sd=0x3000\0" \
  220. "kernelhdr_size_sd=0x10\0" \
  221. "console=ttyS0,115200\0" \
  222. CONFIG_MTDPARTS_DEFAULT "\0" \
  223. BOOTENV \
  224. LS1046A_BOOT_SRC_AND_HDR \
  225. "scan_dev_for_boot_part=" \
  226. "part list ${devtype} ${devnum} devplist; " \
  227. "env exists devplist || setenv devplist 1; " \
  228. "for distro_bootpart in ${devplist}; do " \
  229. "if fstype ${devtype} " \
  230. "${devnum}:${distro_bootpart} " \
  231. "bootfstype; then " \
  232. "run scan_dev_for_boot; " \
  233. "fi; " \
  234. "done\0" \
  235. "boot_a_script=" \
  236. "load ${devtype} ${devnum}:${distro_bootpart} " \
  237. "${scriptaddr} ${prefix}${script}; " \
  238. "env exists secureboot && load ${devtype} " \
  239. "${devnum}:${distro_bootpart} " \
  240. "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
  241. "env exists secureboot " \
  242. "&& esbc_validate ${scripthdraddr};" \
  243. "source ${scriptaddr}\0" \
  244. "qspi_bootcmd=echo Trying load from qspi..;" \
  245. "sf probe && sf read $load_addr " \
  246. "$kernel_start $kernel_size; env exists secureboot " \
  247. "&& sf read $kernelheader_addr_r $kernelheader_start " \
  248. "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
  249. "bootm $load_addr#$board\0" \
  250. "nand_bootcmd=echo Trying load from nand..;" \
  251. "nand info; nand read $load_addr " \
  252. "$kernel_start $kernel_size; env exists secureboot " \
  253. "&& nand read $kernelheader_addr_r $kernelheader_start " \
  254. "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
  255. "bootm $load_addr#$board\0" \
  256. "nor_bootcmd=echo Trying load from nor..;" \
  257. "cp.b $kernel_addr $load_addr " \
  258. "$kernel_size; env exists secureboot " \
  259. "&& cp.b $kernelheader_addr $kernelheader_addr_r " \
  260. "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
  261. "bootm $load_addr#$board\0" \
  262. "sd_bootcmd=echo Trying load from SD ..;" \
  263. "mmcinfo; mmc read $load_addr " \
  264. "$kernel_addr_sd $kernel_size_sd && " \
  265. "env exists secureboot && mmc read $kernelheader_addr_r " \
  266. "$kernelhdr_addr_sd $kernelhdr_size_sd " \
  267. " && esbc_validate ${kernelheader_addr_r};" \
  268. "bootm $load_addr#$board\0"
  269. #endif
  270. /* Monitor Command Prompt */
  271. #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
  272. #define CONFIG_SYS_MAXARGS 64 /* max command args */
  273. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  274. #include <asm/arch/soc.h>
  275. #endif /* __LS1046A_COMMON_H */