ls1021atsn.h 7.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0
  2. * Copyright 2016-2019 NXP Semiconductors
  3. * Copyright 2019 Vladimir Oltean <olteanv@gmail.com>
  4. */
  5. #ifndef __CONFIG_H
  6. #define __CONFIG_H
  7. #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
  8. #define CONFIG_SYS_FSL_CLK
  9. #define CONFIG_DEEP_SLEEP
  10. /* Size of malloc() pool */
  11. #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
  12. #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
  13. #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
  14. /* XHCI Support - enabled by default */
  15. #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
  16. #define CONFIG_SYS_CLK_FREQ 100000000
  17. #define CONFIG_DDR_CLK_FREQ 100000000
  18. #define DDR_SDRAM_CFG 0x470c0008
  19. #define DDR_CS0_BNDS 0x008000bf
  20. #define DDR_CS0_CONFIG 0x80014302
  21. #define DDR_TIMING_CFG_0 0x50550004
  22. #define DDR_TIMING_CFG_1 0xbcb38c56
  23. #define DDR_TIMING_CFG_2 0x0040d120
  24. #define DDR_TIMING_CFG_3 0x010e1000
  25. #define DDR_TIMING_CFG_4 0x00000001
  26. #define DDR_TIMING_CFG_5 0x03401400
  27. #define DDR_SDRAM_CFG_2 0x00401010
  28. #define DDR_SDRAM_MODE 0x00061c60
  29. #define DDR_SDRAM_MODE_2 0x00180000
  30. #define DDR_SDRAM_INTERVAL 0x18600618
  31. #define DDR_DDR_WRLVL_CNTL 0x8655f605
  32. #define DDR_DDR_WRLVL_CNTL_2 0x05060607
  33. #define DDR_DDR_WRLVL_CNTL_3 0x05050505
  34. #define DDR_DDR_CDR1 0x80040000
  35. #define DDR_DDR_CDR2 0x00000001
  36. #define DDR_SDRAM_CLK_CNTL 0x02000000
  37. #define DDR_DDR_ZQ_CNTL 0x89080600
  38. #define DDR_CS0_CONFIG_2 0
  39. #define DDR_SDRAM_CFG_MEM_EN 0x80000000
  40. #define SDRAM_CFG2_D_INIT 0x00000010
  41. #define DDR_CDR2_VREF_TRAIN_EN 0x00000080
  42. #define SDRAM_CFG2_FRC_SR 0x80000000
  43. #define SDRAM_CFG_BI 0x00000001
  44. #ifdef CONFIG_RAMBOOT_PBL
  45. #define CONFIG_SYS_FSL_PBL_PBI \
  46. "board/freescale/ls1021atsn/ls102xa_pbi.cfg"
  47. #endif
  48. #ifdef CONFIG_SD_BOOT
  49. #define CONFIG_SYS_FSL_PBL_RCW \
  50. "board/freescale/ls1021atsn/ls102xa_rcw_sd.cfg"
  51. #ifdef CONFIG_NXP_ESBC
  52. #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
  53. #endif /* ifdef CONFIG_NXP_ESBC */
  54. #define CONFIG_SPL_MAX_SIZE 0x1a000
  55. #define CONFIG_SPL_STACK 0x1001d000
  56. #define CONFIG_SPL_PAD_TO 0x1c000
  57. #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
  58. CONFIG_SYS_MONITOR_LEN)
  59. #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
  60. #define CONFIG_SPL_BSS_START_ADDR 0x80100000
  61. #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
  62. #ifdef CONFIG_U_BOOT_HDR_SIZE
  63. /*
  64. * HDR would be appended at end of image and copied to DDR along
  65. * with U-Boot image. Here u-boot max. size is 512K. So if binary
  66. * size increases then increase this size in case of secure boot as
  67. * it uses raw U-Boot image instead of FIT image.
  68. */
  69. #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
  70. #else
  71. #define CONFIG_SYS_MONITOR_LEN 0x100000
  72. #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
  73. #endif
  74. #define CONFIG_NR_DRAM_BANKS 1
  75. #define PHYS_SDRAM 0x80000000
  76. #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
  77. #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
  78. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  79. #define CONFIG_CHIP_SELECTS_PER_CTRL 4
  80. /* Serial Port */
  81. #define CONFIG_SYS_NS16550_SERIAL
  82. #ifndef CONFIG_DM_SERIAL
  83. #define CONFIG_SYS_NS16550_REG_SIZE 1
  84. #endif
  85. #define CONFIG_SYS_NS16550_CLK get_serial_clock()
  86. /* I2C */
  87. #ifndef CONFIG_DM_I2C
  88. #define CONFIG_SYS_I2C
  89. #else
  90. #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
  91. #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
  92. #endif
  93. #define CONFIG_SYS_I2C_MXC
  94. #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
  95. #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
  96. #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
  97. /* EEPROM */
  98. #define CONFIG_ID_EEPROM
  99. #define CONFIG_SYS_I2C_EEPROM_NXID
  100. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  101. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x51
  102. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
  103. /* QSPI */
  104. #define FSL_QSPI_FLASH_SIZE (1 << 24)
  105. #define FSL_QSPI_FLASH_NUM 2
  106. /* PCIe */
  107. #define CONFIG_PCIE1 /* PCIE controller 1 */
  108. #define CONFIG_PCIE2 /* PCIE controller 2 */
  109. #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
  110. #ifdef CONFIG_PCI
  111. #define CONFIG_PCI_SCAN_SHOW
  112. #endif
  113. #define CONFIG_LAYERSCAPE_NS_ACCESS
  114. #define COUNTER_FREQUENCY 12500000
  115. #define CONFIG_HWCONFIG
  116. #define HWCONFIG_BUFFER_SIZE 256
  117. #define CONFIG_FSL_DEVICE_DISABLE
  118. #define BOOT_TARGET_DEVICES(func) \
  119. func(MMC, mmc, 0) \
  120. func(USB, usb, 0) \
  121. func(DHCP, dhcp, na)
  122. #include <config_distro_bootcmd.h>
  123. #define CONFIG_EXTRA_ENV_SETTINGS \
  124. "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
  125. "initrd_high=0xffffffff\0" \
  126. "fdt_addr=0x64f00000\0" \
  127. "kernel_addr=0x61000000\0" \
  128. "kernelheader_addr=0x60800000\0" \
  129. "scriptaddr=0x80000000\0" \
  130. "scripthdraddr=0x80080000\0" \
  131. "fdtheader_addr_r=0x80100000\0" \
  132. "kernelheader_addr_r=0x80200000\0" \
  133. "kernel_addr_r=0x80008000\0" \
  134. "kernelheader_size=0x40000\0" \
  135. "fdt_addr_r=0x8f000000\0" \
  136. "ramdisk_addr_r=0xa0000000\0" \
  137. "load_addr=0x80008000\0" \
  138. "kernel_size=0x2800000\0" \
  139. "kernel_addr_sd=0x8000\0" \
  140. "kernel_size_sd=0x14000\0" \
  141. "kernelhdr_addr_sd=0x4000\0" \
  142. "kernelhdr_size_sd=0x10\0" \
  143. BOOTENV \
  144. "boot_scripts=ls1021atsn_boot.scr\0" \
  145. "boot_script_hdr=hdr_ls1021atsn_bs.out\0" \
  146. "scan_dev_for_boot_part=" \
  147. "part list ${devtype} ${devnum} devplist; " \
  148. "env exists devplist || setenv devplist 1; " \
  149. "for distro_bootpart in ${devplist}; do " \
  150. "if fstype ${devtype} " \
  151. "${devnum}:${distro_bootpart} " \
  152. "bootfstype; then " \
  153. "run scan_dev_for_boot; " \
  154. "fi; " \
  155. "done\0" \
  156. "scan_dev_for_boot=" \
  157. "echo Scanning ${devtype} " \
  158. "${devnum}:${distro_bootpart}...; " \
  159. "for prefix in ${boot_prefixes}; do " \
  160. "run scan_dev_for_scripts; " \
  161. "run scan_dev_for_extlinux; " \
  162. "done;" \
  163. "\0" \
  164. "boot_a_script=" \
  165. "load ${devtype} ${devnum}:${distro_bootpart} " \
  166. "${scriptaddr} ${prefix}${script}; " \
  167. "env exists secureboot && load ${devtype} " \
  168. "${devnum}:${distro_bootpart} " \
  169. "${scripthdraddr} ${prefix}${boot_script_hdr} " \
  170. "&& esbc_validate ${scripthdraddr};" \
  171. "source ${scriptaddr}\0" \
  172. "qspi_bootcmd=echo Trying load from qspi..;" \
  173. "sf probe && sf read $load_addr " \
  174. "$kernel_addr $kernel_size; env exists secureboot " \
  175. "&& sf read $kernelheader_addr_r $kernelheader_addr " \
  176. "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
  177. "bootm $load_addr#$board\0" \
  178. "sd_bootcmd=echo Trying load from SD ..;" \
  179. "mmcinfo && mmc read $load_addr " \
  180. "$kernel_addr_sd $kernel_size_sd && " \
  181. "env exists secureboot && mmc read $kernelheader_addr_r " \
  182. "$kernelhdr_addr_sd $kernelhdr_size_sd " \
  183. " && esbc_validate ${kernelheader_addr_r};" \
  184. "bootm $load_addr#$board\0"
  185. /* Miscellaneous configurable options */
  186. #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
  187. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  188. #define CONFIG_SYS_PBSIZE \
  189. (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
  190. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  191. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  192. #define CONFIG_SYS_LOAD_ADDR 0x82000000
  193. #define CONFIG_LS102XA_STREAM_ID
  194. #define CONFIG_SYS_INIT_SP_OFFSET \
  195. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  196. #define CONFIG_SYS_INIT_SP_ADDR \
  197. (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
  198. #ifdef CONFIG_SPL_BUILD
  199. #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
  200. #else
  201. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  202. #endif
  203. /* Environment */
  204. #define CONFIG_SYS_BOOTM_LEN 0x8000000 /* 128 MB */
  205. #endif