ls1021aqds.h 14 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2014 Freescale Semiconductor, Inc.
  4. * Copyright 2019 NXP
  5. */
  6. #ifndef __CONFIG_H
  7. #define __CONFIG_H
  8. #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
  9. #define CONFIG_SYS_FSL_CLK
  10. #define CONFIG_SKIP_LOWLEVEL_INIT
  11. #define CONFIG_DEEP_SLEEP
  12. /*
  13. * Size of malloc() pool
  14. */
  15. #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
  16. #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
  17. #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
  18. #ifndef __ASSEMBLY__
  19. unsigned long get_board_sys_clk(void);
  20. unsigned long get_board_ddr_clk(void);
  21. #endif
  22. #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  23. #define CONFIG_SYS_CLK_FREQ 100000000
  24. #define CONFIG_DDR_CLK_FREQ 100000000
  25. #define CONFIG_QIXIS_I2C_ACCESS
  26. #else
  27. #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
  28. #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
  29. #endif
  30. #ifdef CONFIG_RAMBOOT_PBL
  31. #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021aqds/ls102xa_pbi.cfg
  32. #endif
  33. #ifdef CONFIG_SD_BOOT
  34. #ifdef CONFIG_SD_BOOT_QSPI
  35. #define CONFIG_SYS_FSL_PBL_RCW \
  36. board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg
  37. #else
  38. #define CONFIG_SYS_FSL_PBL_RCW \
  39. board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg
  40. #endif
  41. #define CONFIG_SPL_MAX_SIZE 0x1a000
  42. #define CONFIG_SPL_STACK 0x1001d000
  43. #define CONFIG_SPL_PAD_TO 0x1c000
  44. #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
  45. CONFIG_SYS_MONITOR_LEN)
  46. #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
  47. #define CONFIG_SPL_BSS_START_ADDR 0x80100000
  48. #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
  49. #define CONFIG_SYS_MONITOR_LEN 0xc0000
  50. #endif
  51. #ifdef CONFIG_NAND_BOOT
  52. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
  53. #define CONFIG_SPL_MAX_SIZE 0x1a000
  54. #define CONFIG_SPL_STACK 0x1001d000
  55. #define CONFIG_SPL_PAD_TO 0x1c000
  56. #define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10)
  57. #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
  58. #define CONFIG_SYS_NAND_PAGE_SIZE 2048
  59. #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
  60. #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
  61. #define CONFIG_SYS_SPL_MALLOC_START 0x80200000
  62. #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
  63. #define CONFIG_SPL_BSS_START_ADDR 0x80100000
  64. #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
  65. #define CONFIG_SYS_MONITOR_LEN 0x80000
  66. #endif
  67. #define CONFIG_DDR_SPD
  68. #define SPD_EEPROM_ADDRESS 0x51
  69. #define CONFIG_SYS_SPD_BUS_NUM 0
  70. #ifndef CONFIG_SYS_FSL_DDR4
  71. #define CONFIG_SYS_DDR_RAW_TIMING
  72. #endif
  73. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  74. #define CONFIG_CHIP_SELECTS_PER_CTRL 4
  75. #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
  76. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  77. #define CONFIG_DDR_ECC
  78. #ifdef CONFIG_DDR_ECC
  79. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  80. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  81. #endif
  82. /*
  83. * IFC Definitions
  84. */
  85. #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  86. #define CONFIG_FSL_IFC
  87. #define CONFIG_SYS_FLASH_BASE 0x60000000
  88. #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
  89. #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
  90. #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  91. CSPR_PORT_SIZE_16 | \
  92. CSPR_MSEL_NOR | \
  93. CSPR_V)
  94. #define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
  95. #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
  96. + 0x8000000) | \
  97. CSPR_PORT_SIZE_16 | \
  98. CSPR_MSEL_NOR | \
  99. CSPR_V)
  100. #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
  101. #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
  102. CSOR_NOR_TRHZ_80)
  103. #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
  104. FTIM0_NOR_TEADC(0x5) | \
  105. FTIM0_NOR_TEAHC(0x5))
  106. #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
  107. FTIM1_NOR_TRAD_NOR(0x1a) | \
  108. FTIM1_NOR_TSEQRAD_NOR(0x13))
  109. #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
  110. FTIM2_NOR_TCH(0x4) | \
  111. FTIM2_NOR_TWPH(0xe) | \
  112. FTIM2_NOR_TWP(0x1c))
  113. #define CONFIG_SYS_NOR_FTIM3 0
  114. #define CONFIG_SYS_FLASH_QUIET_TEST
  115. #define CONFIG_FLASH_SHOW_PROGRESS 45
  116. #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
  117. #define CONFIG_SYS_WRITE_SWAPPED_DATA
  118. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  119. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  120. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  121. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  122. #define CONFIG_SYS_FLASH_EMPTY_INFO
  123. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
  124. CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
  125. /*
  126. * NAND Flash Definitions
  127. */
  128. #define CONFIG_NAND_FSL_IFC
  129. #define CONFIG_SYS_NAND_BASE 0x7e800000
  130. #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
  131. #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
  132. #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  133. | CSPR_PORT_SIZE_8 \
  134. | CSPR_MSEL_NAND \
  135. | CSPR_V)
  136. #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
  137. #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  138. | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  139. | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
  140. | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
  141. | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
  142. | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
  143. | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
  144. #define CONFIG_SYS_NAND_ONFI_DETECTION
  145. #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
  146. FTIM0_NAND_TWP(0x18) | \
  147. FTIM0_NAND_TWCHT(0x7) | \
  148. FTIM0_NAND_TWH(0xa))
  149. #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
  150. FTIM1_NAND_TWBE(0x39) | \
  151. FTIM1_NAND_TRR(0xe) | \
  152. FTIM1_NAND_TRP(0x18))
  153. #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
  154. FTIM2_NAND_TREH(0xa) | \
  155. FTIM2_NAND_TWHRE(0x1e))
  156. #define CONFIG_SYS_NAND_FTIM3 0x0
  157. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  158. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  159. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  160. #endif
  161. /*
  162. * QIXIS Definitions
  163. */
  164. #define CONFIG_FSL_QIXIS
  165. #ifdef CONFIG_FSL_QIXIS
  166. #define QIXIS_BASE 0x7fb00000
  167. #define QIXIS_BASE_PHYS QIXIS_BASE
  168. #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
  169. #define QIXIS_LBMAP_SWITCH 6
  170. #define QIXIS_LBMAP_MASK 0x0f
  171. #define QIXIS_LBMAP_SHIFT 0
  172. #define QIXIS_LBMAP_DFLTBANK 0x00
  173. #define QIXIS_LBMAP_ALTBANK 0x04
  174. #define QIXIS_PWR_CTL 0x21
  175. #define QIXIS_PWR_CTL_POWEROFF 0x80
  176. #define QIXIS_RST_CTL_RESET 0x44
  177. #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
  178. #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
  179. #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
  180. #define QIXIS_CTL_SYS 0x5
  181. #define QIXIS_CTL_SYS_EVTSW_MASK 0x0c
  182. #define QIXIS_CTL_SYS_EVTSW_IRQ 0x04
  183. #define QIXIS_RST_FORCE_3 0x45
  184. #define QIXIS_RST_FORCE_3_PCIESLOT1 0x80
  185. #define QIXIS_PWR_CTL2 0x21
  186. #define QIXIS_PWR_CTL2_PCTL 0x2
  187. #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
  188. #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
  189. CSPR_PORT_SIZE_8 | \
  190. CSPR_MSEL_GPCM | \
  191. CSPR_V)
  192. #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
  193. #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
  194. CSOR_NOR_NOR_MODE_AVD_NOR | \
  195. CSOR_NOR_TRHZ_80)
  196. /*
  197. * QIXIS Timing parameters for IFC GPCM
  198. */
  199. #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \
  200. FTIM0_GPCM_TEADC(0xe) | \
  201. FTIM0_GPCM_TEAHC(0xe))
  202. #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \
  203. FTIM1_GPCM_TRAD(0x1f))
  204. #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \
  205. FTIM2_GPCM_TCH(0xe) | \
  206. FTIM2_GPCM_TWP(0xf0))
  207. #define CONFIG_SYS_FPGA_FTIM3 0x0
  208. #endif
  209. #if defined(CONFIG_NAND_BOOT)
  210. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
  211. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
  212. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
  213. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
  214. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
  215. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
  216. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
  217. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
  218. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
  219. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
  220. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  221. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  222. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  223. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  224. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  225. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  226. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
  227. #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
  228. #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
  229. #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
  230. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
  231. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
  232. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
  233. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
  234. #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
  235. #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
  236. #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
  237. #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
  238. #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
  239. #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
  240. #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
  241. #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
  242. #else
  243. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
  244. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
  245. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  246. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  247. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  248. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  249. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  250. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  251. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
  252. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
  253. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  254. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  255. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  256. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  257. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  258. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  259. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
  260. #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
  261. #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
  262. #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
  263. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
  264. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
  265. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
  266. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
  267. #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
  268. #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
  269. #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
  270. #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
  271. #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
  272. #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
  273. #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
  274. #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
  275. #endif
  276. /*
  277. * Serial Port
  278. */
  279. #ifdef CONFIG_LPUART
  280. #define CONFIG_LPUART_32B_REG
  281. #else
  282. #define CONFIG_SYS_NS16550_SERIAL
  283. #ifndef CONFIG_DM_SERIAL
  284. #define CONFIG_SYS_NS16550_REG_SIZE 1
  285. #endif
  286. #define CONFIG_SYS_NS16550_CLK get_serial_clock()
  287. #endif
  288. /*
  289. * I2C
  290. */
  291. #ifndef CONFIG_DM_I2C
  292. #define CONFIG_SYS_I2C
  293. #else
  294. #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
  295. #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
  296. #endif
  297. #define CONFIG_SYS_I2C_MXC
  298. #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
  299. #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
  300. #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
  301. /* EEPROM */
  302. #define CONFIG_ID_EEPROM
  303. #define CONFIG_SYS_I2C_EEPROM_NXID
  304. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  305. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  306. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  307. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
  308. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
  309. /*
  310. * I2C bus multiplexer
  311. */
  312. #define I2C_MUX_PCA_ADDR_PRI 0x77
  313. #define I2C_MUX_CH_DEFAULT 0x8
  314. #define I2C_MUX_CH_CH7301 0xC
  315. /*
  316. * MMC
  317. */
  318. /*
  319. * Video
  320. */
  321. #ifdef CONFIG_VIDEO_FSL_DCU_FB
  322. #define CONFIG_VIDEO_LOGO
  323. #define CONFIG_VIDEO_BMP_LOGO
  324. #define CONFIG_FSL_DIU_CH7301
  325. #define CONFIG_SYS_I2C_DVI_BUS_NUM 0
  326. #define CONFIG_SYS_I2C_QIXIS_ADDR 0x66
  327. #define CONFIG_SYS_I2C_DVI_ADDR 0x75
  328. #endif
  329. /*
  330. * eTSEC
  331. */
  332. #ifdef CONFIG_TSEC_ENET
  333. #define CONFIG_MII_DEFAULT_TSEC 3
  334. #define CONFIG_TSEC1 1
  335. #define CONFIG_TSEC1_NAME "eTSEC1"
  336. #define CONFIG_TSEC2 1
  337. #define CONFIG_TSEC2_NAME "eTSEC2"
  338. #define CONFIG_TSEC3 1
  339. #define CONFIG_TSEC3_NAME "eTSEC3"
  340. #define TSEC1_PHY_ADDR 1
  341. #define TSEC2_PHY_ADDR 2
  342. #define TSEC3_PHY_ADDR 3
  343. #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  344. #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  345. #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  346. #define TSEC1_PHYIDX 0
  347. #define TSEC2_PHYIDX 0
  348. #define TSEC3_PHYIDX 0
  349. #define CONFIG_ETHPRIME "eTSEC1"
  350. #define CONFIG_HAS_ETH0
  351. #define CONFIG_HAS_ETH1
  352. #define CONFIG_HAS_ETH2
  353. #define CONFIG_FSL_SGMII_RISER 1
  354. #define SGMII_RISER_PHY_OFFSET 0x1b
  355. #ifdef CONFIG_FSL_SGMII_RISER
  356. #define CONFIG_SYS_TBIPA_VALUE 8
  357. #endif
  358. #endif
  359. /* PCIe */
  360. #define CONFIG_PCIE1 /* PCIE controller 1 */
  361. #define CONFIG_PCIE2 /* PCIE controller 2 */
  362. #ifdef CONFIG_PCI
  363. #define CONFIG_PCI_SCAN_SHOW
  364. #endif
  365. #define CONFIG_CMDLINE_TAG
  366. #define CONFIG_PEN_ADDR_BIG_ENDIAN
  367. #define CONFIG_LAYERSCAPE_NS_ACCESS
  368. #define CONFIG_SMP_PEN_ADDR 0x01ee0200
  369. #define COUNTER_FREQUENCY 12500000
  370. #define CONFIG_HWCONFIG
  371. #define HWCONFIG_BUFFER_SIZE 256
  372. #define CONFIG_FSL_DEVICE_DISABLE
  373. #define CONFIG_SYS_QE_FW_ADDR 0x60940000
  374. #ifdef CONFIG_LPUART
  375. #define CONFIG_EXTRA_ENV_SETTINGS \
  376. "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
  377. "initrd_high=0xffffffff\0" \
  378. "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
  379. #else
  380. #define CONFIG_EXTRA_ENV_SETTINGS \
  381. "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
  382. "initrd_high=0xffffffff\0" \
  383. "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
  384. #endif
  385. /*
  386. * Miscellaneous configurable options
  387. */
  388. #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
  389. #define CONFIG_SYS_LOAD_ADDR 0x82000000
  390. #define CONFIG_LS102XA_STREAM_ID
  391. #define CONFIG_SYS_INIT_SP_OFFSET \
  392. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  393. #define CONFIG_SYS_INIT_SP_ADDR \
  394. (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
  395. #ifdef CONFIG_SPL_BUILD
  396. #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
  397. #else
  398. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  399. #endif
  400. /*
  401. * Environment
  402. */
  403. #include <asm/fsl_secure_boot.h>
  404. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  405. #endif