edminiv2.h 5.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
  4. *
  5. * Based on original Kirkwood support which is
  6. * (C) Copyright 2009
  7. * Marvell Semiconductor <www.marvell.com>
  8. * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
  9. */
  10. #ifndef _CONFIG_EDMINIV2_H
  11. #define _CONFIG_EDMINIV2_H
  12. /*
  13. * SPL
  14. */
  15. #define CONFIG_SPL_MAX_SIZE 0x0000fff0
  16. #define CONFIG_SPL_STACK 0x00020000
  17. #define CONFIG_SPL_BSS_START_ADDR 0x00020000
  18. #define CONFIG_SPL_BSS_MAX_SIZE 0x0001ffff
  19. #define CONFIG_SYS_SPL_MALLOC_START 0x00040000
  20. #define CONFIG_SYS_SPL_MALLOC_SIZE 0x0001ffff
  21. #define CONFIG_SYS_UBOOT_BASE 0xfff90000
  22. #define CONFIG_SYS_UBOOT_START 0x00800000
  23. /*
  24. * High Level Configuration Options (easy to change)
  25. */
  26. #define CONFIG_FEROCEON 1 /* CPU Core subversion */
  27. #define CONFIG_88F5182 1 /* SOC Name */
  28. #include <asm/arch/orion5x.h>
  29. /*
  30. * CLKs configurations
  31. */
  32. /*
  33. * Board-specific values for Orion5x MPP low level init:
  34. * - MPPs 12 to 15 are SATA LEDs (mode 5)
  35. * - Others are GPIO/unused (mode 3 for MPP0, mode 5 for
  36. * MPP16 to MPP19, mode 0 for others
  37. */
  38. #define ORION5X_MPP0_7 0x00000003
  39. #define ORION5X_MPP8_15 0x55550000
  40. #define ORION5X_MPP16_23 0x00005555
  41. /*
  42. * Board-specific values for Orion5x GPIO low level init:
  43. * - GPIO3 is input (RTC interrupt)
  44. * - GPIO16 is Power LED control (0 = on, 1 = off)
  45. * - GPIO17 is Power LED source select (0 = CPLD, 1 = GPIO16)
  46. * - GPIO18 is Power Button status (0 = Released, 1 = Pressed)
  47. * - GPIO19 is SATA disk power toggle (toggles on 0-to-1)
  48. * - GPIO22 is SATA disk power status ()
  49. * - GPIO23 is supply status for SATA disk ()
  50. * - GPIO24 is supply control for board (write 1 to power off)
  51. * Last GPIO is 25, further bits are supposed to be 0.
  52. * Enable mask has ones for INPUT, 0 for OUTPUT.
  53. * Default is LED ON, board ON :)
  54. */
  55. #define ORION5X_GPIO_OUT_ENABLE 0xfef4f0ca
  56. #define ORION5X_GPIO_OUT_VALUE 0x00000000
  57. #define ORION5X_GPIO_IN_POLARITY 0x000000d0
  58. /*
  59. * NS16550 Configuration
  60. */
  61. #define CONFIG_SYS_NS16550_SERIAL
  62. #define CONFIG_SYS_NS16550_REG_SIZE (-4)
  63. #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
  64. #define CONFIG_SYS_NS16550_COM1 ORION5X_UART0_BASE
  65. /*
  66. * Serial Port configuration
  67. * The following definitions let you select what serial you want to use
  68. * for your console driver.
  69. */
  70. #define CONFIG_SYS_BAUDRATE_TABLE \
  71. { 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 }
  72. /*
  73. * FLASH configuration
  74. */
  75. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
  76. #define CONFIG_SYS_MAX_FLASH_SECT 11 /* max num of sects on one chip */
  77. #define CONFIG_SYS_FLASH_BASE 0xfff80000
  78. /* auto boot */
  79. /*
  80. * For booting Linux, the board info and command line data
  81. * have to be in the first 8 MB of memory, since this is
  82. * the maximum mapped by the Linux kernel during initialization.
  83. */
  84. #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
  85. #define CONFIG_INITRD_TAG 1 /* enable INITRD tag */
  86. #define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */
  87. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */
  88. /*
  89. * Network
  90. */
  91. #ifdef CONFIG_CMD_NET
  92. #define CONFIG_MVGBE_PORTS {1} /* enable port 0 only */
  93. #define CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION /* don't randomize MAC */
  94. #define CONFIG_PHY_BASE_ADR 0x8
  95. #define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */
  96. #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
  97. #endif
  98. /*
  99. * IDE
  100. */
  101. #ifdef CONFIG_IDE
  102. #define __io
  103. #define CONFIG_IDE_PREINIT
  104. /* ED Mini V has an IDE-compatible SATA connector for port 1 */
  105. #define CONFIG_MVSATA_IDE_USE_PORT1
  106. /* Needs byte-swapping for ATA data register */
  107. #define CONFIG_IDE_SWAP_IO
  108. /* Data, registers and alternate blocks are at the same offset */
  109. #define CONFIG_SYS_ATA_DATA_OFFSET (0x0100)
  110. #define CONFIG_SYS_ATA_REG_OFFSET (0x0100)
  111. #define CONFIG_SYS_ATA_ALT_OFFSET (0x0100)
  112. /* Each 8-bit ATA register is aligned to a 4-bytes address */
  113. #define CONFIG_SYS_ATA_STRIDE 4
  114. /* Controller supports 48-bits LBA addressing */
  115. #define CONFIG_LBA48
  116. /* A single bus, a single device */
  117. #define CONFIG_SYS_IDE_MAXBUS 1
  118. #define CONFIG_SYS_IDE_MAXDEVICE 1
  119. /* ATA registers base is at SATA controller base */
  120. #define CONFIG_SYS_ATA_BASE_ADDR ORION5X_SATA_BASE
  121. /* ATA bus 0 is orion5x port 1 on ED Mini V2 */
  122. #define CONFIG_SYS_ATA_IDE0_OFFSET ORION5X_SATA_PORT1_OFFSET
  123. /* end of IDE defines */
  124. #endif /* CMD_IDE */
  125. /*
  126. * Common USB/EHCI configuration
  127. */
  128. #ifdef CONFIG_CMD_USB
  129. #define ORION5X_USB20_HOST_PORT_BASE ORION5X_USB20_PORT0_BASE
  130. #endif /* CONFIG_CMD_USB */
  131. /*
  132. * I2C related stuff
  133. */
  134. #ifdef CONFIG_CMD_I2C
  135. #define CONFIG_SYS_I2C
  136. #define CONFIG_SYS_I2C_MVTWSI
  137. #define CONFIG_I2C_MVTWSI_BASE0 ORION5X_TWSI_BASE
  138. #define CONFIG_SYS_I2C_SLAVE 0x0
  139. #define CONFIG_SYS_I2C_SPEED 100000
  140. #endif
  141. /*
  142. * Environment variables configurations
  143. */
  144. /*
  145. * Size of malloc() pool
  146. */
  147. #define CONFIG_SYS_MALLOC_LEN (1024 * 256) /* 256kB for malloc() */
  148. /*
  149. * Other required minimal configurations
  150. */
  151. #define CONFIG_SYS_LOAD_ADDR 0x00800000
  152. #define CONFIG_SYS_RESET_ADDRESS 0xffff0000
  153. /* Enable command line editing */
  154. /* provide extensive help */
  155. /* additions for new relocation code, must be added to all boards */
  156. #define CONFIG_SYS_SDRAM_BASE 0
  157. #define CONFIG_SYS_INIT_SP_ADDR \
  158. (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
  159. #endif /* _CONFIG_EDMINIV2_H */