eb_cpu5282.h 7.7 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Configuation settings for the BuS EB+CPU5283 boards (aka EB+MCF-EV123)
  4. *
  5. * (C) Copyright 2005-2009 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
  6. */
  7. #ifndef _CONFIG_EB_CPU5282_H_
  8. #define _CONFIG_EB_CPU5282_H_
  9. #undef CONFIG_SYS_HALT_BEFOR_RAM_JUMP
  10. /*----------------------------------------------------------------------*
  11. * High Level Configuration Options (easy to change) *
  12. *----------------------------------------------------------------------*/
  13. #define CONFIG_MCFUART
  14. #define CONFIG_SYS_UART_PORT (0)
  15. #undef CONFIG_MONITOR_IS_IN_RAM /* starts uboot direct */
  16. #define CONFIG_BOOTCOMMAND "printenv"
  17. /*----------------------------------------------------------------------*
  18. * Options *
  19. *----------------------------------------------------------------------*/
  20. #define CONFIG_BOOT_RETRY_TIME -1
  21. #define CONFIG_RESET_TO_RETRY
  22. #define CONFIG_HW_WATCHDOG
  23. #define STATUS_LED_ACTIVE 0
  24. /*----------------------------------------------------------------------*
  25. * Configuration for environment *
  26. * Environment is in the second sector of the first 256k of flash *
  27. *----------------------------------------------------------------------*/
  28. /*
  29. * BOOTP options
  30. */
  31. #define CONFIG_BOOTP_BOOTFILESIZE
  32. #define CONFIG_MCFTMR
  33. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  34. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  35. #define CONFIG_SYS_LOAD_ADDR 0x20000
  36. /*#define CONFIG_SYS_DRAM_TEST 1 */
  37. #undef CONFIG_SYS_DRAM_TEST
  38. /*----------------------------------------------------------------------*
  39. * Clock and PLL Configuration *
  40. *----------------------------------------------------------------------*/
  41. #define CONFIG_SYS_CLK 80000000 /* 8MHz * 8 */
  42. /* PLL Configuration: Ext Clock * 8 (see table 9-4 of MCF user manual) */
  43. #define CONFIG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */
  44. #define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */
  45. /*----------------------------------------------------------------------*
  46. * Network *
  47. *----------------------------------------------------------------------*/
  48. #ifdef CONFIG_MCFFEC
  49. #define CONFIG_MII_INIT 1
  50. #define CONFIG_SYS_DISCOVER_PHY
  51. #define CONFIG_SYS_RX_ETH_BUFFER 8
  52. #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  53. #define CONFIG_OVERWRITE_ETHADDR_ONCE
  54. #endif
  55. /*-------------------------------------------------------------------------
  56. * Low Level Configuration Settings
  57. * (address mappings, register initial values, etc.)
  58. * You should know what you are doing if you make changes here.
  59. *-----------------------------------------------------------------------*/
  60. #define CONFIG_SYS_MBAR 0x40000000
  61. /*-----------------------------------------------------------------------
  62. * Definitions for initial stack pointer and data area (in DPRAM)
  63. *-----------------------------------------------------------------------*/
  64. #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
  65. #define CONFIG_SYS_INIT_RAM_SIZE 0x10000
  66. #define CONFIG_SYS_GBL_DATA_OFFSET \
  67. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  68. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  69. /*-----------------------------------------------------------------------
  70. * Start addresses for the final memory configuration
  71. * (Set up by the startup code)
  72. * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  73. */
  74. #define CONFIG_SYS_SDRAM_BASE0 0x00000000
  75. #define CONFIG_SYS_SDRAM_SIZE0 16 /* SDRAM size in MB */
  76. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM_BASE0
  77. #define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM_SIZE0
  78. #define CONFIG_SYS_MONITOR_LEN 0x20000
  79. #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
  80. #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
  81. /*
  82. * For booting Linux, the board info and command line data
  83. * have to be in the first 8 MB of memory, since this is
  84. * the maximum mapped by the Linux kernel during initialization ??
  85. */
  86. #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  87. /*-----------------------------------------------------------------------
  88. * FLASH organization
  89. */
  90. #define CONFIG_FLASH_SHOW_PROGRESS 45
  91. #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
  92. #define CONFIG_SYS_INT_FLASH_BASE 0xF0000000
  93. #define CONFIG_SYS_INT_FLASH_ENABLE 0x21
  94. #define CONFIG_SYS_MAX_FLASH_SECT 128
  95. #define CONFIG_SYS_MAX_FLASH_BANKS 1
  96. #define CONFIG_SYS_FLASH_ERASE_TOUT 10000000
  97. #define CONFIG_SYS_FLASH_SIZE 16*1024*1024
  98. #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
  99. #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
  100. /*-----------------------------------------------------------------------
  101. * Cache Configuration
  102. */
  103. #define CONFIG_SYS_CACHELINE_SIZE 16
  104. #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
  105. CONFIG_SYS_INIT_RAM_SIZE - 8)
  106. #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
  107. CONFIG_SYS_INIT_RAM_SIZE - 4)
  108. #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM)
  109. #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
  110. CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
  111. CF_ACR_EN | CF_ACR_SM_ALL)
  112. #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \
  113. CF_CACR_CEIB | CF_CACR_DBWE | \
  114. CF_CACR_EUSP)
  115. /*-----------------------------------------------------------------------
  116. * Memory bank definitions
  117. */
  118. #define CONFIG_SYS_CS0_BASE 0xFF000000
  119. #define CONFIG_SYS_CS0_CTRL 0x00001980
  120. #define CONFIG_SYS_CS0_MASK 0x00FF0001
  121. #define CONFIG_SYS_CS2_BASE 0xE0000000
  122. #define CONFIG_SYS_CS2_CTRL 0x00001980
  123. #define CONFIG_SYS_CS2_MASK 0x000F0001
  124. #define CONFIG_SYS_CS3_BASE 0xE0100000
  125. #define CONFIG_SYS_CS3_CTRL 0x00001980
  126. #define CONFIG_SYS_CS3_MASK 0x000F0001
  127. /*-----------------------------------------------------------------------
  128. * Port configuration
  129. */
  130. #define CONFIG_SYS_PACNT 0x0000000 /* Port A D[31:24] */
  131. #define CONFIG_SYS_PADDR 0x0000000
  132. #define CONFIG_SYS_PADAT 0x0000000
  133. #define CONFIG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */
  134. #define CONFIG_SYS_PBDDR 0x0000000
  135. #define CONFIG_SYS_PBDAT 0x0000000
  136. #define CONFIG_SYS_PCCNT 0x0000000 /* Port C D[15:08] */
  137. #define CONFIG_SYS_PCDDR 0x0000000
  138. #define CONFIG_SYS_PCDAT 0x0000000
  139. #define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */
  140. #define CONFIG_SYS_PCDDR 0x0000000
  141. #define CONFIG_SYS_PCDAT 0x0000000
  142. #define CONFIG_SYS_PASPAR 0x0F0F
  143. #define CONFIG_SYS_PEHLPAR 0xC0
  144. #define CONFIG_SYS_PUAPAR 0x0F
  145. #define CONFIG_SYS_DDRUA 0x05
  146. #define CONFIG_SYS_PJPAR 0xFF
  147. /*-----------------------------------------------------------------------
  148. * I2C
  149. */
  150. #define CONFIG_SYS_I2C
  151. #define CONFIG_SYS_I2C_FSL
  152. #define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300
  153. #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
  154. #define CONFIG_SYS_FSL_I2C_SPEED 100000
  155. #define CONFIG_SYS_FSL_I2C_SLAVE 0
  156. #ifdef CONFIG_CMD_DATE
  157. #define CONFIG_RTC_DS1338
  158. #define CONFIG_I2C_RTC_ADDR 0x68
  159. #endif
  160. /*-----------------------------------------------------------------------
  161. * VIDEO configuration
  162. */
  163. #ifdef CONFIG_VIDEO
  164. #define CONFIG_VIDEO_VCXK 1
  165. #define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN 2
  166. #define CONFIG_SYS_VCXK_DOUBLEBUFFERED 1
  167. #define CONFIG_SYS_VCXK_BASE CONFIG_SYS_CS2_BASE
  168. #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT MCFGPTB_GPTPORT
  169. #define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR MCFGPTB_GPTDDR
  170. #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN 0x0001
  171. #define CONFIG_SYS_VCXK_ENABLE_PORT MCFGPTB_GPTPORT
  172. #define CONFIG_SYS_VCXK_ENABLE_DDR MCFGPTB_GPTDDR
  173. #define CONFIG_SYS_VCXK_ENABLE_PIN 0x0002
  174. #define CONFIG_SYS_VCXK_REQUEST_PORT MCFGPTB_GPTPORT
  175. #define CONFIG_SYS_VCXK_REQUEST_DDR MCFGPTB_GPTDDR
  176. #define CONFIG_SYS_VCXK_REQUEST_PIN 0x0004
  177. #define CONFIG_SYS_VCXK_INVERT_PORT MCFGPIO_PORTE
  178. #define CONFIG_SYS_VCXK_INVERT_DDR MCFGPIO_DDRE
  179. #define CONFIG_SYS_VCXK_INVERT_PIN MCFGPIO_PORT2
  180. #endif /* CONFIG_VIDEO */
  181. #endif /* _CONFIG_M5282EVB_H */
  182. /*---------------------------------------------------------------------*/