ds414.h 2.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2014 Stefan Roese <sr@denx.de>
  4. */
  5. #ifndef _CONFIG_SYNOLOGY_DS414_H
  6. #define _CONFIG_SYNOLOGY_DS414_H
  7. /*
  8. * High Level Configuration Options (easy to change)
  9. */
  10. /*
  11. * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
  12. * for DDR ECC byte filling in the SPL before loading the main
  13. * U-Boot into it.
  14. */
  15. #define CONFIG_SYS_TCLK 250000000 /* 250MHz */
  16. /* I2C */
  17. #define CONFIG_SYS_I2C
  18. #define CONFIG_SYS_I2C_MVTWSI
  19. #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
  20. #define CONFIG_SYS_I2C_SLAVE 0x0
  21. #define CONFIG_SYS_I2C_SPEED 100000
  22. /* Environment in SPI NOR flash */
  23. #define CONFIG_SYS_NETA_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII
  24. /* PCIe support */
  25. #ifndef CONFIG_SPL_BUILD
  26. #define CONFIG_PCI_SCAN_SHOW
  27. #endif
  28. /* USB/EHCI/XHCI configuration */
  29. #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  30. /* FIXME: broken XHCI support
  31. * Below defines should enable support for the two rear USB3 ports. Sadly, this
  32. * does not work because:
  33. * - xhci-pci seems to not support DM_USB, so with that enabled it is not
  34. * found.
  35. * - USB init fails, controller does not respond in time */
  36. #if !defined(CONFIG_USB_XHCI_HCD)
  37. #define CONFIG_EHCI_IS_TDI
  38. #endif
  39. /* why is this only defined in mv-common.h if CONFIG_DM is undefined? */
  40. /*
  41. * mv-common.h should be defined after CMD configs since it used them
  42. * to enable certain macros
  43. */
  44. #include "mv-common.h"
  45. /*
  46. * Memory layout while starting into the bin_hdr via the
  47. * BootROM:
  48. *
  49. * 0x4000.4000 - 0x4003.4000 headers space (192KiB)
  50. * 0x4000.4030 bin_hdr start address
  51. * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
  52. * 0x4007.fffc BootROM stack top
  53. *
  54. * The address space between 0x4007.fffc and 0x400f.fff is not locked in
  55. * L2 cache thus cannot be used.
  56. */
  57. /* SPL */
  58. /* Defines for SPL */
  59. #define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
  60. #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
  61. #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
  62. #ifdef CONFIG_SPL_BUILD
  63. #define CONFIG_SYS_MALLOC_SIMPLE
  64. #endif
  65. #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
  66. #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
  67. #if defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_SPI)
  68. /* SPL related SPI defines */
  69. #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
  70. #endif
  71. /* DS414 bus width is 32bits */
  72. #define CONFIG_DDR_32BIT
  73. /* Default Environment */
  74. #define CONFIG_BOOTCOMMAND "sf read ${loadaddr} 0xd0000 0x700000; bootm"
  75. #define CONFIG_LOADADDR 0x80000
  76. #endif /* _CONFIG_SYNOLOGY_DS414_H */