colibri_pxa270.h 4.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Toradex Colibri PXA270 configuration file
  4. *
  5. * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
  6. * Copyright (C) 2015-2016 Marcel Ziswiler <marcel@ziswiler.com>
  7. */
  8. #ifndef __CONFIG_H
  9. #define __CONFIG_H
  10. /*
  11. * High Level Board Configuration Options
  12. */
  13. #define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */
  14. /* Avoid overwriting factory configuration block */
  15. #define CONFIG_BOARD_SIZE_LIMIT 0x40000
  16. /*
  17. * Environment settings
  18. */
  19. #define CONFIG_SYS_MALLOC_LEN (128 * 1024)
  20. #define CONFIG_BOOTCOMMAND \
  21. "if fatload mmc 0 0xa0000000 uImage; then " \
  22. "bootm 0xa0000000; " \
  23. "fi; " \
  24. "if usb reset && fatload usb 0 0xa0000000 uImage; then " \
  25. "bootm 0xa0000000; " \
  26. "fi; " \
  27. "bootm 0xc0000;"
  28. #define CONFIG_TIMESTAMP
  29. #define CONFIG_CMDLINE_TAG
  30. #define CONFIG_SETUP_MEMORY_TAGS
  31. /*
  32. * Serial Console Configuration
  33. */
  34. /*
  35. * Bootloader Components Configuration
  36. */
  37. /* I2C support */
  38. #ifdef CONFIG_SYS_I2C
  39. #define CONFIG_SYS_I2C_PXA
  40. #define CONFIG_PXA_STD_I2C
  41. #define CONFIG_PXA_PWR_I2C
  42. #define CONFIG_SYS_I2C_SPEED 100000
  43. #endif
  44. /* LCD support */
  45. #ifdef CONFIG_LCD
  46. #define CONFIG_PXA_LCD
  47. #define CONFIG_PXA_VGA
  48. #define CONFIG_LCD_LOGO
  49. #endif
  50. /*
  51. * Networking Configuration
  52. */
  53. #ifdef CONFIG_CMD_NET
  54. #define CONFIG_DRIVER_DM9000 1
  55. #define CONFIG_DM9000_BASE 0x08000000
  56. #define DM9000_IO (CONFIG_DM9000_BASE)
  57. #define DM9000_DATA (CONFIG_DM9000_BASE + 4)
  58. #define CONFIG_NET_RETRY_COUNT 10
  59. #define CONFIG_BOOTP_BOOTFILESIZE
  60. #endif
  61. /*
  62. * Clock Configuration
  63. */
  64. #define CONFIG_SYS_CPUSPEED 0x290 /* 520MHz */
  65. /*
  66. * DRAM Map
  67. */
  68. #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
  69. #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
  70. #define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
  71. #define CONFIG_SYS_DRAM_SIZE 0x04000000 /* 64 MB DRAM */
  72. #define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1
  73. #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
  74. #define CONFIG_SYS_INIT_SP_ADDR 0x5c010000
  75. /*
  76. * NOR FLASH
  77. */
  78. #ifdef CONFIG_CMD_FLASH
  79. #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
  80. #define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
  81. #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
  82. #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
  83. #define CONFIG_SYS_MAX_FLASH_SECT (4 + 255)
  84. #define CONFIG_SYS_MAX_FLASH_BANKS 1
  85. #define CONFIG_SYS_FLASH_ERASE_TOUT (25 * CONFIG_SYS_HZ)
  86. #define CONFIG_SYS_FLASH_WRITE_TOUT (25 * CONFIG_SYS_HZ)
  87. #define CONFIG_SYS_FLASH_LOCK_TOUT (25 * CONFIG_SYS_HZ)
  88. #define CONFIG_SYS_FLASH_UNLOCK_TOUT (25 * CONFIG_SYS_HZ)
  89. #endif
  90. #define CONFIG_SYS_MONITOR_BASE 0x0
  91. #define CONFIG_SYS_MONITOR_LEN 0x40000
  92. /* Skip factory configuration block */
  93. /*
  94. * GPIO settings
  95. */
  96. #define CONFIG_SYS_GPSR0_VAL 0x00000000
  97. #define CONFIG_SYS_GPSR1_VAL 0x00020000
  98. #define CONFIG_SYS_GPSR2_VAL 0x0002c000
  99. #define CONFIG_SYS_GPSR3_VAL 0x00000000
  100. #define CONFIG_SYS_GPCR0_VAL 0x00000000
  101. #define CONFIG_SYS_GPCR1_VAL 0x00000000
  102. #define CONFIG_SYS_GPCR2_VAL 0x00000000
  103. #define CONFIG_SYS_GPCR3_VAL 0x00000000
  104. #define CONFIG_SYS_GPDR0_VAL 0xc8008000
  105. #define CONFIG_SYS_GPDR1_VAL 0xfc02a981
  106. #define CONFIG_SYS_GPDR2_VAL 0x92c3ffff
  107. #define CONFIG_SYS_GPDR3_VAL 0x0061e804
  108. #define CONFIG_SYS_GAFR0_L_VAL 0x80100000
  109. #define CONFIG_SYS_GAFR0_U_VAL 0xa5c00010
  110. #define CONFIG_SYS_GAFR1_L_VAL 0x6992901a
  111. #define CONFIG_SYS_GAFR1_U_VAL 0xaaa50008
  112. #define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa
  113. #define CONFIG_SYS_GAFR2_U_VAL 0x4109a002
  114. #define CONFIG_SYS_GAFR3_L_VAL 0x54000310
  115. #define CONFIG_SYS_GAFR3_U_VAL 0x00005401
  116. #define CONFIG_SYS_PSSR_VAL 0x30
  117. /*
  118. * Clock settings
  119. */
  120. #define CONFIG_SYS_CKEN 0x00500240
  121. #define CONFIG_SYS_CCCR 0x02000290
  122. /*
  123. * Memory settings
  124. */
  125. #define CONFIG_SYS_MSC0_VAL 0x9ee1c5f2
  126. #define CONFIG_SYS_MSC1_VAL 0x9ee1f994
  127. #define CONFIG_SYS_MSC2_VAL 0x9ee19ee1
  128. #define CONFIG_SYS_MDCNFG_VAL 0x090009c9
  129. #define CONFIG_SYS_MDREFR_VAL 0x2003a031
  130. #define CONFIG_SYS_MDMRS_VAL 0x00220022
  131. #define CONFIG_SYS_FLYCNFG_VAL 0x00010001
  132. #define CONFIG_SYS_SXCNFG_VAL 0x40044004
  133. /*
  134. * PCMCIA and CF Interfaces
  135. */
  136. #define CONFIG_SYS_MECR_VAL 0x00000000
  137. #define CONFIG_SYS_MCMEM0_VAL 0x00028307
  138. #define CONFIG_SYS_MCMEM1_VAL 0x00014307
  139. #define CONFIG_SYS_MCATT0_VAL 0x00038787
  140. #define CONFIG_SYS_MCATT1_VAL 0x0001c787
  141. #define CONFIG_SYS_MCIO0_VAL 0x0002830f
  142. #define CONFIG_SYS_MCIO1_VAL 0x0001430f
  143. #include "pxa-common.h"
  144. #endif /* __CONFIG_H */