at91sam9x5ek.h 3.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2012 Atmel Corporation
  4. *
  5. * Configuation settings for the AT91SAM9X5EK board.
  6. */
  7. #ifndef __CONFIG_H__
  8. #define __CONFIG_H__
  9. /* ARM asynchronous clock */
  10. #define CONFIG_SYS_AT91_SLOW_CLOCK 32768
  11. #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
  12. #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
  13. #define CONFIG_SETUP_MEMORY_TAGS
  14. #define CONFIG_INITRD_TAG
  15. #define CONFIG_SKIP_LOWLEVEL_INIT
  16. /* general purpose I/O */
  17. #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
  18. /*
  19. * BOOTP options
  20. */
  21. #define CONFIG_BOOTP_BOOTFILESIZE
  22. /*
  23. * define CONFIG_USB_EHCI_HCD to enable USB Hi-Speed (aka 2.0)
  24. * NB: in this case, USB 1.1 devices won't be recognized.
  25. */
  26. /* SDRAM */
  27. #define CONFIG_SYS_SDRAM_BASE 0x20000000
  28. #define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */
  29. #define CONFIG_SYS_INIT_SP_ADDR \
  30. (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
  31. /* DataFlash */
  32. /* NAND flash */
  33. #ifdef CONFIG_CMD_NAND
  34. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  35. #define CONFIG_SYS_NAND_BASE 0x40000000
  36. #define CONFIG_SYS_NAND_DBW_8 1
  37. /* our ALE is AD21 */
  38. #define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
  39. /* our CLE is AD22 */
  40. #define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
  41. #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4
  42. #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5
  43. #endif
  44. /* USB */
  45. #ifdef CONFIG_CMD_USB
  46. #ifndef CONFIG_USB_EHCI_HCD
  47. #define CONFIG_USB_ATMEL
  48. #define CONFIG_USB_ATMEL_CLK_SEL_UPLL
  49. #define CONFIG_USB_OHCI_NEW
  50. #define CONFIG_SYS_USB_OHCI_CPU_INIT
  51. #define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI
  52. #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9x5"
  53. #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3
  54. #endif
  55. #endif
  56. #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
  57. #ifdef CONFIG_NAND_BOOT
  58. /* bootstrap + u-boot + env + linux in nandflash */
  59. #define CONFIG_BOOTCOMMAND "nand read " \
  60. "0x22000000 0x200000 0x600000; " \
  61. "nand read 0x21000000 0x180000 0x20000; " \
  62. "bootz 0x22000000 - 0x21000000"
  63. #elif defined(CONFIG_SPI_BOOT)
  64. /* bootstrap + u-boot + env + linux in spi flash */
  65. #define CONFIG_BOOTCOMMAND "sf probe 0; " \
  66. "sf read 0x22000000 0x100000 0x300000; " \
  67. "bootm 0x22000000"
  68. #elif defined(CONFIG_SYS_USE_DATAFLASH)
  69. /* bootstrap + u-boot + env + linux in data flash */
  70. #define CONFIG_BOOTCOMMAND "sf probe 0; " \
  71. "sf read 0x22000000 0x84000 0x294000; " \
  72. "bootm 0x22000000"
  73. #endif
  74. /*
  75. * Size of malloc() pool
  76. */
  77. #define CONFIG_SYS_MALLOC_LEN (512 * 1024 + 0x1000)
  78. /* SPL */
  79. #define CONFIG_SPL_MAX_SIZE 0x6000
  80. #define CONFIG_SPL_STACK 0x308000
  81. #define CONFIG_SPL_BSS_START_ADDR 0x20000000
  82. #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
  83. #define CONFIG_SYS_SPL_MALLOC_START 0x20080000
  84. #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
  85. #define CONFIG_SYS_MONITOR_LEN (512 << 10)
  86. #define CONFIG_SYS_MASTER_CLOCK 132096000
  87. #define CONFIG_SYS_AT91_PLLA 0x20c73f03
  88. #define CONFIG_SYS_MCKR 0x1301
  89. #define CONFIG_SYS_MCKR_CSS 0x1302
  90. #ifdef CONFIG_SD_BOOT
  91. #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
  92. #endif
  93. #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
  94. #define CONFIG_SYS_NAND_5_ADDR_CYCLE
  95. #define CONFIG_SYS_NAND_PAGE_SIZE 0x800
  96. #define CONFIG_SYS_NAND_PAGE_COUNT 64
  97. #define CONFIG_SYS_NAND_OOBSIZE 64
  98. #define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
  99. #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
  100. #endif