adp-ae3xx.h 5.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2011 Andes Technology Corporation
  4. * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
  5. * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
  6. */
  7. #ifndef __CONFIG_H
  8. #define __CONFIG_H
  9. #include <asm/arch-ae3xx/ae3xx.h>
  10. /*
  11. * CPU and Board Configuration Options
  12. */
  13. #define CONFIG_USE_INTERRUPT
  14. #define CONFIG_SKIP_LOWLEVEL_INIT
  15. #define CONFIG_SKIP_TRUNOFF_WATCHDOG
  16. #define CONFIG_ARCH_MAP_SYSMEM
  17. #define CONFIG_BOOTP_SERVERIP
  18. #ifdef CONFIG_SKIP_LOWLEVEL_INIT
  19. #ifdef CONFIG_OF_CONTROL
  20. #undef CONFIG_OF_SEPARATE
  21. #define CONFIG_OF_EMBED
  22. #endif
  23. #endif
  24. /*
  25. * Timer
  26. */
  27. #define CONFIG_SYS_CLK_FREQ 39062500
  28. #define VERSION_CLOCK CONFIG_SYS_CLK_FREQ
  29. /*
  30. * Use Externel CLOCK or PCLK
  31. */
  32. #undef CONFIG_FTRTC010_EXTCLK
  33. #ifndef CONFIG_FTRTC010_EXTCLK
  34. #define CONFIG_FTRTC010_PCLK
  35. #endif
  36. #ifdef CONFIG_FTRTC010_EXTCLK
  37. #define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */
  38. #else
  39. #define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */
  40. #endif
  41. #define TIMER_LOAD_VAL 0xffffffff
  42. /*
  43. * Real Time Clock
  44. */
  45. #define CONFIG_RTC_FTRTC010
  46. /*
  47. * Real Time Clock Divider
  48. * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ)
  49. */
  50. #define OSC_5MHZ (5*1000000)
  51. #define OSC_CLK (4*OSC_5MHZ)
  52. #define RTC_DIV_COUNT (0.5) /* Why?? */
  53. /*
  54. * Serial console configuration
  55. */
  56. /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
  57. #define CONFIG_SYS_NS16550_SERIAL
  58. #define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE
  59. #ifndef CONFIG_DM_SERIAL
  60. #define CONFIG_SYS_NS16550_REG_SIZE -4
  61. #endif
  62. #define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */
  63. /*
  64. * Miscellaneous configurable options
  65. */
  66. /*
  67. * Size of malloc() pool
  68. */
  69. /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
  70. #define CONFIG_SYS_MALLOC_LEN (512 << 10)
  71. /*
  72. * Physical Memory Map
  73. */
  74. #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
  75. #define PHYS_SDRAM_1 \
  76. (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */
  77. #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */
  78. #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */
  79. #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0
  80. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
  81. GENERATED_GBL_DATA_SIZE)
  82. /*
  83. * Load address and memory test area should agree with
  84. * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself.
  85. */
  86. #define CONFIG_SYS_LOAD_ADDR 0x300000
  87. /* memtest works on 63 MB in DRAM */
  88. /*
  89. * Static memory controller configuration
  90. */
  91. #define CONFIG_FTSMC020
  92. #ifdef CONFIG_FTSMC020
  93. #include <faraday/ftsmc020.h>
  94. #define CONFIG_SYS_FTSMC020_CONFIGS { \
  95. { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \
  96. { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \
  97. }
  98. #ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */
  99. #define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \
  100. FTSMC020_BANK_SIZE_32M | \
  101. FTSMC020_BANK_MBW_32)
  102. #define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \
  103. FTSMC020_TPR_AST(1) | \
  104. FTSMC020_TPR_CTW(1) | \
  105. FTSMC020_TPR_ATI(1) | \
  106. FTSMC020_TPR_AT2(1) | \
  107. FTSMC020_TPR_WTC(1) | \
  108. FTSMC020_TPR_AHT(1) | \
  109. FTSMC020_TPR_TRNA(1))
  110. #endif
  111. /*
  112. * FLASH on ADP_AG101P is connected to BANK0
  113. * Just disalbe the other BANK to avoid detection error.
  114. */
  115. #define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \
  116. FTSMC020_BANK_BASE(PHYS_FLASH_1) | \
  117. FTSMC020_BANK_SIZE_32M | \
  118. FTSMC020_BANK_MBW_32)
  119. #define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \
  120. FTSMC020_TPR_CTW(3) | \
  121. FTSMC020_TPR_ATI(0xf) | \
  122. FTSMC020_TPR_AT2(3) | \
  123. FTSMC020_TPR_WTC(3) | \
  124. FTSMC020_TPR_AHT(3) | \
  125. FTSMC020_TPR_TRNA(0xf))
  126. #define FTSMC020_BANK1_CONFIG (0x00)
  127. #define FTSMC020_BANK1_TIMING (0x00)
  128. #endif /* CONFIG_FTSMC020 */
  129. /*
  130. * FLASH and environment organization
  131. */
  132. /* use CFI framework */
  133. #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
  134. #define CONFIG_SYS_CFI_FLASH_STATUS_POLL
  135. /* support JEDEC */
  136. #ifdef CONFIG_CFI_FLASH
  137. #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
  138. #endif
  139. /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
  140. #define PHYS_FLASH_1 0x88000000 /* BANK 0 */
  141. #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
  142. #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, }
  143. #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
  144. #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */
  145. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */
  146. /* max number of memory banks */
  147. /*
  148. * There are 4 banks supported for this Controller,
  149. * but we have only 1 bank connected to flash on board
  150. */
  151. #ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT
  152. #define CONFIG_SYS_MAX_FLASH_BANKS 1
  153. #endif
  154. #define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
  155. /* max number of sectors on one chip */
  156. #define CONFIG_FLASH_SECTOR_SIZE (0x10000*2)
  157. #define CONFIG_SYS_MAX_FLASH_SECT 512
  158. /* environments */
  159. /* SPI FLASH */
  160. /*
  161. * For booting Linux, the board info and command line data
  162. * have to be in the first 16 MB of memory, since this is
  163. * the maximum mapped by the Linux kernel during initialization.
  164. */
  165. /* Initial Memory map for Linux*/
  166. #define CONFIG_SYS_BOOTMAPSZ (64 << 20)
  167. /* Increase max gunzip size */
  168. #define CONFIG_SYS_BOOTM_LEN (64 << 20)
  169. #endif /* __CONFIG_H */