T104xRDB.h 25 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2014 Freescale Semiconductor, Inc.
  4. * Copyright 2020 NXP
  5. */
  6. #ifndef __CONFIG_H
  7. #define __CONFIG_H
  8. #include <linux/stringify.h>
  9. /*
  10. * T104x RDB board configuration file
  11. */
  12. #include <asm/config_mpc85xx.h>
  13. #ifdef CONFIG_RAMBOOT_PBL
  14. #ifndef CONFIG_NXP_ESBC
  15. #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg
  16. #else
  17. #define CONFIG_SYS_FSL_PBL_PBI \
  18. $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg
  19. #endif
  20. #define CONFIG_SPL_FLUSH_IMAGE
  21. #define CONFIG_SPL_PAD_TO 0x40000
  22. #define CONFIG_SPL_MAX_SIZE 0x28000
  23. #ifdef CONFIG_SPL_BUILD
  24. #define CONFIG_SPL_SKIP_RELOCATE
  25. #define CONFIG_SPL_COMMON_INIT_DDR
  26. #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  27. #undef CONFIG_DM_I2C
  28. #endif
  29. #define RESET_VECTOR_OFFSET 0x27FFC
  30. #define BOOT_PAGE_OFFSET 0x27000
  31. #ifdef CONFIG_MTD_RAW_NAND
  32. #ifdef CONFIG_NXP_ESBC
  33. #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
  34. /*
  35. * HDR would be appended at end of image and copied to DDR along
  36. * with U-Boot image.
  37. */
  38. #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \
  39. CONFIG_U_BOOT_HDR_SIZE)
  40. #else
  41. #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
  42. #endif
  43. #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
  44. #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
  45. #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
  46. #ifdef CONFIG_TARGET_T1040RDB
  47. #define CONFIG_SYS_FSL_PBL_RCW \
  48. $(SRCTREE)/board/freescale/t104xrdb/t1040_nand_rcw.cfg
  49. #endif
  50. #ifdef CONFIG_TARGET_T1042RDB_PI
  51. #define CONFIG_SYS_FSL_PBL_RCW \
  52. $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg
  53. #endif
  54. #ifdef CONFIG_TARGET_T1042RDB
  55. #define CONFIG_SYS_FSL_PBL_RCW \
  56. $(SRCTREE)/board/freescale/t104xrdb/t1042_nand_rcw.cfg
  57. #endif
  58. #ifdef CONFIG_TARGET_T1040D4RDB
  59. #define CONFIG_SYS_FSL_PBL_RCW \
  60. $(SRCTREE)/board/freescale/t104xrdb/t1040d4_nand_rcw.cfg
  61. #endif
  62. #ifdef CONFIG_TARGET_T1042D4RDB
  63. #define CONFIG_SYS_FSL_PBL_RCW \
  64. $(SRCTREE)/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg
  65. #endif
  66. #endif
  67. #ifdef CONFIG_SPIFLASH
  68. #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
  69. #define CONFIG_SPL_SPI_FLASH_MINIMAL
  70. #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
  71. #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
  72. #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
  73. #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
  74. #ifndef CONFIG_SPL_BUILD
  75. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  76. #endif
  77. #ifdef CONFIG_TARGET_T1040RDB
  78. #define CONFIG_SYS_FSL_PBL_RCW \
  79. $(SRCTREE)/board/freescale/t104xrdb/t1040_spi_rcw.cfg
  80. #endif
  81. #ifdef CONFIG_TARGET_T1042RDB_PI
  82. #define CONFIG_SYS_FSL_PBL_RCW \
  83. $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg
  84. #endif
  85. #ifdef CONFIG_TARGET_T1042RDB
  86. #define CONFIG_SYS_FSL_PBL_RCW \
  87. $(SRCTREE)/board/freescale/t104xrdb/t1042_spi_rcw.cfg
  88. #endif
  89. #ifdef CONFIG_TARGET_T1040D4RDB
  90. #define CONFIG_SYS_FSL_PBL_RCW \
  91. $(SRCTREE)/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg
  92. #endif
  93. #ifdef CONFIG_TARGET_T1042D4RDB
  94. #define CONFIG_SYS_FSL_PBL_RCW \
  95. $(SRCTREE)/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg
  96. #endif
  97. #endif
  98. #ifdef CONFIG_SDCARD
  99. #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
  100. #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
  101. #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
  102. #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
  103. #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
  104. #ifndef CONFIG_SPL_BUILD
  105. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  106. #endif
  107. #ifdef CONFIG_TARGET_T1040RDB
  108. #define CONFIG_SYS_FSL_PBL_RCW \
  109. $(SRCTREE)/board/freescale/t104xrdb/t1040_sd_rcw.cfg
  110. #endif
  111. #ifdef CONFIG_TARGET_T1042RDB_PI
  112. #define CONFIG_SYS_FSL_PBL_RCW \
  113. $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg
  114. #endif
  115. #ifdef CONFIG_TARGET_T1042RDB
  116. #define CONFIG_SYS_FSL_PBL_RCW \
  117. $(SRCTREE)/board/freescale/t104xrdb/t1042_sd_rcw.cfg
  118. #endif
  119. #ifdef CONFIG_TARGET_T1040D4RDB
  120. #define CONFIG_SYS_FSL_PBL_RCW \
  121. $(SRCTREE)/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg
  122. #endif
  123. #ifdef CONFIG_TARGET_T1042D4RDB
  124. #define CONFIG_SYS_FSL_PBL_RCW \
  125. $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
  126. #endif
  127. #endif
  128. #endif
  129. /* High Level Configuration Options */
  130. #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
  131. /* support deep sleep */
  132. #define CONFIG_DEEP_SLEEP
  133. #ifndef CONFIG_RESET_VECTOR_ADDRESS
  134. #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
  135. #endif
  136. #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
  137. #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
  138. #define CONFIG_PCIE1 /* PCIE controller 1 */
  139. #define CONFIG_PCIE2 /* PCIE controller 2 */
  140. #define CONFIG_PCIE3 /* PCIE controller 3 */
  141. #define CONFIG_PCIE4 /* PCIE controller 4 */
  142. #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
  143. #if defined(CONFIG_SPIFLASH)
  144. #elif defined(CONFIG_MTD_RAW_NAND)
  145. #ifdef CONFIG_NXP_ESBC
  146. #define CONFIG_RAMBOOT_NAND
  147. #define CONFIG_BOOTSCRIPT_COPY_RAM
  148. #endif
  149. #endif
  150. #define CONFIG_SYS_CLK_FREQ 100000000
  151. #define CONFIG_DDR_CLK_FREQ 66666666
  152. /*
  153. * These can be toggled for performance analysis, otherwise use default.
  154. */
  155. #define CONFIG_SYS_CACHE_STASHING
  156. #define CONFIG_BACKSIDE_L2_CACHE
  157. #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
  158. #define CONFIG_BTB /* toggle branch predition */
  159. #define CONFIG_DDR_ECC
  160. #ifdef CONFIG_DDR_ECC
  161. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  162. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  163. #endif
  164. #define CONFIG_ENABLE_36BIT_PHYS
  165. /*
  166. * Config the L3 Cache as L3 SRAM
  167. */
  168. #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
  169. /*
  170. * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence
  171. * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address
  172. * (CONFIG_SYS_INIT_L3_VADDR) will be different.
  173. */
  174. #define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000
  175. #define CONFIG_SYS_L3_SIZE 256 << 10
  176. #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024)
  177. #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
  178. #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
  179. #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
  180. #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
  181. #define CONFIG_SYS_DCSRBAR 0xf0000000
  182. #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
  183. /*
  184. * DDR Setup
  185. */
  186. #define CONFIG_VERY_BIG_RAM
  187. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  188. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  189. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  190. #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  191. #define CONFIG_DDR_SPD
  192. #define CONFIG_SYS_SPD_BUS_NUM 0
  193. #define SPD_EEPROM_ADDRESS 0x51
  194. #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
  195. /*
  196. * IFC Definitions
  197. */
  198. #define CONFIG_SYS_FLASH_BASE 0xe8000000
  199. #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
  200. #define CONFIG_SYS_NOR_CSPR_EXT (0xf)
  201. #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
  202. CSPR_PORT_SIZE_16 | \
  203. CSPR_MSEL_NOR | \
  204. CSPR_V)
  205. #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
  206. /*
  207. * TDM Definition
  208. */
  209. #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000
  210. /* NOR Flash Timing Params */
  211. #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
  212. #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
  213. FTIM0_NOR_TEADC(0x5) | \
  214. FTIM0_NOR_TEAHC(0x5))
  215. #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
  216. FTIM1_NOR_TRAD_NOR(0x1A) |\
  217. FTIM1_NOR_TSEQRAD_NOR(0x13))
  218. #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
  219. FTIM2_NOR_TCH(0x4) | \
  220. FTIM2_NOR_TWPH(0x0E) | \
  221. FTIM2_NOR_TWP(0x1c))
  222. #define CONFIG_SYS_NOR_FTIM3 0x0
  223. #define CONFIG_SYS_FLASH_QUIET_TEST
  224. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  225. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  226. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  227. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  228. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  229. #define CONFIG_SYS_FLASH_EMPTY_INFO
  230. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
  231. /* CPLD on IFC */
  232. #define CPLD_LBMAP_MASK 0x3F
  233. #define CPLD_BANK_SEL_MASK 0x07
  234. #define CPLD_BANK_OVERRIDE 0x40
  235. #define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */
  236. #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */
  237. #define CPLD_LBMAP_RESET 0xFF
  238. #define CPLD_LBMAP_SHIFT 0x03
  239. #if defined(CONFIG_TARGET_T1042RDB_PI)
  240. #define CPLD_DIU_SEL_DFP 0x80
  241. #elif defined(CONFIG_TARGET_T1042D4RDB)
  242. #define CPLD_DIU_SEL_DFP 0xc0
  243. #endif
  244. #if defined(CONFIG_TARGET_T1040D4RDB)
  245. #define CPLD_INT_MASK_ALL 0xFF
  246. #define CPLD_INT_MASK_THERM 0x80
  247. #define CPLD_INT_MASK_DVI_DFP 0x40
  248. #define CPLD_INT_MASK_QSGMII1 0x20
  249. #define CPLD_INT_MASK_QSGMII2 0x10
  250. #define CPLD_INT_MASK_SGMI1 0x08
  251. #define CPLD_INT_MASK_SGMI2 0x04
  252. #define CPLD_INT_MASK_TDMR1 0x02
  253. #define CPLD_INT_MASK_TDMR2 0x01
  254. #endif
  255. #define CONFIG_SYS_CPLD_BASE 0xffdf0000
  256. #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
  257. #define CONFIG_SYS_CSPR2_EXT (0xf)
  258. #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
  259. | CSPR_PORT_SIZE_8 \
  260. | CSPR_MSEL_GPCM \
  261. | CSPR_V)
  262. #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
  263. #define CONFIG_SYS_CSOR2 0x0
  264. /* CPLD Timing parameters for IFC CS2 */
  265. #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
  266. FTIM0_GPCM_TEADC(0x0e) | \
  267. FTIM0_GPCM_TEAHC(0x0e))
  268. #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
  269. FTIM1_GPCM_TRAD(0x1f))
  270. #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
  271. FTIM2_GPCM_TCH(0x8) | \
  272. FTIM2_GPCM_TWP(0x1f))
  273. #define CONFIG_SYS_CS2_FTIM3 0x0
  274. /* NAND Flash on IFC */
  275. #define CONFIG_NAND_FSL_IFC
  276. #define CONFIG_SYS_NAND_BASE 0xff800000
  277. #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
  278. #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
  279. #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  280. | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
  281. | CSPR_MSEL_NAND /* MSEL = NAND */ \
  282. | CSPR_V)
  283. #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
  284. #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  285. | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  286. | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
  287. | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
  288. | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
  289. | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \
  290. | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
  291. #define CONFIG_SYS_NAND_ONFI_DETECTION
  292. /* ONFI NAND Flash mode0 Timing Params */
  293. #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
  294. FTIM0_NAND_TWP(0x18) | \
  295. FTIM0_NAND_TWCHT(0x07) | \
  296. FTIM0_NAND_TWH(0x0a))
  297. #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
  298. FTIM1_NAND_TWBE(0x39) | \
  299. FTIM1_NAND_TRR(0x0e) | \
  300. FTIM1_NAND_TRP(0x18))
  301. #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
  302. FTIM2_NAND_TREH(0x0a) | \
  303. FTIM2_NAND_TWHRE(0x1e))
  304. #define CONFIG_SYS_NAND_FTIM3 0x0
  305. #define CONFIG_SYS_NAND_DDR_LAW 11
  306. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  307. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  308. #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
  309. #if defined(CONFIG_MTD_RAW_NAND)
  310. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
  311. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
  312. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
  313. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
  314. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
  315. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
  316. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
  317. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
  318. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT
  319. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
  320. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  321. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  322. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  323. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  324. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  325. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  326. #else
  327. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT
  328. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
  329. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  330. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  331. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  332. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  333. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  334. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  335. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
  336. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
  337. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
  338. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
  339. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
  340. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
  341. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
  342. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
  343. #endif
  344. #ifdef CONFIG_SPL_BUILD
  345. #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
  346. #else
  347. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  348. #endif
  349. #if defined(CONFIG_RAMBOOT_PBL)
  350. #define CONFIG_SYS_RAMBOOT
  351. #endif
  352. #ifdef CONFIG_SYS_FSL_ERRATUM_A008044
  353. #if defined(CONFIG_MTD_RAW_NAND)
  354. #define CONFIG_A008044_WORKAROUND
  355. #endif
  356. #endif
  357. #define CONFIG_HWCONFIG
  358. /* define to use L1 as initial stack */
  359. #define CONFIG_L1_INIT_RAM
  360. #define CONFIG_SYS_INIT_RAM_LOCK
  361. #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
  362. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
  363. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
  364. /* The assembler doesn't like typecast */
  365. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
  366. ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
  367. CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
  368. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
  369. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
  370. GENERATED_GBL_DATA_SIZE)
  371. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  372. #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
  373. #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
  374. /* Serial Port - controlled on board with jumper J8
  375. * open - index 2
  376. * shorted - index 1
  377. */
  378. #define CONFIG_SYS_NS16550_SERIAL
  379. #define CONFIG_SYS_NS16550_REG_SIZE 1
  380. #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
  381. #define CONFIG_SYS_BAUDRATE_TABLE \
  382. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  383. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
  384. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
  385. #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
  386. #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
  387. #if defined(CONFIG_TARGET_T1042RDB_PI) || defined(CONFIG_TARGET_T1042D4RDB)
  388. /* Video */
  389. #define CONFIG_FSL_DIU_FB
  390. #ifdef CONFIG_FSL_DIU_FB
  391. #define CONFIG_FSL_DIU_CH7301
  392. #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
  393. #define CONFIG_VIDEO_LOGO
  394. #define CONFIG_VIDEO_BMP_LOGO
  395. #endif
  396. #endif
  397. /* I2C */
  398. #ifndef CONFIG_DM_I2C
  399. #define CONFIG_SYS_I2C
  400. #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */
  401. #define CONFIG_SYS_FSL_I2C2_SPEED 400000
  402. #define CONFIG_SYS_FSL_I2C3_SPEED 400000
  403. #define CONFIG_SYS_FSL_I2C4_SPEED 400000
  404. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  405. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  406. #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
  407. #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
  408. #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
  409. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
  410. #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
  411. #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
  412. #else
  413. #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
  414. #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
  415. #endif
  416. #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
  417. /* I2C bus multiplexer */
  418. #define I2C_MUX_PCA_ADDR 0x70
  419. #define I2C_MUX_CH_DEFAULT 0x8
  420. #if defined(CONFIG_TARGET_T1042RDB_PI) || \
  421. defined(CONFIG_TARGET_T1040D4RDB) || \
  422. defined(CONFIG_TARGET_T1042D4RDB)
  423. /* LDI/DVI Encoder for display */
  424. #define CONFIG_SYS_I2C_LDI_ADDR 0x38
  425. #define CONFIG_SYS_I2C_DVI_ADDR 0x75
  426. #define CONFIG_SYS_I2C_DVI_BUS_NUM 0
  427. /*
  428. * RTC configuration
  429. */
  430. #define RTC
  431. #define CONFIG_RTC_DS1337 1
  432. #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  433. /*DVI encoder*/
  434. #define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75
  435. #endif
  436. /*
  437. * eSPI - Enhanced SPI
  438. */
  439. /*
  440. * General PCI
  441. * Memory space is mapped 1-1, but I/O space must start from 0.
  442. */
  443. #ifdef CONFIG_PCI
  444. /* controller 1, direct to uli, tgtid 3, Base address 20000 */
  445. #ifdef CONFIG_PCIE1
  446. #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
  447. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
  448. #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
  449. #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
  450. #endif
  451. /* controller 2, Slot 2, tgtid 2, Base address 201000 */
  452. #ifdef CONFIG_PCIE2
  453. #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
  454. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
  455. #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
  456. #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
  457. #endif
  458. /* controller 3, Slot 1, tgtid 1, Base address 202000 */
  459. #ifdef CONFIG_PCIE3
  460. #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
  461. #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
  462. #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
  463. #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
  464. #endif
  465. /* controller 4, Base address 203000 */
  466. #ifdef CONFIG_PCIE4
  467. #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
  468. #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
  469. #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
  470. #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
  471. #endif
  472. #if !defined(CONFIG_DM_PCI)
  473. #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
  474. #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
  475. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
  476. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  477. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  478. #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
  479. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
  480. #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
  481. #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
  482. #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
  483. #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
  484. #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
  485. #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
  486. #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
  487. #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
  488. #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
  489. #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
  490. #define CONFIG_PCI_INDIRECT_BRIDGE
  491. #endif
  492. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  493. #endif /* CONFIG_PCI */
  494. /* SATA */
  495. #define CONFIG_FSL_SATA_V2
  496. #ifdef CONFIG_FSL_SATA_V2
  497. #define CONFIG_SYS_SATA_MAX_DEVICE 1
  498. #define CONFIG_SATA1
  499. #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
  500. #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
  501. #define CONFIG_LBA48
  502. #endif
  503. /*
  504. * USB
  505. */
  506. #define CONFIG_HAS_FSL_DR_USB
  507. #ifdef CONFIG_HAS_FSL_DR_USB
  508. #ifdef CONFIG_USB_EHCI_HCD
  509. #define CONFIG_USB_EHCI_FSL
  510. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  511. #endif
  512. #endif
  513. #ifdef CONFIG_MMC
  514. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
  515. #endif
  516. /* Qman/Bman */
  517. #ifndef CONFIG_NOBQFMAN
  518. #define CONFIG_SYS_BMAN_NUM_PORTALS 10
  519. #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
  520. #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
  521. #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
  522. #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
  523. #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
  524. #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
  525. #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  526. #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
  527. CONFIG_SYS_BMAN_CENA_SIZE)
  528. #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  529. #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
  530. #define CONFIG_SYS_QMAN_NUM_PORTALS 10
  531. #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
  532. #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
  533. #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
  534. #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
  535. #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
  536. #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
  537. #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  538. #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
  539. CONFIG_SYS_QMAN_CENA_SIZE)
  540. #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  541. #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
  542. #define CONFIG_SYS_DPAA_FMAN
  543. #define CONFIG_SYS_DPAA_PME
  544. #define CONFIG_U_QE
  545. /* Default address of microcode for the Linux Fman driver */
  546. #if defined(CONFIG_SPIFLASH)
  547. /*
  548. * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
  549. * env, so we got 0x110000.
  550. */
  551. #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
  552. #elif defined(CONFIG_SDCARD)
  553. /*
  554. * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
  555. * about 1MB (2048 blocks), Env is stored after the image, and the env size is
  556. * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
  557. */
  558. #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
  559. #elif defined(CONFIG_MTD_RAW_NAND)
  560. #define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
  561. #else
  562. #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
  563. #endif
  564. #if defined(CONFIG_SPIFLASH)
  565. #define CONFIG_SYS_QE_FW_ADDR 0x130000
  566. #elif defined(CONFIG_SDCARD)
  567. #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
  568. #elif defined(CONFIG_MTD_RAW_NAND)
  569. #define CONFIG_SYS_QE_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
  570. #else
  571. #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000
  572. #endif
  573. #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
  574. #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
  575. #endif /* CONFIG_NOBQFMAN */
  576. #ifdef CONFIG_FMAN_ENET
  577. #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB)
  578. #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03
  579. #elif defined(CONFIG_TARGET_T1040D4RDB)
  580. #define CONFIG_SYS_SGMII1_PHY_ADDR 0x01
  581. #elif defined(CONFIG_TARGET_T1042D4RDB)
  582. #define CONFIG_SYS_SGMII1_PHY_ADDR 0x02
  583. #define CONFIG_SYS_SGMII2_PHY_ADDR 0x03
  584. #define CONFIG_SYS_SGMII3_PHY_ADDR 0x01
  585. #endif
  586. #if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
  587. #define CONFIG_SYS_RGMII1_PHY_ADDR 0x04
  588. #define CONFIG_SYS_RGMII2_PHY_ADDR 0x05
  589. #else
  590. #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01
  591. #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02
  592. #endif
  593. /* Enable VSC9953 L2 Switch driver on T1040 SoC */
  594. #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB)
  595. #define CONFIG_VSC9953
  596. #ifdef CONFIG_TARGET_T1040RDB
  597. #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04
  598. #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08
  599. #else
  600. #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08
  601. #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c
  602. #endif
  603. #endif
  604. #define CONFIG_ETHPRIME "FM1@DTSEC4"
  605. #endif
  606. /*
  607. * Environment
  608. */
  609. #define CONFIG_LOADS_ECHO /* echo on for serial download */
  610. #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
  611. /*
  612. * Miscellaneous configurable options
  613. */
  614. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  615. /*
  616. * For booting Linux, the board info and command line data
  617. * have to be in the first 64 MB of memory, since this is
  618. * the maximum mapped by the Linux kernel during initialization.
  619. */
  620. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
  621. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  622. #ifdef CONFIG_CMD_KGDB
  623. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  624. #endif
  625. /*
  626. * Dynamic MTD Partition support with mtdparts
  627. */
  628. /*
  629. * Environment Configuration
  630. */
  631. #define CONFIG_ROOTPATH "/opt/nfsroot"
  632. #define CONFIG_BOOTFILE "uImage"
  633. #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
  634. /* default location for tftp and bootm */
  635. #define CONFIG_LOADADDR 1000000
  636. #define __USB_PHY_TYPE utmi
  637. #define RAMDISKFILE "t104xrdb/ramdisk.uboot"
  638. #ifdef CONFIG_TARGET_T1040RDB
  639. #define FDTFILE "t1040rdb/t1040rdb.dtb"
  640. #elif defined(CONFIG_TARGET_T1042RDB_PI)
  641. #define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb"
  642. #elif defined(CONFIG_TARGET_T1042RDB)
  643. #define FDTFILE "t1042rdb/t1042rdb.dtb"
  644. #elif defined(CONFIG_TARGET_T1040D4RDB)
  645. #define FDTFILE "t1042rdb/t1040d4rdb.dtb"
  646. #elif defined(CONFIG_TARGET_T1042D4RDB)
  647. #define FDTFILE "t1042rdb/t1042d4rdb.dtb"
  648. #endif
  649. #ifdef CONFIG_FSL_DIU_FB
  650. #define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi"
  651. #else
  652. #define DIU_ENVIRONMENT
  653. #endif
  654. #define CONFIG_EXTRA_ENV_SETTINGS \
  655. "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \
  656. "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
  657. "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
  658. "netdev=eth0\0" \
  659. "video-mode=" __stringify(DIU_ENVIRONMENT) "\0" \
  660. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  661. "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
  662. "tftpflash=tftpboot $loadaddr $uboot && " \
  663. "protect off $ubootaddr +$filesize && " \
  664. "erase $ubootaddr +$filesize && " \
  665. "cp.b $loadaddr $ubootaddr $filesize && " \
  666. "protect on $ubootaddr +$filesize && " \
  667. "cmp.b $loadaddr $ubootaddr $filesize\0" \
  668. "consoledev=ttyS0\0" \
  669. "ramdiskaddr=2000000\0" \
  670. "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \
  671. "fdtaddr=1e00000\0" \
  672. "fdtfile=" __stringify(FDTFILE) "\0" \
  673. "bdev=sda3\0"
  674. #define CONFIG_LINUX \
  675. "setenv bootargs root=/dev/ram rw " \
  676. "console=$consoledev,$baudrate $othbootargs;" \
  677. "setenv ramdiskaddr 0x02000000;" \
  678. "setenv fdtaddr 0x00c00000;" \
  679. "setenv loadaddr 0x1000000;" \
  680. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  681. #define CONFIG_HDBOOT \
  682. "setenv bootargs root=/dev/$bdev rw " \
  683. "console=$consoledev,$baudrate $othbootargs;" \
  684. "tftp $loadaddr $bootfile;" \
  685. "tftp $fdtaddr $fdtfile;" \
  686. "bootm $loadaddr - $fdtaddr"
  687. #define CONFIG_NFSBOOTCOMMAND \
  688. "setenv bootargs root=/dev/nfs rw " \
  689. "nfsroot=$serverip:$rootpath " \
  690. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  691. "console=$consoledev,$baudrate $othbootargs;" \
  692. "tftp $loadaddr $bootfile;" \
  693. "tftp $fdtaddr $fdtfile;" \
  694. "bootm $loadaddr - $fdtaddr"
  695. #define CONFIG_RAMBOOTCOMMAND \
  696. "setenv bootargs root=/dev/ram rw " \
  697. "console=$consoledev,$baudrate $othbootargs;" \
  698. "tftp $ramdiskaddr $ramdiskfile;" \
  699. "tftp $loadaddr $bootfile;" \
  700. "tftp $fdtaddr $fdtfile;" \
  701. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  702. #define CONFIG_BOOTCOMMAND CONFIG_LINUX
  703. #include <asm/fsl_secure_boot.h>
  704. #endif /* __CONFIG_H */