MPC8641HPCN.h 21 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2006, 2010-2011 Freescale Semiconductor.
  4. *
  5. * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
  6. */
  7. /*
  8. * MPC8641HPCN board configuration file
  9. *
  10. * Make sure you change the MAC address and other network params first,
  11. * search for CONFIG_SERVERIP, etc. in this file.
  12. */
  13. #ifndef __CONFIG_H
  14. #define __CONFIG_H
  15. #include <linux/stringify.h>
  16. /* High Level Configuration Options */
  17. #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
  18. /*
  19. * default CCSRBAR is at 0xff700000
  20. * assume U-Boot is less than 0.5MB
  21. */
  22. #ifdef RUN_DIAG
  23. #define CONFIG_SYS_DIAG_ADDR CONFIG_SYS_FLASH_BASE
  24. #endif
  25. /*
  26. * virtual address to be used for temporary mappings. There
  27. * should be 128k free at this VA.
  28. */
  29. #define CONFIG_SYS_SCRATCH_VA 0xe0000000
  30. #define CONFIG_SYS_SRIO
  31. #define CONFIG_SRIO1 /* SRIO port 1 */
  32. #define CONFIG_PCIE1 1 /* PCIE controller 1 (ULI bridge) */
  33. #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot) */
  34. #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
  35. #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
  36. #define CONFIG_BAT_RW 1 /* Use common BAT rw code */
  37. #define CONFIG_ALTIVEC 1
  38. /*
  39. * L2CR setup -- make sure this is right for your board!
  40. */
  41. #define CONFIG_SYS_L2
  42. #define L2_INIT 0
  43. #define L2_ENABLE (L2CR_L2E)
  44. #ifndef CONFIG_SYS_CLK_FREQ
  45. #ifndef __ASSEMBLY__
  46. extern unsigned long get_board_sys_clk(unsigned long dummy);
  47. #endif
  48. #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
  49. #endif
  50. /*
  51. * With the exception of PCI Memory and Rapid IO, most devices will simply
  52. * add CONFIG_SYS_PHYS_ADDR_HIGH to the front of the 32-bit VA to get the PA
  53. * when 36-bit is enabled. When 36-bit is not enabled, these bits are 0.
  54. */
  55. #ifdef CONFIG_PHYS_64BIT
  56. #define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f
  57. #else
  58. #define CONFIG_SYS_PHYS_ADDR_HIGH 0x00000000
  59. #endif
  60. /*
  61. * Base addresses -- Note these are effective addresses where the
  62. * actual resources get mapped (not physical addresses)
  63. */
  64. #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
  65. #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
  66. /* Physical addresses */
  67. #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
  68. #define CONFIG_SYS_CCSRBAR_PHYS_HIGH CONFIG_SYS_PHYS_ADDR_HIGH
  69. #define CONFIG_SYS_CCSRBAR_PHYS \
  70. PAIRED_PHYS_TO_PHYS(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
  71. CONFIG_SYS_CCSRBAR_PHYS_HIGH)
  72. #define CONFIG_HWCONFIG /* use hwconfig to control memory interleaving */
  73. /*
  74. * DDR Setup
  75. */
  76. #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
  77. #define CONFIG_DDR_SPD
  78. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
  79. #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
  80. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
  81. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  82. #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
  83. #define CONFIG_VERY_BIG_RAM
  84. #define CONFIG_DIMM_SLOTS_PER_CTLR 2
  85. #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  86. /*
  87. * I2C addresses of SPD EEPROMs
  88. */
  89. #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
  90. #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 0 DIMM 1 */
  91. #define SPD_EEPROM_ADDRESS3 0x53 /* CTLR 1 DIMM 0 */
  92. #define SPD_EEPROM_ADDRESS4 0x54 /* CTLR 1 DIMM 1 */
  93. /*
  94. * These are used when DDR doesn't use SPD.
  95. */
  96. #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
  97. #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
  98. #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */
  99. #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  100. #define CONFIG_SYS_DDR_TIMING_0 0x00260802
  101. #define CONFIG_SYS_DDR_TIMING_1 0x39357322
  102. #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
  103. #define CONFIG_SYS_DDR_MODE_1 0x00480432
  104. #define CONFIG_SYS_DDR_MODE_2 0x00000000
  105. #define CONFIG_SYS_DDR_INTERVAL 0x06090100
  106. #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
  107. #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
  108. #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
  109. #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
  110. #define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */
  111. #define CONFIG_SYS_DDR_CONTROL2 0x04400000
  112. #define CONFIG_ID_EEPROM
  113. #define CONFIG_SYS_I2C_EEPROM_NXID
  114. #define CONFIG_ID_EEPROM
  115. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  116. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  117. #define CONFIG_SYS_FLASH_BASE 0xef800000 /* start of FLASH 8M */
  118. #define CONFIG_SYS_FLASH_BASE_PHYS_LOW CONFIG_SYS_FLASH_BASE
  119. #define CONFIG_SYS_FLASH_BASE_PHYS \
  120. PAIRED_PHYS_TO_PHYS(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
  121. CONFIG_SYS_PHYS_ADDR_HIGH)
  122. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
  123. #define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
  124. | 0x00001001) /* port size 16bit */
  125. #define CONFIG_SYS_OR0_PRELIM 0xff806ff7 /* 8MB Boot Flash area*/
  126. #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CF_BASE_PHYS) \
  127. | 0x00001001) /* port size 16bit */
  128. #define CONFIG_SYS_OR2_PRELIM 0xffffeff7 /* 32k Compact Flash */
  129. #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) \
  130. | 0x00000801) /* port size 8bit */
  131. #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32k PIXIS area*/
  132. /*
  133. * The LBC_BASE is the base of the region that contains the PIXIS and the CF.
  134. * The PIXIS and CF by themselves aren't large enough to take up the 128k
  135. * required for the smallest BAT mapping, so there's a 64k hole.
  136. */
  137. #define CONFIG_SYS_LBC_BASE 0xffde0000
  138. #define CONFIG_SYS_LBC_BASE_PHYS_LOW CONFIG_SYS_LBC_BASE
  139. #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
  140. #define PIXIS_BASE (CONFIG_SYS_LBC_BASE + 0x00010000)
  141. #define PIXIS_BASE_PHYS_LOW (CONFIG_SYS_LBC_BASE_PHYS_LOW + 0x00010000)
  142. #define PIXIS_BASE_PHYS PAIRED_PHYS_TO_PHYS(PIXIS_BASE_PHYS_LOW, \
  143. CONFIG_SYS_PHYS_ADDR_HIGH)
  144. #define PIXIS_SIZE 0x00008000 /* 32k */
  145. #define PIXIS_ID 0x0 /* Board ID at offset 0 */
  146. #define PIXIS_VER 0x1 /* Board version at offset 1 */
  147. #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
  148. #define PIXIS_RST 0x4 /* PIXIS Reset Control register */
  149. #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */
  150. #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
  151. #define PIXIS_VCTL 0x10 /* VELA Control Register */
  152. #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
  153. #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
  154. #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
  155. #define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */
  156. #define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */
  157. #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
  158. #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
  159. #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
  160. #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
  161. #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/
  162. /* Compact flash shares a BAT with PIXIS; make sure they're contiguous */
  163. #define CF_BASE (PIXIS_BASE + PIXIS_SIZE)
  164. #define CF_BASE_PHYS (PIXIS_BASE_PHYS + PIXIS_SIZE)
  165. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  166. #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
  167. #undef CONFIG_SYS_FLASH_CHECKSUM
  168. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  169. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  170. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  171. #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
  172. #define CONFIG_SYS_FLASH_EMPTY_INFO
  173. #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  174. #define CONFIG_SYS_RAMBOOT
  175. #else
  176. #undef CONFIG_SYS_RAMBOOT
  177. #endif
  178. #if defined(CONFIG_SYS_RAMBOOT)
  179. #undef CONFIG_SPD_EEPROM
  180. #define CONFIG_SYS_SDRAM_SIZE 256
  181. #endif
  182. #define CONFIG_SYS_INIT_RAM_LOCK 1
  183. #ifndef CONFIG_SYS_INIT_RAM_LOCK
  184. #define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */
  185. #else
  186. #define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */
  187. #endif
  188. #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
  189. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  190. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  191. #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
  192. #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
  193. /* Serial Port */
  194. #define CONFIG_SYS_NS16550_SERIAL
  195. #define CONFIG_SYS_NS16550_REG_SIZE 1
  196. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  197. #define CONFIG_SYS_BAUDRATE_TABLE \
  198. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
  199. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
  200. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
  201. /*
  202. * I2C
  203. */
  204. #define CONFIG_SYS_I2C
  205. #define CONFIG_SYS_I2C_FSL
  206. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  207. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  208. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3100
  209. #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
  210. /*
  211. * RapidIO MMU
  212. */
  213. #define CONFIG_SYS_SRIO1_MEM_BASE 0x80000000 /* base address */
  214. #ifdef CONFIG_PHYS_64BIT
  215. #define CONFIG_SYS_SRIO1_MEM_PHYS_LOW 0x00000000
  216. #define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH 0x0000000c
  217. #else
  218. #define CONFIG_SYS_SRIO1_MEM_PHYS_LOW CONFIG_SYS_SRIO1_MEM_BASE
  219. #define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH 0x00000000
  220. #endif
  221. #define CONFIG_SYS_SRIO1_MEM_PHYS \
  222. PAIRED_PHYS_TO_PHYS(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
  223. CONFIG_SYS_SRIO1_MEM_PHYS_HIGH)
  224. #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 128M */
  225. /*
  226. * General PCI
  227. * Addresses are mapped 1-1.
  228. */
  229. #define CONFIG_SYS_PCIE1_NAME "ULI"
  230. #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
  231. #ifdef CONFIG_PHYS_64BIT
  232. #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
  233. #define CONFIG_SYS_PCIE1_MEM_PHYS_LOW 0x00000000
  234. #define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x0000000c
  235. #else
  236. #define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT
  237. #define CONFIG_SYS_PCIE1_MEM_PHYS_LOW CONFIG_SYS_PCIE1_MEM_VIRT
  238. #define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x00000000
  239. #endif
  240. #define CONFIG_SYS_PCIE1_MEM_PHYS \
  241. PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
  242. CONFIG_SYS_PCIE1_MEM_PHYS_HIGH)
  243. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
  244. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  245. #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
  246. #define CONFIG_SYS_PCIE1_IO_PHYS_LOW CONFIG_SYS_PCIE1_IO_VIRT
  247. #define CONFIG_SYS_PCIE1_IO_PHYS \
  248. PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
  249. CONFIG_SYS_PHYS_ADDR_HIGH)
  250. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64K */
  251. #ifdef CONFIG_PHYS_64BIT
  252. /*
  253. * Use the same PCI bus address on PCIE1 and PCIE2 if we have PHYS_64BIT.
  254. * This will increase the amount of PCI address space available for
  255. * for mapping RAM.
  256. */
  257. #define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE1_MEM_BUS
  258. #else
  259. #define CONFIG_SYS_PCIE2_MEM_BUS (CONFIG_SYS_PCIE1_MEM_BUS \
  260. + CONFIG_SYS_PCIE1_MEM_SIZE)
  261. #endif
  262. #define CONFIG_SYS_PCIE2_MEM_VIRT (CONFIG_SYS_PCIE1_MEM_VIRT \
  263. + CONFIG_SYS_PCIE1_MEM_SIZE)
  264. #define CONFIG_SYS_PCIE2_MEM_PHYS_LOW (CONFIG_SYS_PCIE1_MEM_PHYS_LOW \
  265. + CONFIG_SYS_PCIE1_MEM_SIZE)
  266. #define CONFIG_SYS_PCIE2_MEM_PHYS_HIGH CONFIG_SYS_PCIE1_MEM_PHYS_HIGH
  267. #define CONFIG_SYS_PCIE2_MEM_PHYS (CONFIG_SYS_PCIE1_MEM_PHYS \
  268. + CONFIG_SYS_PCIE1_MEM_SIZE)
  269. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
  270. #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
  271. #define CONFIG_SYS_PCIE2_IO_VIRT (CONFIG_SYS_PCIE1_IO_VIRT \
  272. + CONFIG_SYS_PCIE1_IO_SIZE)
  273. #define CONFIG_SYS_PCIE2_IO_PHYS_LOW (CONFIG_SYS_PCIE1_IO_PHYS_LOW \
  274. + CONFIG_SYS_PCIE1_IO_SIZE)
  275. #define CONFIG_SYS_PCIE2_IO_PHYS (CONFIG_SYS_PCIE1_IO_PHYS \
  276. + CONFIG_SYS_PCIE1_IO_SIZE)
  277. #define CONFIG_SYS_PCIE2_IO_SIZE CONFIG_SYS_PCIE1_IO_SIZE
  278. #if defined(CONFIG_PCI)
  279. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  280. /************************************************************
  281. * USB support
  282. ************************************************************/
  283. #define CONFIG_PCI_OHCI 1
  284. #define CONFIG_USB_OHCI_NEW 1
  285. #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci"
  286. #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
  287. #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
  288. /*PCIE video card used*/
  289. #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT
  290. /*PCI video card used*/
  291. /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT*/
  292. /* video */
  293. #if defined(CONFIG_VIDEO)
  294. #define CONFIG_BIOSEMU
  295. #define CONFIG_ATI_RADEON_FB
  296. #define CONFIG_VIDEO_LOGO
  297. #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE2_IO_VIRT
  298. #endif
  299. #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  300. #ifdef CONFIG_SCSI_AHCI
  301. #define CONFIG_SATA_ULI5288
  302. #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
  303. #define CONFIG_SYS_SCSI_MAX_LUN 1
  304. #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
  305. #endif
  306. #endif /* CONFIG_PCI */
  307. #if defined(CONFIG_TSEC_ENET)
  308. #define CONFIG_TSEC1 1
  309. #define CONFIG_TSEC1_NAME "eTSEC1"
  310. #define CONFIG_TSEC2 1
  311. #define CONFIG_TSEC2_NAME "eTSEC2"
  312. #define CONFIG_TSEC3 1
  313. #define CONFIG_TSEC3_NAME "eTSEC3"
  314. #define CONFIG_TSEC4 1
  315. #define CONFIG_TSEC4_NAME "eTSEC4"
  316. #define TSEC1_PHY_ADDR 0
  317. #define TSEC2_PHY_ADDR 1
  318. #define TSEC3_PHY_ADDR 2
  319. #define TSEC4_PHY_ADDR 3
  320. #define TSEC1_PHYIDX 0
  321. #define TSEC2_PHYIDX 0
  322. #define TSEC3_PHYIDX 0
  323. #define TSEC4_PHYIDX 0
  324. #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  325. #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  326. #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  327. #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  328. #define CONFIG_ETHPRIME "eTSEC1"
  329. #endif /* CONFIG_TSEC_ENET */
  330. #ifdef CONFIG_PHYS_64BIT
  331. #define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8)
  332. #define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2)
  333. /* Put physical address into the BAT format */
  334. #define BAT_PHYS_ADDR(low, high) \
  335. (low | PHYS_HIGH_TO_BXPN(high) | PHYS_HIGH_TO_BX(high))
  336. /* Convert high/low pairs to actual 64-bit value */
  337. #define PAIRED_PHYS_TO_PHYS(low, high) (low | ((u64)high << 32))
  338. #else
  339. /* 32-bit systems just ignore the "high" bits */
  340. #define BAT_PHYS_ADDR(low, high) (low)
  341. #define PAIRED_PHYS_TO_PHYS(low, high) (low)
  342. #endif
  343. /*
  344. * BAT0 DDR
  345. */
  346. #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
  347. #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
  348. /*
  349. * BAT1 LBC (PIXIS/CF)
  350. */
  351. #define CONFIG_SYS_DBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \
  352. CONFIG_SYS_PHYS_ADDR_HIGH) \
  353. | BATL_PP_RW | BATL_CACHEINHIBIT | \
  354. BATL_GUARDEDSTORAGE)
  355. #define CONFIG_SYS_DBAT1U (CONFIG_SYS_LBC_BASE | BATU_BL_128K \
  356. | BATU_VS | BATU_VP)
  357. #define CONFIG_SYS_IBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \
  358. CONFIG_SYS_PHYS_ADDR_HIGH) \
  359. | BATL_PP_RW | BATL_MEMCOHERENCE)
  360. #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
  361. /* if CONFIG_PCI:
  362. * BAT2 PCIE1 and PCIE1 MEM
  363. * if CONFIG_RIO
  364. * BAT2 Rapidio Memory
  365. */
  366. #ifdef CONFIG_PCI
  367. #define CONFIG_PCI_INDIRECT_BRIDGE
  368. #define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
  369. CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \
  370. | BATL_PP_RW | BATL_CACHEINHIBIT \
  371. | BATL_GUARDEDSTORAGE)
  372. #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_1G \
  373. | BATU_VS | BATU_VP)
  374. #define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
  375. CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \
  376. | BATL_PP_RW | BATL_CACHEINHIBIT)
  377. #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
  378. #else /* CONFIG_RIO */
  379. #define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
  380. CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \
  381. | BATL_PP_RW | BATL_CACHEINHIBIT | \
  382. BATL_GUARDEDSTORAGE)
  383. #define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M \
  384. | BATU_VS | BATU_VP)
  385. #define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
  386. CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \
  387. | BATL_PP_RW | BATL_CACHEINHIBIT)
  388. #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
  389. #endif
  390. /*
  391. * BAT3 CCSR Space
  392. */
  393. #define CONFIG_SYS_DBAT3L (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
  394. CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
  395. | BATL_PP_RW | BATL_CACHEINHIBIT \
  396. | BATL_GUARDEDSTORAGE)
  397. #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \
  398. | BATU_VP)
  399. #define CONFIG_SYS_IBAT3L (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
  400. CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
  401. | BATL_PP_RW | BATL_CACHEINHIBIT)
  402. #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
  403. #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
  404. #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
  405. | BATL_PP_RW | BATL_CACHEINHIBIT \
  406. | BATL_GUARDEDSTORAGE)
  407. #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
  408. | BATU_BL_1M | BATU_VS | BATU_VP)
  409. #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
  410. | BATL_PP_RW | BATL_CACHEINHIBIT)
  411. #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
  412. #endif
  413. /*
  414. * BAT4 PCIE1_IO and PCIE2_IO
  415. */
  416. #define CONFIG_SYS_DBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
  417. CONFIG_SYS_PHYS_ADDR_HIGH) \
  418. | BATL_PP_RW | BATL_CACHEINHIBIT \
  419. | BATL_GUARDEDSTORAGE)
  420. #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_128K \
  421. | BATU_VS | BATU_VP)
  422. #define CONFIG_SYS_IBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
  423. CONFIG_SYS_PHYS_ADDR_HIGH) \
  424. | BATL_PP_RW | BATL_CACHEINHIBIT)
  425. #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
  426. /*
  427. * BAT5 Init RAM for stack in the CPU DCache (no backing memory)
  428. */
  429. #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
  430. #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
  431. #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
  432. #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
  433. /*
  434. * BAT6 FLASH
  435. */
  436. #define CONFIG_SYS_DBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
  437. CONFIG_SYS_PHYS_ADDR_HIGH) \
  438. | BATL_PP_RW | BATL_CACHEINHIBIT \
  439. | BATL_GUARDEDSTORAGE)
  440. #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \
  441. | BATU_VP)
  442. #define CONFIG_SYS_IBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
  443. CONFIG_SYS_PHYS_ADDR_HIGH) \
  444. | BATL_PP_RW | BATL_MEMCOHERENCE)
  445. #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
  446. /* Map the last 1M of flash where we're running from reset */
  447. #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
  448. | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
  449. #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
  450. #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
  451. | BATL_MEMCOHERENCE)
  452. #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
  453. /*
  454. * BAT7 FREE - used later for tmp mappings
  455. */
  456. #define CONFIG_SYS_DBAT7L 0x00000000
  457. #define CONFIG_SYS_DBAT7U 0x00000000
  458. #define CONFIG_SYS_IBAT7L 0x00000000
  459. #define CONFIG_SYS_IBAT7U 0x00000000
  460. /*
  461. * Environment
  462. */
  463. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  464. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  465. /*
  466. * BOOTP options
  467. */
  468. #define CONFIG_BOOTP_BOOTFILESIZE
  469. #undef CONFIG_WATCHDOG /* watchdog disabled */
  470. /*
  471. * Miscellaneous configurable options
  472. */
  473. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  474. /*
  475. * For booting Linux, the board info and command line data
  476. * have to be in the first 8 MB of memory, since this is
  477. * the maximum mapped by the Linux kernel during initialization.
  478. */
  479. #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/
  480. #define CONFIG_SYS_BOOTM_LEN (256 << 20) /* Increase max gunzip size */
  481. #if defined(CONFIG_CMD_KGDB)
  482. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  483. #endif
  484. /*
  485. * Environment Configuration
  486. */
  487. #define CONFIG_HAS_ETH0 1
  488. #define CONFIG_HAS_ETH1 1
  489. #define CONFIG_HAS_ETH2 1
  490. #define CONFIG_HAS_ETH3 1
  491. #define CONFIG_IPADDR 192.168.1.100
  492. #define CONFIG_HOSTNAME "unknown"
  493. #define CONFIG_ROOTPATH "/opt/nfsroot"
  494. #define CONFIG_BOOTFILE "uImage"
  495. #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
  496. #define CONFIG_SERVERIP 192.168.1.1
  497. #define CONFIG_GATEWAYIP 192.168.1.1
  498. #define CONFIG_NETMASK 255.255.255.0
  499. /* default location for tftp and bootm */
  500. #define CONFIG_LOADADDR 0x10000000
  501. #define CONFIG_EXTRA_ENV_SETTINGS \
  502. "netdev=eth0\0" \
  503. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  504. "tftpflash=tftpboot $loadaddr $uboot; " \
  505. "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
  506. " +$filesize; " \
  507. "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
  508. " +$filesize; " \
  509. "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
  510. " $filesize; " \
  511. "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
  512. " +$filesize; " \
  513. "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
  514. " $filesize\0" \
  515. "consoledev=ttyS0\0" \
  516. "ramdiskaddr=0x18000000\0" \
  517. "ramdiskfile=your.ramdisk.u-boot\0" \
  518. "fdtaddr=0x17c00000\0" \
  519. "fdtfile=mpc8641_hpcn.dtb\0" \
  520. "en-wd=mw.b ffdf0010 0x08; echo -expect:- 08; md.b ffdf0010 1\0" \
  521. "dis-wd=mw.b ffdf0010 0x00; echo -expect:- 00; md.b ffdf0010 1\0" \
  522. "maxcpus=2"
  523. #define CONFIG_NFSBOOTCOMMAND \
  524. "setenv bootargs root=/dev/nfs rw " \
  525. "nfsroot=$serverip:$rootpath " \
  526. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  527. "console=$consoledev,$baudrate $othbootargs;" \
  528. "tftp $loadaddr $bootfile;" \
  529. "tftp $fdtaddr $fdtfile;" \
  530. "bootm $loadaddr - $fdtaddr"
  531. #define CONFIG_RAMBOOTCOMMAND \
  532. "setenv bootargs root=/dev/ram rw " \
  533. "console=$consoledev,$baudrate $othbootargs;" \
  534. "tftp $ramdiskaddr $ramdiskfile;" \
  535. "tftp $loadaddr $bootfile;" \
  536. "tftp $fdtaddr $fdtfile;" \
  537. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  538. #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
  539. #endif /* __CONFIG_H */