MPC832XEMDS.h 8.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2006 Freescale Semiconductor, Inc.
  4. */
  5. #ifndef __CONFIG_H
  6. #define __CONFIG_H
  7. /*
  8. * High Level Configuration Options
  9. */
  10. #define CONFIG_E300 1 /* E300 family */
  11. /*
  12. * System IO Config
  13. */
  14. #define CONFIG_SYS_SICRL 0x00000000
  15. /*
  16. * DDR Setup
  17. */
  18. #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
  19. #define CONFIG_SYS_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */
  20. #undef CONFIG_SPD_EEPROM
  21. #if defined(CONFIG_SPD_EEPROM)
  22. /* Determine DDR configuration from I2C interface
  23. */
  24. #define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */
  25. #else
  26. /* Manually set up DDR parameters
  27. */
  28. #define CONFIG_SYS_DDR_SIZE 128 /* MB */
  29. #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
  30. | CSCONFIG_AP \
  31. | CSCONFIG_ODT_WR_CFG \
  32. | CSCONFIG_ROW_BIT_13 \
  33. | CSCONFIG_COL_BIT_10)
  34. /* 0x80840102 */
  35. #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  36. | (0 << TIMING_CFG0_WRT_SHIFT) \
  37. | (0 << TIMING_CFG0_RRT_SHIFT) \
  38. | (0 << TIMING_CFG0_WWT_SHIFT) \
  39. | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  40. | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  41. | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  42. | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  43. /* 0x00220802 */
  44. #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
  45. | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
  46. | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
  47. | (5 << TIMING_CFG1_CASLAT_SHIFT) \
  48. | (13 << TIMING_CFG1_REFREC_SHIFT) \
  49. | (3 << TIMING_CFG1_WRREC_SHIFT) \
  50. | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
  51. | (2 << TIMING_CFG1_WRTORD_SHIFT))
  52. /* 0x3935D322 */
  53. #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
  54. | (31 << TIMING_CFG2_CPO_SHIFT) \
  55. | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
  56. | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
  57. | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
  58. | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
  59. | (10 << TIMING_CFG2_FOUR_ACT_SHIFT))
  60. /* 0x0F9048CA */
  61. #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  62. #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
  63. /* 0x02000000 */
  64. #define CONFIG_SYS_DDR_MODE ((0x4440 << SDRAM_MODE_ESD_SHIFT) \
  65. | (0x0232 << SDRAM_MODE_SD_SHIFT))
  66. /* 0x44400232 */
  67. #define CONFIG_SYS_DDR_MODE2 0x8000c000
  68. #define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
  69. | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
  70. /* 0x03200064 */
  71. #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
  72. #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
  73. | SDRAM_CFG_SDRAM_TYPE_DDR2 \
  74. | SDRAM_CFG_32_BE)
  75. /* 0x43080000 */
  76. #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
  77. #endif
  78. /*
  79. * Memory test
  80. */
  81. #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
  82. /*
  83. * The reserved memory
  84. */
  85. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  86. #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  87. #define CONFIG_SYS_RAMBOOT
  88. #else
  89. #undef CONFIG_SYS_RAMBOOT
  90. #endif
  91. /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
  92. #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
  93. #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
  94. /*
  95. * Initial RAM Base Address Setup
  96. */
  97. #define CONFIG_SYS_INIT_RAM_LOCK 1
  98. #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM addr */
  99. #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
  100. #define CONFIG_SYS_GBL_DATA_OFFSET \
  101. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  102. /*
  103. * FLASH on the Local Bus
  104. */
  105. #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
  106. #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */
  107. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  108. #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
  109. #undef CONFIG_SYS_FLASH_CHECKSUM
  110. /*
  111. * BCSR on the Local Bus
  112. */
  113. #define CONFIG_SYS_BCSR 0xF8000000
  114. /* Access window base at BCSR base */
  115. /*
  116. * Windows to access PIB via local bus
  117. */
  118. /* PIB window base 0xF8008000 */
  119. #define CONFIG_SYS_PIB_BASE 0xF8008000
  120. #define CONFIG_SYS_PIB_WINDOW_SIZE (32 * 1024)
  121. /*
  122. * CS2 on Local Bus, to PIB
  123. */
  124. /*
  125. * CS3 on Local Bus, to PIB
  126. */
  127. /*
  128. * Serial Port
  129. */
  130. #define CONFIG_SYS_NS16550_SERIAL
  131. #define CONFIG_SYS_NS16550_REG_SIZE 1
  132. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  133. #define CONFIG_SYS_BAUDRATE_TABLE \
  134. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
  135. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
  136. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
  137. /* I2C */
  138. #define CONFIG_SYS_I2C
  139. #define CONFIG_SYS_I2C_FSL
  140. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  141. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  142. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  143. #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
  144. /*
  145. * Config on-board RTC
  146. */
  147. #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
  148. #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
  149. /*
  150. * General PCI
  151. * Addresses are mapped 1-1.
  152. */
  153. #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
  154. #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
  155. #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
  156. #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
  157. #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
  158. #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
  159. #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
  160. #define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000
  161. #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
  162. #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
  163. #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
  164. #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
  165. #ifdef CONFIG_PCI
  166. #define CONFIG_PCI_INDIRECT_BRIDGE
  167. #define CONFIG_83XX_PCI_STREAMING
  168. #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  169. #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
  170. #endif /* CONFIG_PCI */
  171. /*
  172. * QE UEC ethernet configuration
  173. */
  174. #define CONFIG_UEC_ETH
  175. #define CONFIG_ETHPRIME "UEC0"
  176. #define CONFIG_UEC_ETH1 /* ETH3 */
  177. #ifdef CONFIG_UEC_ETH1
  178. #define CONFIG_SYS_UEC1_UCC_NUM 2 /* UCC3 */
  179. #define CONFIG_SYS_UEC1_RX_CLK QE_CLK9
  180. #define CONFIG_SYS_UEC1_TX_CLK QE_CLK10
  181. #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
  182. #define CONFIG_SYS_UEC1_PHY_ADDR 3
  183. #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
  184. #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
  185. #endif
  186. #define CONFIG_UEC_ETH2 /* ETH4 */
  187. #ifdef CONFIG_UEC_ETH2
  188. #define CONFIG_SYS_UEC2_UCC_NUM 3 /* UCC4 */
  189. #define CONFIG_SYS_UEC2_RX_CLK QE_CLK7
  190. #define CONFIG_SYS_UEC2_TX_CLK QE_CLK8
  191. #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
  192. #define CONFIG_SYS_UEC2_PHY_ADDR 4
  193. #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
  194. #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
  195. #endif
  196. /*
  197. * Environment
  198. */
  199. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  200. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  201. /*
  202. * BOOTP options
  203. */
  204. #define CONFIG_BOOTP_BOOTFILESIZE
  205. #undef CONFIG_WATCHDOG /* watchdog disabled */
  206. /*
  207. * Miscellaneous configurable options
  208. */
  209. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  210. /*
  211. * For booting Linux, the board info and command line data
  212. * have to be in the first 256 MB of memory, since this is
  213. * the maximum mapped by the Linux kernel during initialization.
  214. */
  215. /* Initial Memory map for Linux */
  216. #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
  217. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  218. #if defined(CONFIG_CMD_KGDB)
  219. #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
  220. #endif
  221. #if defined(CONFIG_UEC_ETH)
  222. #define CONFIG_HAS_ETH0
  223. #define CONFIG_HAS_ETH1
  224. #endif
  225. #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
  226. #define CONFIG_EXTRA_ENV_SETTINGS \
  227. "netdev=eth0\0" \
  228. "consoledev=ttyS0\0" \
  229. "ramdiskaddr=1000000\0" \
  230. "ramdiskfile=ramfs.83xx\0" \
  231. "fdtaddr=780000\0" \
  232. "fdtfile=mpc832x_mds.dtb\0" \
  233. ""
  234. #define CONFIG_NFSBOOTCOMMAND \
  235. "setenv bootargs root=/dev/nfs rw " \
  236. "nfsroot=$serverip:$rootpath " \
  237. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
  238. "$netdev:off " \
  239. "console=$consoledev,$baudrate $othbootargs;" \
  240. "tftp $loadaddr $bootfile;" \
  241. "tftp $fdtaddr $fdtfile;" \
  242. "bootm $loadaddr - $fdtaddr"
  243. #define CONFIG_RAMBOOTCOMMAND \
  244. "setenv bootargs root=/dev/ram rw " \
  245. "console=$consoledev,$baudrate $othbootargs;" \
  246. "tftp $ramdiskaddr $ramdiskfile;" \
  247. "tftp $loadaddr $bootfile;" \
  248. "tftp $fdtaddr $fdtfile;" \
  249. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  250. #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
  251. #endif /* __CONFIG_H */