MPC8323ERDB.h 9.0 KB

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  1. /*
  2. * Copyright (C) 2007 Freescale Semiconductor, Inc.
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms of the GNU General Public License version 2 as published
  6. * by the Free Software Foundation.
  7. */
  8. #ifndef __CONFIG_H
  9. #define __CONFIG_H
  10. #include <linux/stringify.h>
  11. /*
  12. * High Level Configuration Options
  13. */
  14. #define CONFIG_E300 1 /* E300 family */
  15. /*
  16. * System IO Config
  17. */
  18. #define CONFIG_SYS_SICRL 0x00000000
  19. /*
  20. * DDR Setup
  21. */
  22. #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
  23. #undef CONFIG_SPD_EEPROM
  24. #if defined(CONFIG_SPD_EEPROM)
  25. /* Determine DDR configuration from I2C interface
  26. */
  27. #define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */
  28. #else
  29. /* Manually set up DDR parameters
  30. */
  31. #define CONFIG_SYS_DDR_SIZE 64 /* MB */
  32. #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
  33. | CSCONFIG_ROW_BIT_13 \
  34. | CSCONFIG_COL_BIT_9)
  35. /* 0x80010101 */
  36. #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  37. | (0 << TIMING_CFG0_WRT_SHIFT) \
  38. | (0 << TIMING_CFG0_RRT_SHIFT) \
  39. | (0 << TIMING_CFG0_WWT_SHIFT) \
  40. | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  41. | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  42. | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  43. | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  44. /* 0x00220802 */
  45. #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
  46. | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
  47. | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
  48. | (5 << TIMING_CFG1_CASLAT_SHIFT) \
  49. | (3 << TIMING_CFG1_REFREC_SHIFT) \
  50. | (2 << TIMING_CFG1_WRREC_SHIFT) \
  51. | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
  52. | (2 << TIMING_CFG1_WRTORD_SHIFT))
  53. /* 0x26253222 */
  54. #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
  55. | (31 << TIMING_CFG2_CPO_SHIFT) \
  56. | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
  57. | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
  58. | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
  59. | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
  60. | (7 << TIMING_CFG2_FOUR_ACT_SHIFT))
  61. /* 0x1f9048c7 */
  62. #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  63. #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
  64. /* 0x02000000 */
  65. #define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
  66. | (0x0232 << SDRAM_MODE_SD_SHIFT))
  67. /* 0x44480232 */
  68. #define CONFIG_SYS_DDR_MODE2 0x8000c000
  69. #define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
  70. | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
  71. /* 0x03200064 */
  72. #define CONFIG_SYS_DDR_CS0_BNDS 0x00000003
  73. #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
  74. | SDRAM_CFG_SDRAM_TYPE_DDR2 \
  75. | SDRAM_CFG_32_BE)
  76. /* 0x43080000 */
  77. #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
  78. #endif
  79. /*
  80. * Memory test
  81. */
  82. #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
  83. /*
  84. * The reserved memory
  85. */
  86. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  87. #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  88. #define CONFIG_SYS_RAMBOOT
  89. #else
  90. #undef CONFIG_SYS_RAMBOOT
  91. #endif
  92. /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
  93. #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
  94. #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
  95. /*
  96. * Initial RAM Base Address Setup
  97. */
  98. #define CONFIG_SYS_INIT_RAM_LOCK 1
  99. #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
  100. #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
  101. #define CONFIG_SYS_GBL_DATA_OFFSET \
  102. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  103. /*
  104. * FLASH on the Local Bus
  105. */
  106. #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
  107. #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */
  108. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  109. #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
  110. #undef CONFIG_SYS_FLASH_CHECKSUM
  111. /*
  112. * Serial Port
  113. */
  114. #define CONFIG_SYS_NS16550_SERIAL
  115. #define CONFIG_SYS_NS16550_REG_SIZE 1
  116. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  117. #define CONFIG_SYS_BAUDRATE_TABLE \
  118. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
  119. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
  120. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
  121. /* I2C */
  122. #define CONFIG_SYS_I2C
  123. #define CONFIG_SYS_I2C_FSL
  124. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  125. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  126. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  127. #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
  128. /*
  129. * Config on-board EEPROM
  130. */
  131. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
  132. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
  133. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
  134. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
  135. /*
  136. * General PCI
  137. * Addresses are mapped 1-1.
  138. */
  139. #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
  140. #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
  141. #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
  142. #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
  143. #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
  144. #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
  145. #define CONFIG_SYS_PCI1_IO_BASE 0xd0000000
  146. #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
  147. #define CONFIG_SYS_PCI1_IO_SIZE 0x04000000 /* 64M */
  148. #ifdef CONFIG_PCI
  149. #define CONFIG_PCI_INDIRECT_BRIDGE
  150. #define CONFIG_PCI_SKIP_HOST_BRIDGE
  151. #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  152. #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
  153. #endif /* CONFIG_PCI */
  154. /*
  155. * QE UEC ethernet configuration
  156. */
  157. #define CONFIG_UEC_ETH
  158. #define CONFIG_ETHPRIME "UEC0"
  159. #define CONFIG_UEC_ETH1 /* ETH3 */
  160. #ifdef CONFIG_UEC_ETH1
  161. #define CONFIG_SYS_UEC1_UCC_NUM 2 /* UCC3 */
  162. #define CONFIG_SYS_UEC1_RX_CLK QE_CLK9
  163. #define CONFIG_SYS_UEC1_TX_CLK QE_CLK10
  164. #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
  165. #define CONFIG_SYS_UEC1_PHY_ADDR 4
  166. #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
  167. #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
  168. #endif
  169. #define CONFIG_UEC_ETH2 /* ETH4 */
  170. #ifdef CONFIG_UEC_ETH2
  171. #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */
  172. #define CONFIG_SYS_UEC2_RX_CLK QE_CLK16
  173. #define CONFIG_SYS_UEC2_TX_CLK QE_CLK3
  174. #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
  175. #define CONFIG_SYS_UEC2_PHY_ADDR 0
  176. #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
  177. #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
  178. #endif
  179. /*
  180. * Environment
  181. */
  182. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  183. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  184. /*
  185. * BOOTP options
  186. */
  187. #define CONFIG_BOOTP_BOOTFILESIZE
  188. #undef CONFIG_WATCHDOG /* watchdog disabled */
  189. /*
  190. * Miscellaneous configurable options
  191. */
  192. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  193. /*
  194. * For booting Linux, the board info and command line data
  195. * have to be in the first 256 MB of memory, since this is
  196. * the maximum mapped by the Linux kernel during initialization.
  197. */
  198. /* Initial Memory map for Linux */
  199. #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
  200. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  201. #if (CONFIG_CMD_KGDB)
  202. #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
  203. #endif
  204. /*
  205. * Environment Configuration
  206. */
  207. #define CONFIG_HAS_ETH0 /* add support for "ethaddr" */
  208. #define CONFIG_HAS_ETH1 /* add support for "eth1addr" */
  209. /* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM
  210. * (see CONFIG_SYS_I2C_EEPROM) */
  211. /* MAC address offset in I2C EEPROM */
  212. #define CONFIG_SYS_I2C_MAC_OFFSET 0x7f00
  213. #define CONFIG_NETDEV "eth1"
  214. #define CONFIG_HOSTNAME "mpc8323erdb"
  215. #define CONFIG_ROOTPATH "/nfsroot"
  216. #define CONFIG_BOOTFILE "uImage"
  217. /* U-Boot image on TFTP server */
  218. #define CONFIG_UBOOTPATH "u-boot.bin"
  219. #define CONFIG_FDTFILE "mpc832x_rdb.dtb"
  220. #define CONFIG_RAMDISKFILE "rootfs.ext2.gz.uboot"
  221. /* default location for tftp and bootm */
  222. #define CONFIG_LOADADDR 800000
  223. #define CONFIG_EXTRA_ENV_SETTINGS \
  224. "netdev=" CONFIG_NETDEV "\0" \
  225. "uboot=" CONFIG_UBOOTPATH "\0" \
  226. "tftpflash=tftp $loadaddr $uboot;" \
  227. "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
  228. " +$filesize; " \
  229. "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
  230. " +$filesize; " \
  231. "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
  232. " $filesize; " \
  233. "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
  234. " +$filesize; " \
  235. "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
  236. " $filesize\0" \
  237. "fdtaddr=780000\0" \
  238. "fdtfile=" CONFIG_FDTFILE "\0" \
  239. "ramdiskaddr=1000000\0" \
  240. "ramdiskfile=" CONFIG_RAMDISKFILE "\0" \
  241. "console=ttyS0\0" \
  242. "setbootargs=setenv bootargs " \
  243. "root=$rootdev rw console=$console,$baudrate $othbootargs\0"\
  244. "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
  245. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
  246. "$netdev:off "\
  247. "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
  248. #define CONFIG_NFSBOOTCOMMAND \
  249. "setenv rootdev /dev/nfs;" \
  250. "run setbootargs;" \
  251. "run setipargs;" \
  252. "tftp $loadaddr $bootfile;" \
  253. "tftp $fdtaddr $fdtfile;" \
  254. "bootm $loadaddr - $fdtaddr"
  255. #define CONFIG_RAMBOOTCOMMAND \
  256. "setenv rootdev /dev/ram;" \
  257. "run setbootargs;" \
  258. "tftp $ramdiskaddr $ramdiskfile;" \
  259. "tftp $loadaddr $bootfile;" \
  260. "tftp $fdtaddr $fdtfile;" \
  261. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  262. #endif /* __CONFIG_H */