andes_pcu.h 13 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2011 Andes Technology Corp
  4. * Macpaul Lin <macpaul@andestech.com>
  5. */
  6. /*
  7. * Andes Power Control Unit
  8. */
  9. #ifndef __ANDES_PCU_H
  10. #define __ANDES_PCU_H
  11. #ifndef __ASSEMBLY__
  12. struct pcs {
  13. unsigned int cr; /* PCSx Configuration (clock scaling) */
  14. unsigned int parm; /* PCSx Parameter*/
  15. unsigned int stat1; /* PCSx Status 1 */
  16. unsigned int stat2; /* PCSx Stusts 2 */
  17. unsigned int pdd; /* PCSx PDD */
  18. };
  19. struct andes_pcu {
  20. unsigned int rev; /* 0x00 - PCU Revision */
  21. unsigned int spinfo; /* 0x04 - Scratch Pad Info */
  22. unsigned int rsvd1[2]; /* 0x08-0x0C: Reserved */
  23. unsigned int soc_id; /* 0x10 - SoC ID */
  24. unsigned int soc_ahb; /* 0x14 - SoC AHB configuration */
  25. unsigned int soc_apb; /* 0x18 - SoC APB configuration */
  26. unsigned int rsvd2; /* 0x1C */
  27. unsigned int dcsrcr0; /* 0x20 - Driving Capability
  28. and Slew Rate Control 0 */
  29. unsigned int dcsrcr1; /* 0x24 - Driving Capability
  30. and Slew Rate Control 1 */
  31. unsigned int dcsrcr2; /* 0x28 - Driving Capability
  32. and Slew Rate Control 2 */
  33. unsigned int rsvd3; /* 0x2C */
  34. unsigned int mfpsr0; /* 0x30 - Multi-Func Port Setting 0 */
  35. unsigned int mfpsr1; /* 0x34 - Multi-Func Port Setting 1 */
  36. unsigned int dmaes; /* 0x38 - DMA Engine Selection */
  37. unsigned int rsvd4; /* 0x3C */
  38. unsigned int oscc; /* 0x40 - OSC Control */
  39. unsigned int pwmcd; /* 0x44 - PWM Clock divider */
  40. unsigned int socmisc; /* 0x48 - SoC Misc. */
  41. unsigned int rsvd5[13]; /* 0x4C-0x7C: Reserved */
  42. unsigned int bsmcr; /* 0x80 - BSM Controrl */
  43. unsigned int bsmst; /* 0x84 - BSM Status */
  44. unsigned int wes; /* 0x88 - Wakeup Event Sensitivity*/
  45. unsigned int west; /* 0x8C - Wakeup Event Status */
  46. unsigned int rsttiming; /* 0x90 - Reset Timing */
  47. unsigned int intr_st; /* 0x94 - PCU Interrupt Status */
  48. unsigned int rsvd6[2]; /* 0x98-0x9C: Reserved */
  49. struct pcs pcs1; /* 0xA0-0xB0: PCS1 (clock scaling) */
  50. unsigned int pcsrsvd1[3]; /* 0xB4-0xBC: Reserved */
  51. struct pcs pcs2; /* 0xC0-0xD0: PCS2 (AHB clock gating) */
  52. unsigned int pcsrsvd2[3]; /* 0xD4-0xDC: Reserved */
  53. struct pcs pcs3; /* 0xE0-0xF0: PCS3 (APB clock gating) */
  54. unsigned int pcsrsvd3[3]; /* 0xF4-0xFC: Reserved */
  55. struct pcs pcs4; /* 0x100-0x110: PCS4 main PLL scaling */
  56. unsigned int pcsrsvd4[3]; /* 0x114-0x11C: Reserved */
  57. struct pcs pcs5; /* 0x120-0x130: PCS5 PCI PLL scaling */
  58. unsigned int pcsrsvd5[3]; /* 0x134-0x13C: Reserved */
  59. struct pcs pcs6; /* 0x140-0x150: PCS6 AC97 PLL scaling */
  60. unsigned int pcsrsvd6[3]; /* 0x154-0x15C: Reserved */
  61. struct pcs pcs7; /* 0x160-0x170: PCS7 GMAC PLL scaling */
  62. unsigned int pcsrsvd7[3]; /* 0x174-0x17C: Reserved */
  63. struct pcs pcs8; /* 0x180-0x190: PCS8 voltage scaling */
  64. unsigned int pcsrsvd8[3]; /* 0x194-0x19C: Reserved */
  65. struct pcs pcs9; /* 0x1A0-0x1B0: PCS9 power control */
  66. unsigned int pcsrsvd9[93]; /* 0x1B4-0x3FC: Reserved */
  67. unsigned int pmspdm[40]; /* 0x400-0x4fC: Power Manager
  68. Scratch Pad Memory 0 */
  69. };
  70. #endif /* __ASSEMBLY__ */
  71. /*
  72. * PCU Revision Register (ro)
  73. */
  74. #define ANDES_PCU_REV_NUMBER_PCS(x) (((x) >> 0) & 0xff)
  75. #define ANDES_PCU_REV_VER(x) (((x) >> 16) & 0xffff)
  76. /*
  77. * Scratch Pad Info Register (ro)
  78. */
  79. #define ANDES_PCU_SPINFO_SIZE(x) (((x) >> 0) & 0xff)
  80. #define ANDES_PCU_SPINFO_OFFSET(x) (((x) >> 8) & 0xf)
  81. /*
  82. * SoC ID Register (ro)
  83. */
  84. #define ANDES_PCU_SOC_ID_VER_MINOR(x) (((x) >> 0) & 0xf)
  85. #define ANDES_PCU_SOC_ID_VER_MAJOR(x) (((x) >> 4) & 0xfff)
  86. #define ANDES_PCU_SOC_ID_DEVICEID(x) (((x) >> 16) & 0xffff)
  87. /*
  88. * SoC AHB Configuration Register (ro)
  89. */
  90. #define ANDES_PCU_SOC_AHB_AHBC(x) ((x) << 0)
  91. #define ANDES_PCU_SOC_AHB_APBREG(x) ((x) << 1)
  92. #define ANDES_PCU_SOC_AHB_APB(x) ((x) << 2)
  93. #define ANDES_PCU_SOC_AHB_DLM1(x) ((x) << 3)
  94. #define ANDES_PCU_SOC_AHB_SPIROM(x) ((x) << 4)
  95. #define ANDES_PCU_SOC_AHB_DDR2C(x) ((x) << 5)
  96. #define ANDES_PCU_SOC_AHB_DDR2MEM(x) ((x) << 6)
  97. #define ANDES_PCU_SOC_AHB_DMAC(x) ((x) << 7)
  98. #define ANDES_PCU_SOC_AHB_DLM2(x) ((x) << 8)
  99. #define ANDES_PCU_SOC_AHB_GPU(x) ((x) << 9)
  100. #define ANDES_PCU_SOC_AHB_GMAC(x) ((x) << 12)
  101. #define ANDES_PCU_SOC_AHB_IDE(x) ((x) << 13)
  102. #define ANDES_PCU_SOC_AHB_USBOTG(x) ((x) << 14)
  103. #define ANDES_PCU_SOC_AHB_INTC(x) ((x) << 15)
  104. #define ANDES_PCU_SOC_AHB_LPCIO(x) ((x) << 16)
  105. #define ANDES_PCU_SOC_AHB_LPCREG(x) ((x) << 17)
  106. #define ANDES_PCU_SOC_AHB_PCIIO(x) ((x) << 18)
  107. #define ANDES_PCU_SOC_AHB_PCIMEM(x) ((x) << 19)
  108. #define ANDES_PCU_SOC_AHB_L2CC(x) ((x) << 20)
  109. #define ANDES_PCU_SOC_AHB_AHB2AHBREG(x) ((x) << 27)
  110. #define ANDES_PCU_SOC_AHB_AHB2AHBMEM0(x) ((x) << 28)
  111. #define ANDES_PCU_SOC_AHB_AHB2AHBMEM1(x) ((x) << 29)
  112. #define ANDES_PCU_SOC_AHB_AHB2AHBMEM2(x) ((x) << 30)
  113. #define ANDES_PCU_SOC_AHB_AHB2AHBMEM3(x) ((x) << 31)
  114. /*
  115. * SoC APB Configuration Register (ro)
  116. */
  117. #define ANDES_PCU_SOC_APB_CFC(x) ((x) << 1)
  118. #define ANDES_PCU_SOC_APB_SSP(x) ((x) << 2)
  119. #define ANDES_PCU_SOC_APB_UART1(x) ((x) << 3)
  120. #define ANDES_PCU_SOC_APB_SDC(x) ((x) << 5)
  121. #define ANDES_PCU_SOC_APB_AC97I2S(x) ((x) << 6)
  122. #define ANDES_PCU_SOC_APB_UART2(x) ((x) << 8)
  123. #define ANDES_PCU_SOC_APB_PCU(x) ((x) << 16)
  124. #define ANDES_PCU_SOC_APB_TMR(x) ((x) << 17)
  125. #define ANDES_PCU_SOC_APB_WDT(x) ((x) << 18)
  126. #define ANDES_PCU_SOC_APB_RTC(x) ((x) << 19)
  127. #define ANDES_PCU_SOC_APB_GPIO(x) ((x) << 20)
  128. #define ANDES_PCU_SOC_APB_I2C(x) ((x) << 22)
  129. #define ANDES_PCU_SOC_APB_PWM(x) ((x) << 23)
  130. /*
  131. * Driving Capability and Slew Rate Control Register 0 (rw)
  132. */
  133. #define ANDES_PCU_DCSRCR0_TRIAHB(x) (((x) & 0x1f) << 0)
  134. #define ANDES_PCU_DCSRCR0_LPC(x) (((x) & 0xf) << 8)
  135. #define ANDES_PCU_DCSRCR0_ULPI(x) (((x) & 0xf) << 12)
  136. #define ANDES_PCU_DCSRCR0_GMAC(x) (((x) & 0xf) << 16)
  137. #define ANDES_PCU_DCSRCR0_GPU(x) (((x) & 0xf) << 20)
  138. /*
  139. * Driving Capability and Slew Rate Control Register 1 (rw)
  140. */
  141. #define ANDES_PCU_DCSRCR1_I2C(x) (((x) & 0xf) << 0)
  142. /*
  143. * Driving Capability and Slew Rate Control Register 2 (rw)
  144. */
  145. #define ANDES_PCU_DCSRCR2_UART1(x) (((x) & 0xf) << 0)
  146. #define ANDES_PCU_DCSRCR2_UART2(x) (((x) & 0xf) << 4)
  147. #define ANDES_PCU_DCSRCR2_AC97(x) (((x) & 0xf) << 8)
  148. #define ANDES_PCU_DCSRCR2_SPI(x) (((x) & 0xf) << 12)
  149. #define ANDES_PCU_DCSRCR2_SD(x) (((x) & 0xf) << 16)
  150. #define ANDES_PCU_DCSRCR2_CFC(x) (((x) & 0xf) << 20)
  151. #define ANDES_PCU_DCSRCR2_GPIO(x) (((x) & 0xf) << 24)
  152. #define ANDES_PCU_DCSRCR2_PCU(x) (((x) & 0xf) << 28)
  153. /*
  154. * Multi-function Port Setting Register 0 (rw)
  155. */
  156. #define ANDES_PCU_MFPSR0_PCIMODE(x) ((x) << 0)
  157. #define ANDES_PCU_MFPSR0_IDEMODE(x) ((x) << 1)
  158. #define ANDES_PCU_MFPSR0_MINI_TC01(x) ((x) << 2)
  159. #define ANDES_PCU_MFPSR0_AHB_DEBUG(x) ((x) << 3)
  160. #define ANDES_PCU_MFPSR0_AHB_TARGET(x) ((x) << 4)
  161. #define ANDES_PCU_MFPSR0_DEFAULT_IVB(x) (((x) & 0x7) << 28)
  162. #define ANDES_PCU_MFPSR0_DEFAULT_ENDIAN(x) ((x) << 31)
  163. /*
  164. * Multi-function Port Setting Register 1 (rw)
  165. */
  166. #define ANDES_PCU_MFPSR1_SUSPEND(x) ((x) << 0)
  167. #define ANDES_PCU_MFPSR1_PWM0(x) ((x) << 1)
  168. #define ANDES_PCU_MFPSR1_PWM1(x) ((x) << 2)
  169. #define ANDES_PCU_MFPSR1_AC97CLKOUT(x) ((x) << 3)
  170. #define ANDES_PCU_MFPSR1_PWREN(x) ((x) << 4)
  171. #define ANDES_PCU_MFPSR1_PME(x) ((x) << 5)
  172. #define ANDES_PCU_MFPSR1_I2C(x) ((x) << 6)
  173. #define ANDES_PCU_MFPSR1_UART1(x) ((x) << 7)
  174. #define ANDES_PCU_MFPSR1_UART2(x) ((x) << 8)
  175. #define ANDES_PCU_MFPSR1_SPI(x) ((x) << 9)
  176. #define ANDES_PCU_MFPSR1_SD(x) ((x) << 10)
  177. #define ANDES_PCU_MFPSR1_GPUPLLSRC(x) ((x) << 27)
  178. #define ANDES_PCU_MFPSR1_DVOMODE(x) ((x) << 28)
  179. #define ANDES_PCU_MFPSR1_HSMP_FAST_REQ(x) ((x) << 29)
  180. #define ANDES_PCU_MFPSR1_AHB_FAST_REQ(x) ((x) << 30)
  181. #define ANDES_PCU_MFPSR1_PMUR_EXT_INT(x) ((x) << 31)
  182. /*
  183. * DMA Engine Selection Register (rw)
  184. */
  185. #define ANDES_PCU_DMAES_AC97RX(x) ((x) << 2)
  186. #define ANDES_PCU_DMAES_AC97TX(x) ((x) << 3)
  187. #define ANDES_PCU_DMAES_UART1RX(x) ((x) << 4)
  188. #define ANDES_PCU_DMAES_UART1TX(x) ((x) << 5)
  189. #define ANDES_PCU_DMAES_UART2RX(x) ((x) << 6)
  190. #define ANDES_PCU_DMAES_UART2TX(x) ((x) << 7)
  191. #define ANDES_PCU_DMAES_SDDMA(x) ((x) << 8)
  192. #define ANDES_PCU_DMAES_CFCDMA(x) ((x) << 9)
  193. /*
  194. * OSC Control Register (rw)
  195. */
  196. #define ANDES_PCU_OSCC_OSCH_OFF(x) ((x) << 0)
  197. #define ANDES_PCU_OSCC_OSCH_STABLE(x) ((x) << 1)
  198. #define ANDES_PCU_OSCC_OSCH_TRI(x) ((x) << 2)
  199. #define ANDES_PCU_OSCC_OSCH_RANGE(x) (((x) & 0x3) << 4)
  200. #define ANDES_PCU_OSCC_OSCH2_RANGE(x) (((x) & 0x3) << 6)
  201. #define ANDES_PCU_OSCC_OSCH3_RANGE(x) (((x) & 0x3) << 8)
  202. /*
  203. * PWM Clock Divider Register (rw)
  204. */
  205. #define ANDES_PCU_PWMCD_PWMDIV(x) (((x) & 0xf) << 0)
  206. /*
  207. * SoC Misc. Register (rw)
  208. */
  209. #define ANDES_PCU_SOCMISC_RSCPUA(x) ((x) << 0)
  210. #define ANDES_PCU_SOCMISC_RSCPUB(x) ((x) << 1)
  211. #define ANDES_PCU_SOCMISC_RSPCI(x) ((x) << 2)
  212. #define ANDES_PCU_SOCMISC_USBWAKE(x) ((x) << 3)
  213. #define ANDES_PCU_SOCMISC_EXLM_WAITA(x) (((x) & 0x3) << 4)
  214. #define ANDES_PCU_SOCMISC_EXLM_WAITB(x) (((x) & 0x3) << 6)
  215. #define ANDES_PCU_SOCMISC_DDRPLL_BYPASS(x) (((x) << 8)
  216. #define ANDES_PCU_SOCMISC_300MHZSEL(x) (((x) << 9)
  217. #define ANDES_PCU_SOCMISC_DDRDLL_SRST(x) (((x) << 10)
  218. #define ANDES_PCU_SOCMISC_DDRDDQ_TEST(x) (((x) << 11)
  219. #define ANDES_PCU_SOCMISC_DDRDLL_TEST(x) (((x) << 12)
  220. #define ANDES_PCU_SOCMISC_GPUPLL_BYPASS(x) (((x) << 13)
  221. #define ANDES_PCU_SOCMISC_ENCPUA(x) (((x) << 14)
  222. #define ANDES_PCU_SOCMISC_ENCPUB(x) (((x) << 15)
  223. #define ANDES_PCU_SOCMISC_PWON_PWBTN(x) (((x) << 16)
  224. #define ANDES_PCU_SOCMISC_PWON_GPIO1(x) (((x) << 17)
  225. #define ANDES_PCU_SOCMISC_PWON_GPIO2(x) (((x) << 18)
  226. #define ANDES_PCU_SOCMISC_PWON_GPIO3(x) (((x) << 19)
  227. #define ANDES_PCU_SOCMISC_PWON_GPIO4(x) (((x) << 20)
  228. #define ANDES_PCU_SOCMISC_PWON_GPIO5(x) (((x) << 21)
  229. #define ANDES_PCU_SOCMISC_PWON_WOL(x) (((x) << 22)
  230. #define ANDES_PCU_SOCMISC_PWON_RTC(x) (((x) << 23)
  231. #define ANDES_PCU_SOCMISC_PWON_RTCALM(x) (((x) << 24)
  232. #define ANDES_PCU_SOCMISC_PWON_XDBGIN(x) (((x) << 25)
  233. #define ANDES_PCU_SOCMISC_PWON_PME(x) (((x) << 26)
  234. #define ANDES_PCU_SOCMISC_PWON_PWFAIL(x) (((x) << 27)
  235. #define ANDES_PCU_SOCMISC_CPUA_SRSTED(x) (((x) << 28)
  236. #define ANDES_PCU_SOCMISC_CPUB_SRSTED(x) (((x) << 29)
  237. #define ANDES_PCU_SOCMISC_WD_RESET(x) (((x) << 30)
  238. #define ANDES_PCU_SOCMISC_HW_RESET(x) (((x) << 31)
  239. /*
  240. * BSM Control Register (rw)
  241. */
  242. #define ANDES_PCU_BSMCR_LINK0(x) (((x) & 0xf) << 0)
  243. #define ANDES_PCU_BSMCR_LINK1(x) (((x) & 0xf) << 4)
  244. #define ANDES_PCU_BSMCR_SYNCSRC(x) (((x) & 0xf) << 24)
  245. #define ANDES_PCU_BSMCR_CMD(x) (((x) & 0x7) << 28)
  246. #define ANDES_PCU_BSMCR_IE(x) ((x) << 31)
  247. /*
  248. * BSM Status Register
  249. */
  250. #define ANDES_PCU_BSMSR_CI0(x) (((x) & 0xf) << 0)
  251. #define ANDES_PCU_BSMSR_CI1(x) (((x) & 0xf) << 4)
  252. #define ANDES_PCU_BSMSR_SYNCSRC(x) (((x) & 0xf) << 24)
  253. #define ANDES_PCU_BSMSR_BSMST(x) (((x) & 0xf) << 28)
  254. /*
  255. * Wakeup Event Sensitivity Register (rw)
  256. */
  257. #define ANDES_PCU_WESR_POLOR(x) (((x) & 0xff) << 0)
  258. /*
  259. * Wakeup Event Status Register (ro)
  260. */
  261. #define ANDES_PCU_WEST_SIG(x) (((x) & 0xff) << 0)
  262. /*
  263. * Reset Timing Register
  264. */
  265. #define ANDES_PCU_RSTTIMING_RG0(x) (((x) & 0xff) << 0)
  266. #define ANDES_PCU_RSTTIMING_RG1(x) (((x) & 0xff) << 8)
  267. #define ANDES_PCU_RSTTIMING_RG2(x) (((x) & 0xff) << 16)
  268. #define ANDES_PCU_RSTTIMING_RG3(x) (((x) & 0xff) << 24)
  269. /*
  270. * PCU Interrupt Status Register
  271. */
  272. #define ANDES_PCU_INTR_ST_BSM(x) ((x) << 0)
  273. #define ANDES_PCU_INTR_ST_PCS1(x) ((x) << 1)
  274. #define ANDES_PCU_INTR_ST_PCS2(x) ((x) << 2)
  275. #define ANDES_PCU_INTR_ST_PCS3(x) ((x) << 3)
  276. #define ANDES_PCU_INTR_ST_PCS4(x) ((x) << 4)
  277. #define ANDES_PCU_INTR_ST_PCS5(x) ((x) << 5)
  278. #define ANDES_PCU_INTR_ST_PCS6(x) ((x) << 6)
  279. #define ANDES_PCU_INTR_ST_PCS7(x) ((x) << 7)
  280. #define ANDES_PCU_INTR_ST_PCS8(x) ((x) << 8)
  281. #define ANDES_PCU_INTR_ST_PCS9(x) ((x) << 9)
  282. /*
  283. * PCSx Configuration Register
  284. */
  285. #define ANDES_PCU_PCSX_CR_WAKEUP_EN(x) (((x) & 0xff) << 0)
  286. #define ANDES_PCU_PCSX_CR_LW(x) (((x) & 0xf) << 16)
  287. #define ANDES_PCU_PCSX_CR_LS(x) (((x) & 0xf) << 20)
  288. #define ANDES_PCU_PCSX_CR_TYPE(x) (((x) >> 28) & 0x7) /* (ro) */
  289. /*
  290. * PCSx Parameter Register (rw)
  291. */
  292. #define ANDES_PCU_PCSX_PARM_NEXT(x) (((x) & 0xffffff) << 0)
  293. #define ANDES_PCU_PCSX_PARM_SYNCSRC(x) (((x) & 0xf) << 24)
  294. #define ANDES_PCU_PCSX_PARM_PCSCMD(x) (((x) & 0x7) << 28)
  295. #define ANDES_PCU_PCSX_PARM_IE(x) (((x) << 31)
  296. /*
  297. * PCSx Status Register 1
  298. */
  299. #define ANDES_PCU_PCSX_STAT1_ERRNO(x) (((x) & 0xf) << 0)
  300. #define ANDES_PCU_PCSX_STAT1_ST(x) (((x) & 0x7) << 28)
  301. /*
  302. * PCSx Status Register 2
  303. */
  304. #define ANDES_PCU_PCSX_STAT2_CRNTPARM(x) (((x) & 0xffffff) << 0)
  305. #define ANDES_PCU_PCSX_STAT2_SYNCSRC(x) (((x) & 0xf) << 24)
  306. /*
  307. * PCSx PDD Register
  308. * This is reserved for PCS(1-7)
  309. */
  310. #define ANDES_PCU_PCS8_PDD_1BYTE(x) (((x) & 0xff) << 0)
  311. #define ANDES_PCU_PCS8_PDD_2BYTE(x) (((x) & 0xff) << 8)
  312. #define ANDES_PCU_PCS8_PDD_3BYTE(x) (((x) & 0xff) << 16)
  313. #define ANDES_PCU_PCS8_PDD_4BYTE(x) (((x) & 0xff) << 24)
  314. #define ANDES_PCU_PCS9_PDD_TIME1(x) (((x) & 0x3f) << 0)
  315. #define ANDES_PCU_PCS9_PDD_TIME2(x) (((x) & 0x3f) << 6)
  316. #define ANDES_PCU_PCS9_PDD_TIME3(x) (((x) & 0x3f) << 12)
  317. #define ANDES_PCU_PCS9_PDD_TIME4(x) (((x) & 0x3f) << 18)
  318. #define ANDES_PCU_PCS9_PDD_TICKTYPE(x) ((x) << 24)
  319. #define ANDES_PCU_PCS9_PDD_GPU_SRST(x) ((x) << 27)
  320. #define ANDES_PCU_PCS9_PDD_PWOFFTIME(x) (((x) & 0x3) << 28)
  321. #define ANDES_PCU_PCS9_PDD_SUS2DRAM(x) ((x) << 30)
  322. #define ANDES_PCU_PCS9_PDD_CLRPWOFF_FLAG(x) ((x) << 31)
  323. #endif /* __ANDES_PCU_H */