sunxi_display.c 37 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Display driver for Allwinner SoCs.
  4. *
  5. * (C) Copyright 2013-2014 Luc Verhaegen <libv@skynet.be>
  6. * (C) Copyright 2014-2015 Hans de Goede <hdegoede@redhat.com>
  7. */
  8. #include <common.h>
  9. #include <cpu_func.h>
  10. #include <efi_loader.h>
  11. #include <init.h>
  12. #include <time.h>
  13. #include <linux/delay.h>
  14. #include <asm/arch/clock.h>
  15. #include <asm/arch/display.h>
  16. #include <asm/arch/gpio.h>
  17. #include <asm/arch/lcdc.h>
  18. #include <asm/arch/pwm.h>
  19. #include <asm/arch/tve.h>
  20. #include <asm/global_data.h>
  21. #include <asm/gpio.h>
  22. #include <asm/io.h>
  23. #include <axp_pmic.h>
  24. #include <errno.h>
  25. #include <fdtdec.h>
  26. #include <fdt_support.h>
  27. #include <i2c.h>
  28. #include <malloc.h>
  29. #include <video_fb.h>
  30. #include "../videomodes.h"
  31. #include "../anx9804.h"
  32. #include "../hitachi_tx18d42vm_lcd.h"
  33. #include "../ssd2828.h"
  34. #include "simplefb_common.h"
  35. #ifdef CONFIG_VIDEO_LCD_BL_PWM_ACTIVE_LOW
  36. #define PWM_ON 0
  37. #define PWM_OFF 1
  38. #else
  39. #define PWM_ON 1
  40. #define PWM_OFF 0
  41. #endif
  42. DECLARE_GLOBAL_DATA_PTR;
  43. enum sunxi_monitor {
  44. sunxi_monitor_none,
  45. sunxi_monitor_dvi,
  46. sunxi_monitor_hdmi,
  47. sunxi_monitor_lcd,
  48. sunxi_monitor_vga,
  49. sunxi_monitor_composite_pal,
  50. sunxi_monitor_composite_ntsc,
  51. sunxi_monitor_composite_pal_m,
  52. sunxi_monitor_composite_pal_nc,
  53. };
  54. #define SUNXI_MONITOR_LAST sunxi_monitor_composite_pal_nc
  55. struct sunxi_display {
  56. GraphicDevice graphic_device;
  57. enum sunxi_monitor monitor;
  58. unsigned int depth;
  59. unsigned int fb_addr;
  60. unsigned int fb_size;
  61. } sunxi_display;
  62. const struct ctfb_res_modes composite_video_modes[2] = {
  63. /* x y hz pixclk ps/kHz le ri up lo hs vs s vmode */
  64. { 720, 576, 50, 37037, 27000, 137, 5, 20, 27, 2, 2, 0, FB_VMODE_INTERLACED },
  65. { 720, 480, 60, 37037, 27000, 116, 20, 16, 27, 2, 2, 0, FB_VMODE_INTERLACED },
  66. };
  67. #ifdef CONFIG_VIDEO_HDMI
  68. /*
  69. * Wait up to 200ms for value to be set in given part of reg.
  70. */
  71. static int await_completion(u32 *reg, u32 mask, u32 val)
  72. {
  73. unsigned long tmo = timer_get_us() + 200000;
  74. while ((readl(reg) & mask) != val) {
  75. if (timer_get_us() > tmo) {
  76. printf("DDC: timeout reading EDID\n");
  77. return -ETIME;
  78. }
  79. }
  80. return 0;
  81. }
  82. static int sunxi_hdmi_hpd_detect(int hpd_delay)
  83. {
  84. struct sunxi_ccm_reg * const ccm =
  85. (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  86. struct sunxi_hdmi_reg * const hdmi =
  87. (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
  88. unsigned long tmo = timer_get_us() + hpd_delay * 1000;
  89. /* Set pll3 to 300MHz */
  90. clock_set_pll3(300000000);
  91. /* Set hdmi parent to pll3 */
  92. clrsetbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_PLL_MASK,
  93. CCM_HDMI_CTRL_PLL3);
  94. /* Set ahb gating to pass */
  95. #ifdef CONFIG_SUNXI_GEN_SUN6I
  96. setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);
  97. #endif
  98. setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
  99. /* Clock on */
  100. setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
  101. writel(SUNXI_HDMI_CTRL_ENABLE, &hdmi->ctrl);
  102. writel(SUNXI_HDMI_PAD_CTRL0_HDP, &hdmi->pad_ctrl0);
  103. /* Enable PLLs for eventual DDC */
  104. writel(SUNXI_HDMI_PAD_CTRL1 | SUNXI_HDMI_PAD_CTRL1_HALVE,
  105. &hdmi->pad_ctrl1);
  106. writel(SUNXI_HDMI_PLL_CTRL | SUNXI_HDMI_PLL_CTRL_DIV(15),
  107. &hdmi->pll_ctrl);
  108. writel(SUNXI_HDMI_PLL_DBG0_PLL3, &hdmi->pll_dbg0);
  109. while (timer_get_us() < tmo) {
  110. if (readl(&hdmi->hpd) & SUNXI_HDMI_HPD_DETECT)
  111. return 1;
  112. }
  113. return 0;
  114. }
  115. static void sunxi_hdmi_shutdown(void)
  116. {
  117. struct sunxi_ccm_reg * const ccm =
  118. (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  119. struct sunxi_hdmi_reg * const hdmi =
  120. (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
  121. clrbits_le32(&hdmi->ctrl, SUNXI_HDMI_CTRL_ENABLE);
  122. clrbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
  123. clrbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
  124. #ifdef CONFIG_SUNXI_GEN_SUN6I
  125. clrbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);
  126. #endif
  127. clock_set_pll3(0);
  128. }
  129. static int sunxi_hdmi_ddc_do_command(u32 cmnd, int offset, int n)
  130. {
  131. struct sunxi_hdmi_reg * const hdmi =
  132. (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
  133. setbits_le32(&hdmi->ddc_fifo_ctrl, SUNXI_HDMI_DDC_FIFO_CTRL_CLEAR);
  134. writel(SUNXI_HMDI_DDC_ADDR_EDDC_SEGMENT(offset >> 8) |
  135. SUNXI_HMDI_DDC_ADDR_EDDC_ADDR |
  136. SUNXI_HMDI_DDC_ADDR_OFFSET(offset) |
  137. SUNXI_HMDI_DDC_ADDR_SLAVE_ADDR, &hdmi->ddc_addr);
  138. #ifndef CONFIG_MACH_SUN6I
  139. writel(n, &hdmi->ddc_byte_count);
  140. writel(cmnd, &hdmi->ddc_cmnd);
  141. #else
  142. writel(n << 16 | cmnd, &hdmi->ddc_cmnd);
  143. #endif
  144. setbits_le32(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_START);
  145. return await_completion(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_START, 0);
  146. }
  147. static int sunxi_hdmi_ddc_read(int offset, u8 *buf, int count)
  148. {
  149. struct sunxi_hdmi_reg * const hdmi =
  150. (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
  151. int i, n;
  152. while (count > 0) {
  153. if (count > 16)
  154. n = 16;
  155. else
  156. n = count;
  157. if (sunxi_hdmi_ddc_do_command(
  158. SUNXI_HDMI_DDC_CMND_EXPLICIT_EDDC_READ,
  159. offset, n))
  160. return -ETIME;
  161. for (i = 0; i < n; i++)
  162. *buf++ = readb(&hdmi->ddc_fifo_data);
  163. offset += n;
  164. count -= n;
  165. }
  166. return 0;
  167. }
  168. static int sunxi_hdmi_edid_get_block(int block, u8 *buf)
  169. {
  170. int r, retries = 2;
  171. do {
  172. r = sunxi_hdmi_ddc_read(block * 128, buf, 128);
  173. if (r)
  174. continue;
  175. r = edid_check_checksum(buf);
  176. if (r) {
  177. printf("EDID block %d: checksum error%s\n",
  178. block, retries ? ", retrying" : "");
  179. }
  180. } while (r && retries--);
  181. return r;
  182. }
  183. static int sunxi_hdmi_edid_get_mode(struct ctfb_res_modes *mode,
  184. bool verbose_mode)
  185. {
  186. struct edid1_info edid1;
  187. struct edid_cea861_info cea681[4];
  188. struct edid_detailed_timing *t =
  189. (struct edid_detailed_timing *)edid1.monitor_details.timing;
  190. struct sunxi_hdmi_reg * const hdmi =
  191. (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
  192. struct sunxi_ccm_reg * const ccm =
  193. (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  194. int i, r, ext_blocks = 0;
  195. /* Reset i2c controller */
  196. setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_DDC_GATE);
  197. writel(SUNXI_HMDI_DDC_CTRL_ENABLE |
  198. SUNXI_HMDI_DDC_CTRL_SDA_ENABLE |
  199. SUNXI_HMDI_DDC_CTRL_SCL_ENABLE |
  200. SUNXI_HMDI_DDC_CTRL_RESET, &hdmi->ddc_ctrl);
  201. if (await_completion(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_RESET, 0))
  202. return -EIO;
  203. writel(SUNXI_HDMI_DDC_CLOCK, &hdmi->ddc_clock);
  204. #ifndef CONFIG_MACH_SUN6I
  205. writel(SUNXI_HMDI_DDC_LINE_CTRL_SDA_ENABLE |
  206. SUNXI_HMDI_DDC_LINE_CTRL_SCL_ENABLE, &hdmi->ddc_line_ctrl);
  207. #endif
  208. r = sunxi_hdmi_edid_get_block(0, (u8 *)&edid1);
  209. if (r == 0) {
  210. r = edid_check_info(&edid1);
  211. if (r) {
  212. if (verbose_mode)
  213. printf("EDID: invalid EDID data\n");
  214. r = -EINVAL;
  215. }
  216. }
  217. if (r == 0) {
  218. ext_blocks = edid1.extension_flag;
  219. if (ext_blocks > 4)
  220. ext_blocks = 4;
  221. for (i = 0; i < ext_blocks; i++) {
  222. if (sunxi_hdmi_edid_get_block(1 + i,
  223. (u8 *)&cea681[i]) != 0) {
  224. ext_blocks = i;
  225. break;
  226. }
  227. }
  228. }
  229. /* Disable DDC engine, no longer needed */
  230. clrbits_le32(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_ENABLE);
  231. clrbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_DDC_GATE);
  232. if (r)
  233. return r;
  234. /* We want version 1.3 or 1.2 with detailed timing info */
  235. if (edid1.version != 1 || (edid1.revision < 3 &&
  236. !EDID1_INFO_FEATURE_PREFERRED_TIMING_MODE(edid1))) {
  237. printf("EDID: unsupported version %d.%d\n",
  238. edid1.version, edid1.revision);
  239. return -EINVAL;
  240. }
  241. /* Take the first usable detailed timing */
  242. for (i = 0; i < 4; i++, t++) {
  243. r = video_edid_dtd_to_ctfb_res_modes(t, mode);
  244. if (r == 0)
  245. break;
  246. }
  247. if (i == 4) {
  248. printf("EDID: no usable detailed timing found\n");
  249. return -ENOENT;
  250. }
  251. /* Check for basic audio support, if found enable hdmi output */
  252. sunxi_display.monitor = sunxi_monitor_dvi;
  253. for (i = 0; i < ext_blocks; i++) {
  254. if (cea681[i].extension_tag != EDID_CEA861_EXTENSION_TAG ||
  255. cea681[i].revision < 2)
  256. continue;
  257. if (EDID_CEA861_SUPPORTS_BASIC_AUDIO(cea681[i]))
  258. sunxi_display.monitor = sunxi_monitor_hdmi;
  259. }
  260. return 0;
  261. }
  262. #endif /* CONFIG_VIDEO_HDMI */
  263. #ifdef CONFIG_MACH_SUN4I
  264. /*
  265. * Testing has shown that on sun4i the display backend engine does not have
  266. * deep enough fifo-s causing flickering / tearing in full-hd mode due to
  267. * fifo underruns. So on sun4i we use the display frontend engine to do the
  268. * dma from memory, as the frontend does have deep enough fifo-s.
  269. */
  270. static const u32 sun4i_vert_coef[32] = {
  271. 0x00004000, 0x000140ff, 0x00033ffe, 0x00043ffd,
  272. 0x00063efc, 0xff083dfc, 0x000a3bfb, 0xff0d39fb,
  273. 0xff0f37fb, 0xff1136fa, 0xfe1433fb, 0xfe1631fb,
  274. 0xfd192ffb, 0xfd1c2cfb, 0xfd1f29fb, 0xfc2127fc,
  275. 0xfc2424fc, 0xfc2721fc, 0xfb291ffd, 0xfb2c1cfd,
  276. 0xfb2f19fd, 0xfb3116fe, 0xfb3314fe, 0xfa3611ff,
  277. 0xfb370fff, 0xfb390dff, 0xfb3b0a00, 0xfc3d08ff,
  278. 0xfc3e0600, 0xfd3f0400, 0xfe3f0300, 0xff400100,
  279. };
  280. static const u32 sun4i_horz_coef[64] = {
  281. 0x40000000, 0x00000000, 0x40fe0000, 0x0000ff03,
  282. 0x3ffd0000, 0x0000ff05, 0x3ffc0000, 0x0000ff06,
  283. 0x3efb0000, 0x0000ff08, 0x3dfb0000, 0x0000ff09,
  284. 0x3bfa0000, 0x0000fe0d, 0x39fa0000, 0x0000fe0f,
  285. 0x38fa0000, 0x0000fe10, 0x36fa0000, 0x0000fe12,
  286. 0x33fa0000, 0x0000fd16, 0x31fa0000, 0x0000fd18,
  287. 0x2ffa0000, 0x0000fd1a, 0x2cfa0000, 0x0000fc1e,
  288. 0x29fa0000, 0x0000fc21, 0x27fb0000, 0x0000fb23,
  289. 0x24fb0000, 0x0000fb26, 0x21fb0000, 0x0000fb29,
  290. 0x1ffc0000, 0x0000fa2b, 0x1cfc0000, 0x0000fa2e,
  291. 0x19fd0000, 0x0000fa30, 0x16fd0000, 0x0000fa33,
  292. 0x14fd0000, 0x0000fa35, 0x11fe0000, 0x0000fa37,
  293. 0x0ffe0000, 0x0000fa39, 0x0dfe0000, 0x0000fa3b,
  294. 0x0afe0000, 0x0000fa3e, 0x08ff0000, 0x0000fb3e,
  295. 0x06ff0000, 0x0000fb40, 0x05ff0000, 0x0000fc40,
  296. 0x03ff0000, 0x0000fd41, 0x01ff0000, 0x0000fe42,
  297. };
  298. static void sunxi_frontend_init(void)
  299. {
  300. struct sunxi_ccm_reg * const ccm =
  301. (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  302. struct sunxi_de_fe_reg * const de_fe =
  303. (struct sunxi_de_fe_reg *)SUNXI_DE_FE0_BASE;
  304. int i;
  305. /* Clocks on */
  306. setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_DE_FE0);
  307. setbits_le32(&ccm->dram_clk_gate, 1 << CCM_DRAM_GATE_OFFSET_DE_FE0);
  308. clock_set_de_mod_clock(&ccm->fe0_clk_cfg, 300000000);
  309. setbits_le32(&de_fe->enable, SUNXI_DE_FE_ENABLE_EN);
  310. for (i = 0; i < 32; i++) {
  311. writel(sun4i_horz_coef[2 * i], &de_fe->ch0_horzcoef0[i]);
  312. writel(sun4i_horz_coef[2 * i + 1], &de_fe->ch0_horzcoef1[i]);
  313. writel(sun4i_vert_coef[i], &de_fe->ch0_vertcoef[i]);
  314. writel(sun4i_horz_coef[2 * i], &de_fe->ch1_horzcoef0[i]);
  315. writel(sun4i_horz_coef[2 * i + 1], &de_fe->ch1_horzcoef1[i]);
  316. writel(sun4i_vert_coef[i], &de_fe->ch1_vertcoef[i]);
  317. }
  318. setbits_le32(&de_fe->frame_ctrl, SUNXI_DE_FE_FRAME_CTRL_COEF_RDY);
  319. }
  320. static void sunxi_frontend_mode_set(const struct ctfb_res_modes *mode,
  321. unsigned int address)
  322. {
  323. struct sunxi_de_fe_reg * const de_fe =
  324. (struct sunxi_de_fe_reg *)SUNXI_DE_FE0_BASE;
  325. setbits_le32(&de_fe->bypass, SUNXI_DE_FE_BYPASS_CSC_BYPASS);
  326. writel(CONFIG_SYS_SDRAM_BASE + address, &de_fe->ch0_addr);
  327. writel(mode->xres * 4, &de_fe->ch0_stride);
  328. writel(SUNXI_DE_FE_INPUT_FMT_ARGB8888, &de_fe->input_fmt);
  329. writel(SUNXI_DE_FE_OUTPUT_FMT_ARGB8888, &de_fe->output_fmt);
  330. writel(SUNXI_DE_FE_HEIGHT(mode->yres) | SUNXI_DE_FE_WIDTH(mode->xres),
  331. &de_fe->ch0_insize);
  332. writel(SUNXI_DE_FE_HEIGHT(mode->yres) | SUNXI_DE_FE_WIDTH(mode->xres),
  333. &de_fe->ch0_outsize);
  334. writel(SUNXI_DE_FE_FACTOR_INT(1), &de_fe->ch0_horzfact);
  335. writel(SUNXI_DE_FE_FACTOR_INT(1), &de_fe->ch0_vertfact);
  336. writel(SUNXI_DE_FE_HEIGHT(mode->yres) | SUNXI_DE_FE_WIDTH(mode->xres),
  337. &de_fe->ch1_insize);
  338. writel(SUNXI_DE_FE_HEIGHT(mode->yres) | SUNXI_DE_FE_WIDTH(mode->xres),
  339. &de_fe->ch1_outsize);
  340. writel(SUNXI_DE_FE_FACTOR_INT(1), &de_fe->ch1_horzfact);
  341. writel(SUNXI_DE_FE_FACTOR_INT(1), &de_fe->ch1_vertfact);
  342. setbits_le32(&de_fe->frame_ctrl, SUNXI_DE_FE_FRAME_CTRL_REG_RDY);
  343. }
  344. static void sunxi_frontend_enable(void)
  345. {
  346. struct sunxi_de_fe_reg * const de_fe =
  347. (struct sunxi_de_fe_reg *)SUNXI_DE_FE0_BASE;
  348. setbits_le32(&de_fe->frame_ctrl, SUNXI_DE_FE_FRAME_CTRL_FRM_START);
  349. }
  350. #else
  351. static void sunxi_frontend_init(void) {}
  352. static void sunxi_frontend_mode_set(const struct ctfb_res_modes *mode,
  353. unsigned int address) {}
  354. static void sunxi_frontend_enable(void) {}
  355. #endif
  356. static bool sunxi_is_composite(void)
  357. {
  358. switch (sunxi_display.monitor) {
  359. case sunxi_monitor_none:
  360. case sunxi_monitor_dvi:
  361. case sunxi_monitor_hdmi:
  362. case sunxi_monitor_lcd:
  363. case sunxi_monitor_vga:
  364. return false;
  365. case sunxi_monitor_composite_pal:
  366. case sunxi_monitor_composite_ntsc:
  367. case sunxi_monitor_composite_pal_m:
  368. case sunxi_monitor_composite_pal_nc:
  369. return true;
  370. }
  371. return false; /* Never reached */
  372. }
  373. /*
  374. * This is the entity that mixes and matches the different layers and inputs.
  375. * Allwinner calls it the back-end, but i like composer better.
  376. */
  377. static void sunxi_composer_init(void)
  378. {
  379. struct sunxi_ccm_reg * const ccm =
  380. (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  381. struct sunxi_de_be_reg * const de_be =
  382. (struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
  383. int i;
  384. sunxi_frontend_init();
  385. #ifdef CONFIG_SUNXI_GEN_SUN6I
  386. /* Reset off */
  387. setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DE_BE0);
  388. #endif
  389. /* Clocks on */
  390. setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_DE_BE0);
  391. #ifndef CONFIG_MACH_SUN4I /* On sun4i the frontend does the dma */
  392. setbits_le32(&ccm->dram_clk_gate, 1 << CCM_DRAM_GATE_OFFSET_DE_BE0);
  393. #endif
  394. clock_set_de_mod_clock(&ccm->be0_clk_cfg, 300000000);
  395. /* Engine bug, clear registers after reset */
  396. for (i = 0x0800; i < 0x1000; i += 4)
  397. writel(0, SUNXI_DE_BE0_BASE + i);
  398. setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_ENABLE);
  399. }
  400. static const u32 sunxi_rgb2yuv_coef[12] = {
  401. 0x00000107, 0x00000204, 0x00000064, 0x00000108,
  402. 0x00003f69, 0x00003ed6, 0x000001c1, 0x00000808,
  403. 0x000001c1, 0x00003e88, 0x00003fb8, 0x00000808
  404. };
  405. static void sunxi_composer_mode_set(const struct ctfb_res_modes *mode,
  406. unsigned int address)
  407. {
  408. struct sunxi_de_be_reg * const de_be =
  409. (struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
  410. int i;
  411. sunxi_frontend_mode_set(mode, address);
  412. writel(SUNXI_DE_BE_HEIGHT(mode->yres) | SUNXI_DE_BE_WIDTH(mode->xres),
  413. &de_be->disp_size);
  414. writel(SUNXI_DE_BE_HEIGHT(mode->yres) | SUNXI_DE_BE_WIDTH(mode->xres),
  415. &de_be->layer0_size);
  416. #ifndef CONFIG_MACH_SUN4I /* On sun4i the frontend does the dma */
  417. writel(SUNXI_DE_BE_LAYER_STRIDE(mode->xres), &de_be->layer0_stride);
  418. writel(address << 3, &de_be->layer0_addr_low32b);
  419. writel(address >> 29, &de_be->layer0_addr_high4b);
  420. #else
  421. writel(SUNXI_DE_BE_LAYER_ATTR0_SRC_FE0, &de_be->layer0_attr0_ctrl);
  422. #endif
  423. writel(SUNXI_DE_BE_LAYER_ATTR1_FMT_XRGB8888, &de_be->layer0_attr1_ctrl);
  424. setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_LAYER0_ENABLE);
  425. if (mode->vmode == FB_VMODE_INTERLACED)
  426. setbits_le32(&de_be->mode,
  427. #ifndef CONFIG_MACH_SUN5I
  428. SUNXI_DE_BE_MODE_DEFLICKER_ENABLE |
  429. #endif
  430. SUNXI_DE_BE_MODE_INTERLACE_ENABLE);
  431. if (sunxi_is_composite()) {
  432. writel(SUNXI_DE_BE_OUTPUT_COLOR_CTRL_ENABLE,
  433. &de_be->output_color_ctrl);
  434. for (i = 0; i < 12; i++)
  435. writel(sunxi_rgb2yuv_coef[i],
  436. &de_be->output_color_coef[i]);
  437. }
  438. }
  439. static void sunxi_composer_enable(void)
  440. {
  441. struct sunxi_de_be_reg * const de_be =
  442. (struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
  443. sunxi_frontend_enable();
  444. setbits_le32(&de_be->reg_ctrl, SUNXI_DE_BE_REG_CTRL_LOAD_REGS);
  445. setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_START);
  446. }
  447. static void sunxi_lcdc_init(void)
  448. {
  449. struct sunxi_ccm_reg * const ccm =
  450. (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  451. struct sunxi_lcdc_reg * const lcdc =
  452. (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
  453. /* Reset off */
  454. #ifdef CONFIG_SUNXI_GEN_SUN6I
  455. setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0);
  456. #else
  457. setbits_le32(&ccm->lcd0_ch0_clk_cfg, CCM_LCD_CH0_CTRL_RST);
  458. #endif
  459. /* Clock on */
  460. setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD0);
  461. #ifdef CONFIG_VIDEO_LCD_IF_LVDS
  462. #ifdef CONFIG_SUNXI_GEN_SUN6I
  463. setbits_le32(&ccm->ahb_reset2_cfg, 1 << AHB_RESET_OFFSET_LVDS);
  464. #else
  465. setbits_le32(&ccm->lvds_clk_cfg, CCM_LVDS_CTRL_RST);
  466. #endif
  467. #endif
  468. lcdc_init(lcdc);
  469. }
  470. static void sunxi_lcdc_panel_enable(void)
  471. {
  472. int pin, reset_pin;
  473. /*
  474. * Start with backlight disabled to avoid the screen flashing to
  475. * white while the lcd inits.
  476. */
  477. pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_BL_EN);
  478. if (pin >= 0) {
  479. gpio_request(pin, "lcd_backlight_enable");
  480. gpio_direction_output(pin, 0);
  481. }
  482. pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_BL_PWM);
  483. if (pin >= 0) {
  484. gpio_request(pin, "lcd_backlight_pwm");
  485. gpio_direction_output(pin, PWM_OFF);
  486. }
  487. reset_pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_RESET);
  488. if (reset_pin >= 0) {
  489. gpio_request(reset_pin, "lcd_reset");
  490. gpio_direction_output(reset_pin, 0); /* Assert reset */
  491. }
  492. /* Give the backlight some time to turn off and power up the panel. */
  493. mdelay(40);
  494. pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_POWER);
  495. if (pin >= 0) {
  496. gpio_request(pin, "lcd_power");
  497. gpio_direction_output(pin, 1);
  498. }
  499. if (reset_pin >= 0)
  500. gpio_direction_output(reset_pin, 1); /* De-assert reset */
  501. }
  502. static void sunxi_lcdc_backlight_enable(void)
  503. {
  504. int pin;
  505. /*
  506. * We want to have scanned out at least one frame before enabling the
  507. * backlight to avoid the screen flashing to white when we enable it.
  508. */
  509. mdelay(40);
  510. pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_BL_EN);
  511. if (pin >= 0)
  512. gpio_direction_output(pin, 1);
  513. pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_BL_PWM);
  514. #ifdef SUNXI_PWM_PIN0
  515. if (pin == SUNXI_PWM_PIN0) {
  516. writel(SUNXI_PWM_CTRL_POLARITY0(PWM_ON) |
  517. SUNXI_PWM_CTRL_ENABLE0 |
  518. SUNXI_PWM_CTRL_PRESCALE0(0xf), SUNXI_PWM_CTRL_REG);
  519. writel(SUNXI_PWM_PERIOD_80PCT, SUNXI_PWM_CH0_PERIOD);
  520. sunxi_gpio_set_cfgpin(pin, SUNXI_PWM_MUX);
  521. return;
  522. }
  523. #endif
  524. if (pin >= 0)
  525. gpio_direction_output(pin, PWM_ON);
  526. }
  527. static void sunxi_lcdc_tcon0_mode_set(const struct ctfb_res_modes *mode,
  528. bool for_ext_vga_dac)
  529. {
  530. struct sunxi_lcdc_reg * const lcdc =
  531. (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
  532. struct sunxi_ccm_reg * const ccm =
  533. (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  534. int clk_div, clk_double, pin;
  535. struct display_timing timing;
  536. #if defined CONFIG_MACH_SUN8I && defined CONFIG_VIDEO_LCD_IF_LVDS
  537. for (pin = SUNXI_GPD(18); pin <= SUNXI_GPD(27); pin++) {
  538. #else
  539. for (pin = SUNXI_GPD(0); pin <= SUNXI_GPD(27); pin++) {
  540. #endif
  541. #ifdef CONFIG_VIDEO_LCD_IF_PARALLEL
  542. sunxi_gpio_set_cfgpin(pin, SUNXI_GPD_LCD0);
  543. #endif
  544. #ifdef CONFIG_VIDEO_LCD_IF_LVDS
  545. sunxi_gpio_set_cfgpin(pin, SUNXI_GPD_LVDS0);
  546. #endif
  547. #ifdef CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
  548. sunxi_gpio_set_drv(pin, 3);
  549. #endif
  550. }
  551. lcdc_pll_set(ccm, 0, mode->pixclock_khz, &clk_div, &clk_double,
  552. sunxi_is_composite());
  553. video_ctfb_mode_to_display_timing(mode, &timing);
  554. lcdc_tcon0_mode_set(lcdc, &timing, clk_div, for_ext_vga_dac,
  555. sunxi_display.depth, CONFIG_VIDEO_LCD_DCLK_PHASE);
  556. }
  557. #if defined CONFIG_VIDEO_HDMI || defined CONFIG_VIDEO_VGA || defined CONFIG_VIDEO_COMPOSITE
  558. static void sunxi_lcdc_tcon1_mode_set(const struct ctfb_res_modes *mode,
  559. int *clk_div, int *clk_double,
  560. bool use_portd_hvsync)
  561. {
  562. struct sunxi_lcdc_reg * const lcdc =
  563. (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
  564. struct sunxi_ccm_reg * const ccm =
  565. (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  566. struct display_timing timing;
  567. video_ctfb_mode_to_display_timing(mode, &timing);
  568. lcdc_tcon1_mode_set(lcdc, &timing, use_portd_hvsync,
  569. sunxi_is_composite());
  570. if (use_portd_hvsync) {
  571. sunxi_gpio_set_cfgpin(SUNXI_GPD(26), SUNXI_GPD_LCD0);
  572. sunxi_gpio_set_cfgpin(SUNXI_GPD(27), SUNXI_GPD_LCD0);
  573. }
  574. lcdc_pll_set(ccm, 1, mode->pixclock_khz, clk_div, clk_double,
  575. sunxi_is_composite());
  576. }
  577. #endif /* CONFIG_VIDEO_HDMI || defined CONFIG_VIDEO_VGA || CONFIG_VIDEO_COMPOSITE */
  578. #ifdef CONFIG_VIDEO_HDMI
  579. static void sunxi_hdmi_setup_info_frames(const struct ctfb_res_modes *mode)
  580. {
  581. struct sunxi_hdmi_reg * const hdmi =
  582. (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
  583. u8 checksum = 0;
  584. u8 avi_info_frame[17] = {
  585. 0x82, 0x02, 0x0d, 0x00, 0x12, 0x00, 0x88, 0x00,
  586. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  587. 0x00
  588. };
  589. u8 vendor_info_frame[19] = {
  590. 0x81, 0x01, 0x06, 0x29, 0x03, 0x0c, 0x00, 0x40,
  591. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  592. 0x00, 0x00, 0x00
  593. };
  594. int i;
  595. if (mode->pixclock_khz <= 27000)
  596. avi_info_frame[5] = 0x40; /* SD-modes, ITU601 colorspace */
  597. else
  598. avi_info_frame[5] = 0x80; /* HD-modes, ITU709 colorspace */
  599. if (mode->xres * 100 / mode->yres < 156)
  600. avi_info_frame[5] |= 0x18; /* 4 : 3 */
  601. else
  602. avi_info_frame[5] |= 0x28; /* 16 : 9 */
  603. for (i = 0; i < ARRAY_SIZE(avi_info_frame); i++)
  604. checksum += avi_info_frame[i];
  605. avi_info_frame[3] = 0x100 - checksum;
  606. for (i = 0; i < ARRAY_SIZE(avi_info_frame); i++)
  607. writeb(avi_info_frame[i], &hdmi->avi_info_frame[i]);
  608. writel(SUNXI_HDMI_QCP_PACKET0, &hdmi->qcp_packet0);
  609. writel(SUNXI_HDMI_QCP_PACKET1, &hdmi->qcp_packet1);
  610. for (i = 0; i < ARRAY_SIZE(vendor_info_frame); i++)
  611. writeb(vendor_info_frame[i], &hdmi->vendor_info_frame[i]);
  612. writel(SUNXI_HDMI_PKT_CTRL0, &hdmi->pkt_ctrl0);
  613. writel(SUNXI_HDMI_PKT_CTRL1, &hdmi->pkt_ctrl1);
  614. setbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_HDMI);
  615. }
  616. static void sunxi_hdmi_mode_set(const struct ctfb_res_modes *mode,
  617. int clk_div, int clk_double)
  618. {
  619. struct sunxi_hdmi_reg * const hdmi =
  620. (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
  621. int x, y;
  622. /* Write clear interrupt status bits */
  623. writel(SUNXI_HDMI_IRQ_STATUS_BITS, &hdmi->irq);
  624. if (sunxi_display.monitor == sunxi_monitor_hdmi)
  625. sunxi_hdmi_setup_info_frames(mode);
  626. /* Set input sync enable */
  627. writel(SUNXI_HDMI_UNKNOWN_INPUT_SYNC, &hdmi->unknown);
  628. /* Init various registers, select pll3 as clock source */
  629. writel(SUNXI_HDMI_VIDEO_POL_TX_CLK, &hdmi->video_polarity);
  630. writel(SUNXI_HDMI_PAD_CTRL0_RUN, &hdmi->pad_ctrl0);
  631. writel(SUNXI_HDMI_PAD_CTRL1, &hdmi->pad_ctrl1);
  632. writel(SUNXI_HDMI_PLL_CTRL, &hdmi->pll_ctrl);
  633. writel(SUNXI_HDMI_PLL_DBG0_PLL3, &hdmi->pll_dbg0);
  634. /* Setup clk div and doubler */
  635. clrsetbits_le32(&hdmi->pll_ctrl, SUNXI_HDMI_PLL_CTRL_DIV_MASK,
  636. SUNXI_HDMI_PLL_CTRL_DIV(clk_div));
  637. if (!clk_double)
  638. setbits_le32(&hdmi->pad_ctrl1, SUNXI_HDMI_PAD_CTRL1_HALVE);
  639. /* Setup timing registers */
  640. writel(SUNXI_HDMI_Y(mode->yres) | SUNXI_HDMI_X(mode->xres),
  641. &hdmi->video_size);
  642. x = mode->hsync_len + mode->left_margin;
  643. y = mode->vsync_len + mode->upper_margin;
  644. writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_bp);
  645. x = mode->right_margin;
  646. y = mode->lower_margin;
  647. writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_fp);
  648. x = mode->hsync_len;
  649. y = mode->vsync_len;
  650. writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_spw);
  651. if (mode->sync & FB_SYNC_HOR_HIGH_ACT)
  652. setbits_le32(&hdmi->video_polarity, SUNXI_HDMI_VIDEO_POL_HOR);
  653. if (mode->sync & FB_SYNC_VERT_HIGH_ACT)
  654. setbits_le32(&hdmi->video_polarity, SUNXI_HDMI_VIDEO_POL_VER);
  655. }
  656. static void sunxi_hdmi_enable(void)
  657. {
  658. struct sunxi_hdmi_reg * const hdmi =
  659. (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
  660. udelay(100);
  661. setbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_ENABLE);
  662. }
  663. #endif /* CONFIG_VIDEO_HDMI */
  664. #if defined CONFIG_VIDEO_VGA || defined CONFIG_VIDEO_COMPOSITE
  665. static void sunxi_tvencoder_mode_set(void)
  666. {
  667. struct sunxi_ccm_reg * const ccm =
  668. (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  669. struct sunxi_tve_reg * const tve =
  670. (struct sunxi_tve_reg *)SUNXI_TVE0_BASE;
  671. /* Reset off */
  672. setbits_le32(&ccm->lcd0_ch0_clk_cfg, CCM_LCD_CH0_CTRL_TVE_RST);
  673. /* Clock on */
  674. setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_TVE0);
  675. switch (sunxi_display.monitor) {
  676. case sunxi_monitor_vga:
  677. tvencoder_mode_set(tve, tve_mode_vga);
  678. break;
  679. case sunxi_monitor_composite_pal_nc:
  680. tvencoder_mode_set(tve, tve_mode_composite_pal_nc);
  681. break;
  682. case sunxi_monitor_composite_pal:
  683. tvencoder_mode_set(tve, tve_mode_composite_pal);
  684. break;
  685. case sunxi_monitor_composite_pal_m:
  686. tvencoder_mode_set(tve, tve_mode_composite_pal_m);
  687. break;
  688. case sunxi_monitor_composite_ntsc:
  689. tvencoder_mode_set(tve, tve_mode_composite_ntsc);
  690. break;
  691. case sunxi_monitor_none:
  692. case sunxi_monitor_dvi:
  693. case sunxi_monitor_hdmi:
  694. case sunxi_monitor_lcd:
  695. break;
  696. }
  697. }
  698. #endif /* CONFIG_VIDEO_VGA || defined CONFIG_VIDEO_COMPOSITE */
  699. static void sunxi_drc_init(void)
  700. {
  701. #ifdef CONFIG_SUNXI_GEN_SUN6I
  702. struct sunxi_ccm_reg * const ccm =
  703. (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  704. /* On sun6i the drc must be clocked even when in pass-through mode */
  705. #ifdef CONFIG_MACH_SUN8I_A33
  706. setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_SAT);
  707. #endif
  708. setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DRC0);
  709. clock_set_de_mod_clock(&ccm->iep_drc0_clk_cfg, 300000000);
  710. #endif
  711. }
  712. #ifdef CONFIG_VIDEO_VGA_VIA_LCD
  713. static void sunxi_vga_external_dac_enable(void)
  714. {
  715. int pin;
  716. pin = sunxi_name_to_gpio(CONFIG_VIDEO_VGA_EXTERNAL_DAC_EN);
  717. if (pin >= 0) {
  718. gpio_request(pin, "vga_enable");
  719. gpio_direction_output(pin, 1);
  720. }
  721. }
  722. #endif /* CONFIG_VIDEO_VGA_VIA_LCD */
  723. #ifdef CONFIG_VIDEO_LCD_SSD2828
  724. static int sunxi_ssd2828_init(const struct ctfb_res_modes *mode)
  725. {
  726. struct ssd2828_config cfg = {
  727. .csx_pin = name_to_gpio(CONFIG_VIDEO_LCD_SPI_CS),
  728. .sck_pin = name_to_gpio(CONFIG_VIDEO_LCD_SPI_SCLK),
  729. .sdi_pin = name_to_gpio(CONFIG_VIDEO_LCD_SPI_MOSI),
  730. .sdo_pin = name_to_gpio(CONFIG_VIDEO_LCD_SPI_MISO),
  731. .reset_pin = name_to_gpio(CONFIG_VIDEO_LCD_SSD2828_RESET),
  732. .ssd2828_tx_clk_khz = CONFIG_VIDEO_LCD_SSD2828_TX_CLK * 1000,
  733. .ssd2828_color_depth = 24,
  734. #ifdef CONFIG_VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
  735. .mipi_dsi_number_of_data_lanes = 4,
  736. .mipi_dsi_bitrate_per_data_lane_mbps = 513,
  737. .mipi_dsi_delay_after_exit_sleep_mode_ms = 100,
  738. .mipi_dsi_delay_after_set_display_on_ms = 200
  739. #else
  740. #error MIPI LCD panel needs configuration parameters
  741. #endif
  742. };
  743. if (cfg.csx_pin == -1 || cfg.sck_pin == -1 || cfg.sdi_pin == -1) {
  744. printf("SSD2828: SPI pins are not properly configured\n");
  745. return 1;
  746. }
  747. if (cfg.reset_pin == -1) {
  748. printf("SSD2828: Reset pin is not properly configured\n");
  749. return 1;
  750. }
  751. return ssd2828_init(&cfg, mode);
  752. }
  753. #endif /* CONFIG_VIDEO_LCD_SSD2828 */
  754. static void sunxi_engines_init(void)
  755. {
  756. sunxi_composer_init();
  757. sunxi_lcdc_init();
  758. sunxi_drc_init();
  759. }
  760. static void sunxi_mode_set(const struct ctfb_res_modes *mode,
  761. unsigned int address)
  762. {
  763. int __maybe_unused clk_div, clk_double;
  764. struct sunxi_lcdc_reg * const lcdc =
  765. (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
  766. struct sunxi_tve_reg * __maybe_unused const tve =
  767. (struct sunxi_tve_reg *)SUNXI_TVE0_BASE;
  768. switch (sunxi_display.monitor) {
  769. case sunxi_monitor_none:
  770. break;
  771. case sunxi_monitor_dvi:
  772. case sunxi_monitor_hdmi:
  773. #ifdef CONFIG_VIDEO_HDMI
  774. sunxi_composer_mode_set(mode, address);
  775. sunxi_lcdc_tcon1_mode_set(mode, &clk_div, &clk_double, 0);
  776. sunxi_hdmi_mode_set(mode, clk_div, clk_double);
  777. sunxi_composer_enable();
  778. lcdc_enable(lcdc, sunxi_display.depth);
  779. sunxi_hdmi_enable();
  780. #endif
  781. break;
  782. case sunxi_monitor_lcd:
  783. sunxi_lcdc_panel_enable();
  784. if (IS_ENABLED(CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804)) {
  785. /*
  786. * The anx9804 needs 1.8V from eldo3, we do this here
  787. * and not via CONFIG_AXP_ELDO3_VOLT from board_init()
  788. * to avoid turning this on when using hdmi output.
  789. */
  790. axp_set_eldo(3, 1800);
  791. anx9804_init(CONFIG_VIDEO_LCD_I2C_BUS, 4,
  792. ANX9804_DATA_RATE_1620M,
  793. sunxi_display.depth);
  794. }
  795. if (IS_ENABLED(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM)) {
  796. mdelay(50); /* Wait for lcd controller power on */
  797. hitachi_tx18d42vm_init();
  798. }
  799. if (IS_ENABLED(CONFIG_VIDEO_LCD_TL059WV5C0)) {
  800. unsigned int orig_i2c_bus = i2c_get_bus_num();
  801. i2c_set_bus_num(CONFIG_VIDEO_LCD_I2C_BUS);
  802. i2c_reg_write(0x5c, 0x04, 0x42); /* Turn on the LCD */
  803. i2c_set_bus_num(orig_i2c_bus);
  804. }
  805. sunxi_composer_mode_set(mode, address);
  806. sunxi_lcdc_tcon0_mode_set(mode, false);
  807. sunxi_composer_enable();
  808. lcdc_enable(lcdc, sunxi_display.depth);
  809. #ifdef CONFIG_VIDEO_LCD_SSD2828
  810. sunxi_ssd2828_init(mode);
  811. #endif
  812. sunxi_lcdc_backlight_enable();
  813. break;
  814. case sunxi_monitor_vga:
  815. #ifdef CONFIG_VIDEO_VGA
  816. sunxi_composer_mode_set(mode, address);
  817. sunxi_lcdc_tcon1_mode_set(mode, &clk_div, &clk_double, 1);
  818. sunxi_tvencoder_mode_set();
  819. sunxi_composer_enable();
  820. lcdc_enable(lcdc, sunxi_display.depth);
  821. tvencoder_enable(tve);
  822. #elif defined CONFIG_VIDEO_VGA_VIA_LCD
  823. sunxi_composer_mode_set(mode, address);
  824. sunxi_lcdc_tcon0_mode_set(mode, true);
  825. sunxi_composer_enable();
  826. lcdc_enable(lcdc, sunxi_display.depth);
  827. sunxi_vga_external_dac_enable();
  828. #endif
  829. break;
  830. case sunxi_monitor_composite_pal:
  831. case sunxi_monitor_composite_ntsc:
  832. case sunxi_monitor_composite_pal_m:
  833. case sunxi_monitor_composite_pal_nc:
  834. #ifdef CONFIG_VIDEO_COMPOSITE
  835. sunxi_composer_mode_set(mode, address);
  836. sunxi_lcdc_tcon1_mode_set(mode, &clk_div, &clk_double, 0);
  837. sunxi_tvencoder_mode_set();
  838. sunxi_composer_enable();
  839. lcdc_enable(lcdc, sunxi_display.depth);
  840. tvencoder_enable(tve);
  841. #endif
  842. break;
  843. }
  844. }
  845. static const char *sunxi_get_mon_desc(enum sunxi_monitor monitor)
  846. {
  847. switch (monitor) {
  848. case sunxi_monitor_dvi: return "dvi";
  849. case sunxi_monitor_hdmi: return "hdmi";
  850. case sunxi_monitor_lcd: return "lcd";
  851. case sunxi_monitor_vga: return "vga";
  852. case sunxi_monitor_composite_pal: return "composite-pal";
  853. case sunxi_monitor_composite_ntsc: return "composite-ntsc";
  854. case sunxi_monitor_composite_pal_m: return "composite-pal-m";
  855. case sunxi_monitor_composite_pal_nc: return "composite-pal-nc";
  856. case sunxi_monitor_none: /* fall through */
  857. default: return "none";
  858. }
  859. }
  860. ulong board_get_usable_ram_top(ulong total_size)
  861. {
  862. return gd->ram_top - CONFIG_SUNXI_MAX_FB_SIZE;
  863. }
  864. static bool sunxi_has_hdmi(void)
  865. {
  866. #ifdef CONFIG_VIDEO_HDMI
  867. return true;
  868. #else
  869. return false;
  870. #endif
  871. }
  872. static bool sunxi_has_lcd(void)
  873. {
  874. char *lcd_mode = CONFIG_VIDEO_LCD_MODE;
  875. return lcd_mode[0] != 0;
  876. }
  877. static bool sunxi_has_vga(void)
  878. {
  879. #if defined CONFIG_VIDEO_VGA || defined CONFIG_VIDEO_VGA_VIA_LCD
  880. return true;
  881. #else
  882. return false;
  883. #endif
  884. }
  885. static bool sunxi_has_composite(void)
  886. {
  887. #ifdef CONFIG_VIDEO_COMPOSITE
  888. return true;
  889. #else
  890. return false;
  891. #endif
  892. }
  893. static enum sunxi_monitor sunxi_get_default_mon(bool allow_hdmi)
  894. {
  895. if (allow_hdmi && sunxi_has_hdmi())
  896. return sunxi_monitor_dvi;
  897. else if (sunxi_has_lcd())
  898. return sunxi_monitor_lcd;
  899. else if (sunxi_has_vga())
  900. return sunxi_monitor_vga;
  901. else if (sunxi_has_composite())
  902. return sunxi_monitor_composite_pal;
  903. else
  904. return sunxi_monitor_none;
  905. }
  906. void *video_hw_init(void)
  907. {
  908. static GraphicDevice *graphic_device = &sunxi_display.graphic_device;
  909. const struct ctfb_res_modes *mode;
  910. struct ctfb_res_modes custom;
  911. const char *options;
  912. #ifdef CONFIG_VIDEO_HDMI
  913. int hpd, hpd_delay, edid;
  914. bool hdmi_present;
  915. #endif
  916. int i, overscan_offset, overscan_x, overscan_y;
  917. unsigned int fb_dma_addr;
  918. char mon[16];
  919. char *lcd_mode = CONFIG_VIDEO_LCD_MODE;
  920. memset(&sunxi_display, 0, sizeof(struct sunxi_display));
  921. video_get_ctfb_res_modes(RES_MODE_1024x768, 24, &mode,
  922. &sunxi_display.depth, &options);
  923. #ifdef CONFIG_VIDEO_HDMI
  924. hpd = video_get_option_int(options, "hpd", 1);
  925. hpd_delay = video_get_option_int(options, "hpd_delay", 500);
  926. edid = video_get_option_int(options, "edid", 1);
  927. #endif
  928. overscan_x = video_get_option_int(options, "overscan_x", -1);
  929. overscan_y = video_get_option_int(options, "overscan_y", -1);
  930. sunxi_display.monitor = sunxi_get_default_mon(true);
  931. video_get_option_string(options, "monitor", mon, sizeof(mon),
  932. sunxi_get_mon_desc(sunxi_display.monitor));
  933. for (i = 0; i <= SUNXI_MONITOR_LAST; i++) {
  934. if (strcmp(mon, sunxi_get_mon_desc(i)) == 0) {
  935. sunxi_display.monitor = i;
  936. break;
  937. }
  938. }
  939. if (i > SUNXI_MONITOR_LAST)
  940. printf("Unknown monitor: '%s', falling back to '%s'\n",
  941. mon, sunxi_get_mon_desc(sunxi_display.monitor));
  942. #ifdef CONFIG_VIDEO_HDMI
  943. /* If HDMI/DVI is selected do HPD & EDID, and handle fallback */
  944. if (sunxi_display.monitor == sunxi_monitor_dvi ||
  945. sunxi_display.monitor == sunxi_monitor_hdmi) {
  946. /* Always call hdp_detect, as it also enables clocks, etc. */
  947. hdmi_present = (sunxi_hdmi_hpd_detect(hpd_delay) == 1);
  948. if (hdmi_present && edid) {
  949. printf("HDMI connected: ");
  950. if (sunxi_hdmi_edid_get_mode(&custom, true) == 0)
  951. mode = &custom;
  952. else
  953. hdmi_present = false;
  954. }
  955. /* Fall back to EDID in case HPD failed */
  956. if (edid && !hdmi_present) {
  957. if (sunxi_hdmi_edid_get_mode(&custom, false) == 0) {
  958. mode = &custom;
  959. hdmi_present = true;
  960. }
  961. }
  962. /* Shut down when display was not found */
  963. if ((hpd || edid) && !hdmi_present) {
  964. sunxi_hdmi_shutdown();
  965. sunxi_display.monitor = sunxi_get_default_mon(false);
  966. } /* else continue with hdmi/dvi without a cable connected */
  967. }
  968. #endif
  969. switch (sunxi_display.monitor) {
  970. case sunxi_monitor_none:
  971. return NULL;
  972. case sunxi_monitor_dvi:
  973. case sunxi_monitor_hdmi:
  974. if (!sunxi_has_hdmi()) {
  975. printf("HDMI/DVI not supported on this board\n");
  976. sunxi_display.monitor = sunxi_monitor_none;
  977. return NULL;
  978. }
  979. break;
  980. case sunxi_monitor_lcd:
  981. if (!sunxi_has_lcd()) {
  982. printf("LCD not supported on this board\n");
  983. sunxi_display.monitor = sunxi_monitor_none;
  984. return NULL;
  985. }
  986. sunxi_display.depth = video_get_params(&custom, lcd_mode);
  987. mode = &custom;
  988. break;
  989. case sunxi_monitor_vga:
  990. if (!sunxi_has_vga()) {
  991. printf("VGA not supported on this board\n");
  992. sunxi_display.monitor = sunxi_monitor_none;
  993. return NULL;
  994. }
  995. sunxi_display.depth = 18;
  996. break;
  997. case sunxi_monitor_composite_pal:
  998. case sunxi_monitor_composite_ntsc:
  999. case sunxi_monitor_composite_pal_m:
  1000. case sunxi_monitor_composite_pal_nc:
  1001. if (!sunxi_has_composite()) {
  1002. printf("Composite video not supported on this board\n");
  1003. sunxi_display.monitor = sunxi_monitor_none;
  1004. return NULL;
  1005. }
  1006. if (sunxi_display.monitor == sunxi_monitor_composite_pal ||
  1007. sunxi_display.monitor == sunxi_monitor_composite_pal_nc)
  1008. mode = &composite_video_modes[0];
  1009. else
  1010. mode = &composite_video_modes[1];
  1011. sunxi_display.depth = 24;
  1012. break;
  1013. }
  1014. /* Yes these defaults are quite high, overscan on composite sucks... */
  1015. if (overscan_x == -1)
  1016. overscan_x = sunxi_is_composite() ? 32 : 0;
  1017. if (overscan_y == -1)
  1018. overscan_y = sunxi_is_composite() ? 20 : 0;
  1019. sunxi_display.fb_size =
  1020. (mode->xres * mode->yres * 4 + 0xfff) & ~0xfff;
  1021. overscan_offset = (overscan_y * mode->xres + overscan_x) * 4;
  1022. /* We want to keep the fb_base for simplefb page aligned, where as
  1023. * the sunxi dma engines will happily accept an unaligned address. */
  1024. if (overscan_offset)
  1025. sunxi_display.fb_size += 0x1000;
  1026. if (sunxi_display.fb_size > CONFIG_SUNXI_MAX_FB_SIZE) {
  1027. printf("Error need %dkB for fb, but only %dkB is reserved\n",
  1028. sunxi_display.fb_size >> 10,
  1029. CONFIG_SUNXI_MAX_FB_SIZE >> 10);
  1030. return NULL;
  1031. }
  1032. printf("Setting up a %dx%d%s %s console (overscan %dx%d)\n",
  1033. mode->xres, mode->yres,
  1034. (mode->vmode == FB_VMODE_INTERLACED) ? "i" : "",
  1035. sunxi_get_mon_desc(sunxi_display.monitor),
  1036. overscan_x, overscan_y);
  1037. gd->fb_base = gd->bd->bi_dram[0].start +
  1038. gd->bd->bi_dram[0].size - sunxi_display.fb_size;
  1039. sunxi_engines_init();
  1040. #ifdef CONFIG_EFI_LOADER
  1041. efi_add_memory_map(gd->fb_base, sunxi_display.fb_size,
  1042. EFI_RESERVED_MEMORY_TYPE);
  1043. #endif
  1044. fb_dma_addr = gd->fb_base - CONFIG_SYS_SDRAM_BASE;
  1045. sunxi_display.fb_addr = gd->fb_base;
  1046. if (overscan_offset) {
  1047. fb_dma_addr += 0x1000 - (overscan_offset & 0xfff);
  1048. sunxi_display.fb_addr += (overscan_offset + 0xfff) & ~0xfff;
  1049. memset((void *)gd->fb_base, 0, sunxi_display.fb_size);
  1050. flush_cache(gd->fb_base, sunxi_display.fb_size);
  1051. }
  1052. sunxi_mode_set(mode, fb_dma_addr);
  1053. /*
  1054. * These are the only members of this structure that are used. All the
  1055. * others are driver specific. The pitch is stored in plnSizeX.
  1056. */
  1057. graphic_device->frameAdrs = sunxi_display.fb_addr;
  1058. graphic_device->gdfIndex = GDF_32BIT_X888RGB;
  1059. graphic_device->gdfBytesPP = 4;
  1060. graphic_device->winSizeX = mode->xres - 2 * overscan_x;
  1061. graphic_device->winSizeY = mode->yres - 2 * overscan_y;
  1062. graphic_device->plnSizeX = mode->xres * graphic_device->gdfBytesPP;
  1063. return graphic_device;
  1064. }
  1065. /*
  1066. * Simplefb support.
  1067. */
  1068. #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_VIDEO_DT_SIMPLEFB)
  1069. int sunxi_simplefb_setup(void *blob)
  1070. {
  1071. static GraphicDevice *graphic_device = &sunxi_display.graphic_device;
  1072. int offset, ret;
  1073. u64 start, size;
  1074. const char *pipeline = NULL;
  1075. #ifdef CONFIG_MACH_SUN4I
  1076. #define PIPELINE_PREFIX "de_fe0-"
  1077. #else
  1078. #define PIPELINE_PREFIX
  1079. #endif
  1080. switch (sunxi_display.monitor) {
  1081. case sunxi_monitor_none:
  1082. return 0;
  1083. case sunxi_monitor_dvi:
  1084. case sunxi_monitor_hdmi:
  1085. pipeline = PIPELINE_PREFIX "de_be0-lcd0-hdmi";
  1086. break;
  1087. case sunxi_monitor_lcd:
  1088. pipeline = PIPELINE_PREFIX "de_be0-lcd0";
  1089. break;
  1090. case sunxi_monitor_vga:
  1091. #ifdef CONFIG_VIDEO_VGA
  1092. pipeline = PIPELINE_PREFIX "de_be0-lcd0-tve0";
  1093. #elif defined CONFIG_VIDEO_VGA_VIA_LCD
  1094. pipeline = PIPELINE_PREFIX "de_be0-lcd0";
  1095. #endif
  1096. break;
  1097. case sunxi_monitor_composite_pal:
  1098. case sunxi_monitor_composite_ntsc:
  1099. case sunxi_monitor_composite_pal_m:
  1100. case sunxi_monitor_composite_pal_nc:
  1101. pipeline = PIPELINE_PREFIX "de_be0-lcd0-tve0";
  1102. break;
  1103. }
  1104. offset = sunxi_simplefb_fdt_match(blob, pipeline);
  1105. if (offset < 0) {
  1106. eprintf("Cannot setup simplefb: node not found\n");
  1107. return 0; /* Keep older kernels working */
  1108. }
  1109. /*
  1110. * Do not report the framebuffer as free RAM to the OS, note we cannot
  1111. * use fdt_add_mem_rsv() here, because then it is still seen as RAM,
  1112. * and e.g. Linux refuses to iomap RAM on ARM, see:
  1113. * linux/arch/arm/mm/ioremap.c around line 301.
  1114. */
  1115. start = gd->bd->bi_dram[0].start;
  1116. size = gd->bd->bi_dram[0].size - sunxi_display.fb_size;
  1117. ret = fdt_fixup_memory_banks(blob, &start, &size, 1);
  1118. if (ret) {
  1119. eprintf("Cannot setup simplefb: Error reserving memory\n");
  1120. return ret;
  1121. }
  1122. ret = fdt_setup_simplefb_node(blob, offset, sunxi_display.fb_addr,
  1123. graphic_device->winSizeX, graphic_device->winSizeY,
  1124. graphic_device->plnSizeX, "x8r8g8b8");
  1125. if (ret)
  1126. eprintf("Cannot setup simplefb: Error setting properties\n");
  1127. return ret;
  1128. }
  1129. #endif /* CONFIG_OF_BOARD_SETUP && CONFIG_VIDEO_DT_SIMPLEFB */