ssd2828.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) 2015 Siarhei Siamashka <siarhei.siamashka@gmail.com>
  4. */
  5. /*
  6. * Support for the SSD2828 bridge chip, which can take pixel data coming
  7. * from a parallel LCD interface and translate it on the flight into MIPI DSI
  8. * interface for driving a MIPI compatible TFT display.
  9. */
  10. #include <common.h>
  11. #include <malloc.h>
  12. #include <mipi_display.h>
  13. #include <asm/arch/gpio.h>
  14. #include <asm/gpio.h>
  15. #include <linux/delay.h>
  16. #include "videomodes.h"
  17. #include "ssd2828.h"
  18. #define SSD2828_DIR 0xB0
  19. #define SSD2828_VICR1 0xB1
  20. #define SSD2828_VICR2 0xB2
  21. #define SSD2828_VICR3 0xB3
  22. #define SSD2828_VICR4 0xB4
  23. #define SSD2828_VICR5 0xB5
  24. #define SSD2828_VICR6 0xB6
  25. #define SSD2828_CFGR 0xB7
  26. #define SSD2828_VCR 0xB8
  27. #define SSD2828_PCR 0xB9
  28. #define SSD2828_PLCR 0xBA
  29. #define SSD2828_CCR 0xBB
  30. #define SSD2828_PSCR1 0xBC
  31. #define SSD2828_PSCR2 0xBD
  32. #define SSD2828_PSCR3 0xBE
  33. #define SSD2828_PDR 0xBF
  34. #define SSD2828_OCR 0xC0
  35. #define SSD2828_MRSR 0xC1
  36. #define SSD2828_RDCR 0xC2
  37. #define SSD2828_ARSR 0xC3
  38. #define SSD2828_LCR 0xC4
  39. #define SSD2828_ICR 0xC5
  40. #define SSD2828_ISR 0xC6
  41. #define SSD2828_ESR 0xC7
  42. #define SSD2828_DAR1 0xC9
  43. #define SSD2828_DAR2 0xCA
  44. #define SSD2828_DAR3 0xCB
  45. #define SSD2828_DAR4 0xCC
  46. #define SSD2828_DAR5 0xCD
  47. #define SSD2828_DAR6 0xCE
  48. #define SSD2828_HTTR1 0xCF
  49. #define SSD2828_HTTR2 0xD0
  50. #define SSD2828_LRTR1 0xD1
  51. #define SSD2828_LRTR2 0xD2
  52. #define SSD2828_TSR 0xD3
  53. #define SSD2828_LRR 0xD4
  54. #define SSD2828_PLLR 0xD5
  55. #define SSD2828_TR 0xD6
  56. #define SSD2828_TECR 0xD7
  57. #define SSD2828_ACR1 0xD8
  58. #define SSD2828_ACR2 0xD9
  59. #define SSD2828_ACR3 0xDA
  60. #define SSD2828_ACR4 0xDB
  61. #define SSD2828_IOCR 0xDC
  62. #define SSD2828_VICR7 0xDD
  63. #define SSD2828_LCFR 0xDE
  64. #define SSD2828_DAR7 0xDF
  65. #define SSD2828_PUCR1 0xE0
  66. #define SSD2828_PUCR2 0xE1
  67. #define SSD2828_PUCR3 0xE2
  68. #define SSD2828_CBCR1 0xE9
  69. #define SSD2828_CBCR2 0xEA
  70. #define SSD2828_CBSR 0xEB
  71. #define SSD2828_ECR 0xEC
  72. #define SSD2828_VSDR 0xED
  73. #define SSD2828_TMR 0xEE
  74. #define SSD2828_GPIO1 0xEF
  75. #define SSD2828_GPIO2 0xF0
  76. #define SSD2828_DLYA01 0xF1
  77. #define SSD2828_DLYA23 0xF2
  78. #define SSD2828_DLYB01 0xF3
  79. #define SSD2828_DLYB23 0xF4
  80. #define SSD2828_DLYC01 0xF5
  81. #define SSD2828_DLYC23 0xF6
  82. #define SSD2828_ACR5 0xF7
  83. #define SSD2828_RR 0xFF
  84. #define SSD2828_CFGR_HS (1 << 0)
  85. #define SSD2828_CFGR_CKE (1 << 1)
  86. #define SSD2828_CFGR_SLP (1 << 2)
  87. #define SSD2828_CFGR_VEN (1 << 3)
  88. #define SSD2828_CFGR_HCLK (1 << 4)
  89. #define SSD2828_CFGR_CSS (1 << 5)
  90. #define SSD2828_CFGR_DCS (1 << 6)
  91. #define SSD2828_CFGR_REN (1 << 7)
  92. #define SSD2828_CFGR_ECD (1 << 8)
  93. #define SSD2828_CFGR_EOT (1 << 9)
  94. #define SSD2828_CFGR_LPE (1 << 10)
  95. #define SSD2828_CFGR_TXD (1 << 11)
  96. #define SSD2828_VIDEO_MODE_NON_BURST_WITH_SYNC_PULSES (0 << 2)
  97. #define SSD2828_VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (1 << 2)
  98. #define SSD2828_VIDEO_MODE_BURST (2 << 2)
  99. #define SSD2828_VIDEO_PIXEL_FORMAT_16BPP 0
  100. #define SSD2828_VIDEO_PIXEL_FORMAT_18BPP_PACKED 1
  101. #define SSD2828_VIDEO_PIXEL_FORMAT_18BPP_LOOSELY_PACKED 2
  102. #define SSD2828_VIDEO_PIXEL_FORMAT_24BPP 3
  103. #define SSD2828_LP_CLOCK_DIVIDER(n) (((n) - 1) & 0x3F)
  104. /*
  105. * SPI transfer, using the "24-bit 3 wire" mode (that's how it is called in
  106. * the SSD2828 documentation). The 'dout' input parameter specifies 24-bits
  107. * of data to be written to SSD2828. Returns the lowest 16-bits of data,
  108. * that is received back.
  109. */
  110. static u32 soft_spi_xfer_24bit_3wire(const struct ssd2828_config *drv, u32 dout)
  111. {
  112. int j, bitlen = 24;
  113. u32 tmpdin = 0;
  114. /*
  115. * According to the "24 Bit 3 Wire SPI Interface Timing Characteristics"
  116. * and "TX_CLK Timing Characteristics" tables in the SSD2828 datasheet,
  117. * the lowest possible 'tx_clk' clock frequency is 8MHz, and SPI runs
  118. * at 1/8 of that after reset. So using 1 microsecond delays is safe in
  119. * the main loop. But the delays around chip select pin manipulations
  120. * need to be longer (up to 16 'tx_clk' cycles, or 2 microseconds in
  121. * the worst case).
  122. */
  123. const int spi_delay_us = 1;
  124. const int spi_cs_delay_us = 2;
  125. gpio_set_value(drv->csx_pin, 0);
  126. udelay(spi_cs_delay_us);
  127. for (j = bitlen - 1; j >= 0; j--) {
  128. gpio_set_value(drv->sck_pin, 0);
  129. gpio_set_value(drv->sdi_pin, (dout & (1 << j)) != 0);
  130. udelay(spi_delay_us);
  131. if (drv->sdo_pin != -1)
  132. tmpdin = (tmpdin << 1) | gpio_get_value(drv->sdo_pin);
  133. gpio_set_value(drv->sck_pin, 1);
  134. udelay(spi_delay_us);
  135. }
  136. udelay(spi_cs_delay_us);
  137. gpio_set_value(drv->csx_pin, 1);
  138. udelay(spi_cs_delay_us);
  139. return tmpdin & 0xFFFF;
  140. }
  141. /*
  142. * Read from a SSD2828 hardware register (regnum >= 0xB0)
  143. */
  144. static u32 read_hw_register(const struct ssd2828_config *cfg, u8 regnum)
  145. {
  146. soft_spi_xfer_24bit_3wire(cfg, 0x700000 | regnum);
  147. return soft_spi_xfer_24bit_3wire(cfg, 0x730000);
  148. }
  149. /*
  150. * Write to a SSD2828 hardware register (regnum >= 0xB0)
  151. */
  152. static void write_hw_register(const struct ssd2828_config *cfg, u8 regnum,
  153. u16 val)
  154. {
  155. soft_spi_xfer_24bit_3wire(cfg, 0x700000 | regnum);
  156. soft_spi_xfer_24bit_3wire(cfg, 0x720000 | val);
  157. }
  158. /*
  159. * Send MIPI command to the LCD panel (cmdnum < 0xB0)
  160. */
  161. static void send_mipi_dcs_command(const struct ssd2828_config *cfg, u8 cmdnum)
  162. {
  163. /* Set packet size to 1 (a single command with no parameters) */
  164. write_hw_register(cfg, SSD2828_PSCR1, 1);
  165. /* Send the command */
  166. write_hw_register(cfg, SSD2828_PDR, cmdnum);
  167. }
  168. /*
  169. * Reset SSD2828
  170. */
  171. static void ssd2828_reset(const struct ssd2828_config *cfg)
  172. {
  173. /* RESET needs 10 milliseconds according to the datasheet */
  174. gpio_set_value(cfg->reset_pin, 0);
  175. mdelay(10);
  176. gpio_set_value(cfg->reset_pin, 1);
  177. mdelay(10);
  178. }
  179. static int ssd2828_enable_gpio(const struct ssd2828_config *cfg)
  180. {
  181. if (gpio_request(cfg->csx_pin, "ssd2828_csx")) {
  182. printf("SSD2828: request for 'ssd2828_csx' pin failed\n");
  183. return 1;
  184. }
  185. if (gpio_request(cfg->sck_pin, "ssd2828_sck")) {
  186. gpio_free(cfg->csx_pin);
  187. printf("SSD2828: request for 'ssd2828_sck' pin failed\n");
  188. return 1;
  189. }
  190. if (gpio_request(cfg->sdi_pin, "ssd2828_sdi")) {
  191. gpio_free(cfg->csx_pin);
  192. gpio_free(cfg->sck_pin);
  193. printf("SSD2828: request for 'ssd2828_sdi' pin failed\n");
  194. return 1;
  195. }
  196. if (gpio_request(cfg->reset_pin, "ssd2828_reset")) {
  197. gpio_free(cfg->csx_pin);
  198. gpio_free(cfg->sck_pin);
  199. gpio_free(cfg->sdi_pin);
  200. printf("SSD2828: request for 'ssd2828_reset' pin failed\n");
  201. return 1;
  202. }
  203. if (cfg->sdo_pin != -1 && gpio_request(cfg->sdo_pin, "ssd2828_sdo")) {
  204. gpio_free(cfg->csx_pin);
  205. gpio_free(cfg->sck_pin);
  206. gpio_free(cfg->sdi_pin);
  207. gpio_free(cfg->reset_pin);
  208. printf("SSD2828: request for 'ssd2828_sdo' pin failed\n");
  209. return 1;
  210. }
  211. gpio_direction_output(cfg->reset_pin, 0);
  212. gpio_direction_output(cfg->csx_pin, 1);
  213. gpio_direction_output(cfg->sck_pin, 1);
  214. gpio_direction_output(cfg->sdi_pin, 1);
  215. if (cfg->sdo_pin != -1)
  216. gpio_direction_input(cfg->sdo_pin);
  217. return 0;
  218. }
  219. static int ssd2828_free_gpio(const struct ssd2828_config *cfg)
  220. {
  221. gpio_free(cfg->csx_pin);
  222. gpio_free(cfg->sck_pin);
  223. gpio_free(cfg->sdi_pin);
  224. gpio_free(cfg->reset_pin);
  225. if (cfg->sdo_pin != -1)
  226. gpio_free(cfg->sdo_pin);
  227. return 1;
  228. }
  229. /*
  230. * PLL configuration register settings.
  231. *
  232. * See the "PLL Configuration Register Description" in the SSD2828 datasheet.
  233. */
  234. static u32 construct_pll_config(u32 desired_pll_freq_kbps,
  235. u32 reference_freq_khz)
  236. {
  237. u32 div_factor = 1, mul_factor, fr = 0;
  238. u32 output_freq_kbps;
  239. /* The intermediate clock after division can't be less than 5MHz */
  240. while (reference_freq_khz / (div_factor + 1) >= 5000)
  241. div_factor++;
  242. if (div_factor > 31)
  243. div_factor = 31;
  244. mul_factor = DIV_ROUND_UP(desired_pll_freq_kbps * div_factor,
  245. reference_freq_khz);
  246. output_freq_kbps = reference_freq_khz * mul_factor / div_factor;
  247. if (output_freq_kbps >= 501000)
  248. fr = 3;
  249. else if (output_freq_kbps >= 251000)
  250. fr = 2;
  251. else if (output_freq_kbps >= 126000)
  252. fr = 1;
  253. return (fr << 14) | (div_factor << 8) | mul_factor;
  254. }
  255. static u32 decode_pll_config(u32 pll_config, u32 reference_freq_khz)
  256. {
  257. u32 mul_factor = pll_config & 0xFF;
  258. u32 div_factor = (pll_config >> 8) & 0x1F;
  259. if (mul_factor == 0)
  260. mul_factor = 1;
  261. if (div_factor == 0)
  262. div_factor = 1;
  263. return reference_freq_khz * mul_factor / div_factor;
  264. }
  265. static int ssd2828_configure_video_interface(const struct ssd2828_config *cfg,
  266. const struct ctfb_res_modes *mode)
  267. {
  268. u32 val;
  269. /* RGB Interface Control Register 1 */
  270. write_hw_register(cfg, SSD2828_VICR1, (mode->vsync_len << 8) |
  271. (mode->hsync_len));
  272. /* RGB Interface Control Register 2 */
  273. u32 vbp = mode->vsync_len + mode->upper_margin;
  274. u32 hbp = mode->hsync_len + mode->left_margin;
  275. write_hw_register(cfg, SSD2828_VICR2, (vbp << 8) | hbp);
  276. /* RGB Interface Control Register 3 */
  277. write_hw_register(cfg, SSD2828_VICR3, (mode->lower_margin << 8) |
  278. (mode->right_margin));
  279. /* RGB Interface Control Register 4 */
  280. write_hw_register(cfg, SSD2828_VICR4, mode->xres);
  281. /* RGB Interface Control Register 5 */
  282. write_hw_register(cfg, SSD2828_VICR5, mode->yres);
  283. /* RGB Interface Control Register 6 */
  284. val = SSD2828_VIDEO_MODE_BURST;
  285. switch (cfg->ssd2828_color_depth) {
  286. case 16:
  287. val |= SSD2828_VIDEO_PIXEL_FORMAT_16BPP;
  288. break;
  289. case 18:
  290. val |= cfg->mipi_dsi_loosely_packed_pixel_format ?
  291. SSD2828_VIDEO_PIXEL_FORMAT_18BPP_LOOSELY_PACKED :
  292. SSD2828_VIDEO_PIXEL_FORMAT_18BPP_PACKED;
  293. break;
  294. case 24:
  295. val |= SSD2828_VIDEO_PIXEL_FORMAT_24BPP;
  296. break;
  297. default:
  298. printf("SSD2828: unsupported color depth\n");
  299. return 1;
  300. }
  301. write_hw_register(cfg, SSD2828_VICR6, val);
  302. /* Lane Configuration Register */
  303. write_hw_register(cfg, SSD2828_LCFR,
  304. cfg->mipi_dsi_number_of_data_lanes - 1);
  305. return 0;
  306. }
  307. int ssd2828_init(const struct ssd2828_config *cfg,
  308. const struct ctfb_res_modes *mode)
  309. {
  310. u32 lp_div, pll_freq_kbps, reference_freq_khz, pll_config;
  311. /* The LP clock speed is limited by 10MHz */
  312. const u32 mipi_dsi_low_power_clk_khz = 10000;
  313. /*
  314. * This is just the reset default value of CFGR register (0x301).
  315. * Because we are not always able to read back from SPI, have
  316. * it initialized here.
  317. */
  318. u32 cfgr_reg = SSD2828_CFGR_EOT | /* EOT Packet Enable */
  319. SSD2828_CFGR_ECD | /* Disable ECC and CRC */
  320. SSD2828_CFGR_HS; /* Data lanes are in HS mode */
  321. /* Initialize the pins */
  322. if (ssd2828_enable_gpio(cfg) != 0)
  323. return 1;
  324. /* Reset the chip */
  325. ssd2828_reset(cfg);
  326. /*
  327. * If there is a pin to read data back from SPI, then we are lucky. Try
  328. * to check if SPI is configured correctly and SSD2828 is actually able
  329. * to talk back.
  330. */
  331. if (cfg->sdo_pin != -1) {
  332. if (read_hw_register(cfg, SSD2828_DIR) != 0x2828 ||
  333. read_hw_register(cfg, SSD2828_CFGR) != cfgr_reg) {
  334. printf("SSD2828: SPI communication failed.\n");
  335. ssd2828_free_gpio(cfg);
  336. return 1;
  337. }
  338. }
  339. /*
  340. * Pick the reference clock for PLL. If we know the exact 'tx_clk'
  341. * clock speed, then everything is good. If not, then we can fallback
  342. * to 'pclk' (pixel clock from the parallel LCD interface). In the
  343. * case of using this fallback, it is necessary to have parallel LCD
  344. * already initialized and running at this point.
  345. */
  346. reference_freq_khz = cfg->ssd2828_tx_clk_khz;
  347. if (reference_freq_khz == 0) {
  348. reference_freq_khz = mode->pixclock_khz;
  349. /* Use 'pclk' as the reference clock for PLL */
  350. cfgr_reg |= SSD2828_CFGR_CSS;
  351. }
  352. /*
  353. * Setup the parallel LCD timings in the appropriate registers.
  354. */
  355. if (ssd2828_configure_video_interface(cfg, mode) != 0) {
  356. ssd2828_free_gpio(cfg);
  357. return 1;
  358. }
  359. /* Configuration Register */
  360. cfgr_reg &= ~SSD2828_CFGR_HS; /* Data lanes are in LP mode */
  361. cfgr_reg |= SSD2828_CFGR_CKE; /* Clock lane is in HS mode */
  362. cfgr_reg |= SSD2828_CFGR_DCS; /* Only use DCS packets */
  363. write_hw_register(cfg, SSD2828_CFGR, cfgr_reg);
  364. /* PLL Configuration Register */
  365. pll_config = construct_pll_config(
  366. cfg->mipi_dsi_bitrate_per_data_lane_mbps * 1000,
  367. reference_freq_khz);
  368. write_hw_register(cfg, SSD2828_PLCR, pll_config);
  369. pll_freq_kbps = decode_pll_config(pll_config, reference_freq_khz);
  370. lp_div = DIV_ROUND_UP(pll_freq_kbps, mipi_dsi_low_power_clk_khz * 8);
  371. /* VC Control Register */
  372. write_hw_register(cfg, SSD2828_VCR, 0);
  373. /* Clock Control Register */
  374. write_hw_register(cfg, SSD2828_CCR, SSD2828_LP_CLOCK_DIVIDER(lp_div));
  375. /* PLL Control Register */
  376. write_hw_register(cfg, SSD2828_PCR, 1); /* Enable PLL */
  377. /* Wait for PLL lock */
  378. udelay(500);
  379. send_mipi_dcs_command(cfg, MIPI_DCS_EXIT_SLEEP_MODE);
  380. mdelay(cfg->mipi_dsi_delay_after_exit_sleep_mode_ms);
  381. send_mipi_dcs_command(cfg, MIPI_DCS_SET_DISPLAY_ON);
  382. mdelay(cfg->mipi_dsi_delay_after_set_display_on_ms);
  383. cfgr_reg |= SSD2828_CFGR_HS; /* Enable HS mode for data lanes */
  384. cfgr_reg |= SSD2828_CFGR_VEN; /* Enable video pipeline */
  385. write_hw_register(cfg, SSD2828_CFGR, cfgr_reg);
  386. return 0;
  387. }