rk_vop.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2015 Google, Inc
  4. * Copyright 2014 Rockchip Inc.
  5. */
  6. #include <common.h>
  7. #include <clk.h>
  8. #include <display.h>
  9. #include <dm.h>
  10. #include <edid.h>
  11. #include <log.h>
  12. #include <regmap.h>
  13. #include <syscon.h>
  14. #include <video.h>
  15. #include <asm/gpio.h>
  16. #include <asm/io.h>
  17. #include <asm/arch-rockchip/clock.h>
  18. #include <asm/arch-rockchip/edp_rk3288.h>
  19. #include <asm/arch-rockchip/vop_rk3288.h>
  20. #include <dm/device-internal.h>
  21. #include <dm/uclass-internal.h>
  22. #include <linux/bitops.h>
  23. #include <linux/err.h>
  24. #include <power/regulator.h>
  25. #include "rk_vop.h"
  26. DECLARE_GLOBAL_DATA_PTR;
  27. enum vop_pol {
  28. HSYNC_POSITIVE = 0,
  29. VSYNC_POSITIVE = 1,
  30. DEN_NEGATIVE = 2,
  31. DCLK_INVERT = 3
  32. };
  33. static void rkvop_enable(struct rk3288_vop *regs, ulong fbbase,
  34. int fb_bits_per_pixel,
  35. const struct display_timing *edid)
  36. {
  37. u32 lb_mode;
  38. u32 rgb_mode;
  39. u32 hactive = edid->hactive.typ;
  40. u32 vactive = edid->vactive.typ;
  41. writel(V_ACT_WIDTH(hactive - 1) | V_ACT_HEIGHT(vactive - 1),
  42. &regs->win0_act_info);
  43. writel(V_DSP_XST(edid->hsync_len.typ + edid->hback_porch.typ) |
  44. V_DSP_YST(edid->vsync_len.typ + edid->vback_porch.typ),
  45. &regs->win0_dsp_st);
  46. writel(V_DSP_WIDTH(hactive - 1) |
  47. V_DSP_HEIGHT(vactive - 1),
  48. &regs->win0_dsp_info);
  49. clrsetbits_le32(&regs->win0_color_key, M_WIN0_KEY_EN | M_WIN0_KEY_COLOR,
  50. V_WIN0_KEY_EN(0) | V_WIN0_KEY_COLOR(0));
  51. switch (fb_bits_per_pixel) {
  52. case 16:
  53. rgb_mode = RGB565;
  54. writel(V_RGB565_VIRWIDTH(hactive), &regs->win0_vir);
  55. break;
  56. case 24:
  57. rgb_mode = RGB888;
  58. writel(V_RGB888_VIRWIDTH(hactive), &regs->win0_vir);
  59. break;
  60. case 32:
  61. default:
  62. rgb_mode = ARGB8888;
  63. writel(V_ARGB888_VIRWIDTH(hactive), &regs->win0_vir);
  64. break;
  65. }
  66. if (hactive > 2560)
  67. lb_mode = LB_RGB_3840X2;
  68. else if (hactive > 1920)
  69. lb_mode = LB_RGB_2560X4;
  70. else if (hactive > 1280)
  71. lb_mode = LB_RGB_1920X5;
  72. else
  73. lb_mode = LB_RGB_1280X8;
  74. clrsetbits_le32(&regs->win0_ctrl0,
  75. M_WIN0_LB_MODE | M_WIN0_DATA_FMT | M_WIN0_EN,
  76. V_WIN0_LB_MODE(lb_mode) | V_WIN0_DATA_FMT(rgb_mode) |
  77. V_WIN0_EN(1));
  78. writel(fbbase, &regs->win0_yrgb_mst);
  79. writel(0x01, &regs->reg_cfg_done); /* enable reg config */
  80. }
  81. static void rkvop_set_pin_polarity(struct udevice *dev,
  82. enum vop_modes mode, u32 polarity)
  83. {
  84. struct rkvop_driverdata *ops =
  85. (struct rkvop_driverdata *)dev_get_driver_data(dev);
  86. if (ops->set_pin_polarity)
  87. ops->set_pin_polarity(dev, mode, polarity);
  88. }
  89. static void rkvop_enable_output(struct udevice *dev, enum vop_modes mode)
  90. {
  91. struct rk_vop_priv *priv = dev_get_priv(dev);
  92. struct rk3288_vop *regs = priv->regs;
  93. /* remove from standby */
  94. clrbits_le32(&regs->sys_ctrl, V_STANDBY_EN(1));
  95. switch (mode) {
  96. case VOP_MODE_HDMI:
  97. clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN,
  98. V_HDMI_OUT_EN(1));
  99. break;
  100. case VOP_MODE_EDP:
  101. clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN,
  102. V_EDP_OUT_EN(1));
  103. break;
  104. #if defined(CONFIG_ROCKCHIP_RK3288)
  105. case VOP_MODE_LVDS:
  106. clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN,
  107. V_RGB_OUT_EN(1));
  108. break;
  109. #endif
  110. case VOP_MODE_MIPI:
  111. clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN,
  112. V_MIPI_OUT_EN(1));
  113. break;
  114. default:
  115. debug("%s: unsupported output mode %x\n", __func__, mode);
  116. }
  117. }
  118. static void rkvop_mode_set(struct udevice *dev,
  119. const struct display_timing *edid,
  120. enum vop_modes mode)
  121. {
  122. struct rk_vop_priv *priv = dev_get_priv(dev);
  123. struct rk3288_vop *regs = priv->regs;
  124. struct rkvop_driverdata *data =
  125. (struct rkvop_driverdata *)dev_get_driver_data(dev);
  126. u32 hactive = edid->hactive.typ;
  127. u32 vactive = edid->vactive.typ;
  128. u32 hsync_len = edid->hsync_len.typ;
  129. u32 hback_porch = edid->hback_porch.typ;
  130. u32 vsync_len = edid->vsync_len.typ;
  131. u32 vback_porch = edid->vback_porch.typ;
  132. u32 hfront_porch = edid->hfront_porch.typ;
  133. u32 vfront_porch = edid->vfront_porch.typ;
  134. int mode_flags;
  135. u32 pin_polarity;
  136. pin_polarity = BIT(DCLK_INVERT);
  137. if (edid->flags & DISPLAY_FLAGS_HSYNC_HIGH)
  138. pin_polarity |= BIT(HSYNC_POSITIVE);
  139. if (edid->flags & DISPLAY_FLAGS_VSYNC_HIGH)
  140. pin_polarity |= BIT(VSYNC_POSITIVE);
  141. rkvop_set_pin_polarity(dev, mode, pin_polarity);
  142. rkvop_enable_output(dev, mode);
  143. mode_flags = 0; /* RGB888 */
  144. if ((data->features & VOP_FEATURE_OUTPUT_10BIT) &&
  145. (mode == VOP_MODE_HDMI || mode == VOP_MODE_EDP))
  146. mode_flags = 15; /* RGBaaa */
  147. clrsetbits_le32(&regs->dsp_ctrl0, M_DSP_OUT_MODE,
  148. V_DSP_OUT_MODE(mode_flags));
  149. writel(V_HSYNC(hsync_len) |
  150. V_HORPRD(hsync_len + hback_porch + hactive + hfront_porch),
  151. &regs->dsp_htotal_hs_end);
  152. writel(V_HEAP(hsync_len + hback_porch + hactive) |
  153. V_HASP(hsync_len + hback_porch),
  154. &regs->dsp_hact_st_end);
  155. writel(V_VSYNC(vsync_len) |
  156. V_VERPRD(vsync_len + vback_porch + vactive + vfront_porch),
  157. &regs->dsp_vtotal_vs_end);
  158. writel(V_VAEP(vsync_len + vback_porch + vactive)|
  159. V_VASP(vsync_len + vback_porch),
  160. &regs->dsp_vact_st_end);
  161. writel(V_HEAP(hsync_len + hback_porch + hactive) |
  162. V_HASP(hsync_len + hback_porch),
  163. &regs->post_dsp_hact_info);
  164. writel(V_VAEP(vsync_len + vback_porch + vactive)|
  165. V_VASP(vsync_len + vback_porch),
  166. &regs->post_dsp_vact_info);
  167. writel(0x01, &regs->reg_cfg_done); /* enable reg config */
  168. }
  169. /**
  170. * rk_display_init() - Try to enable the given display device
  171. *
  172. * This function performs many steps:
  173. * - Finds the display device being referenced by @ep_node
  174. * - Puts the VOP's ID into its uclass platform data
  175. * - Probes the device to set it up
  176. * - Reads the EDID timing information
  177. * - Sets up the VOP clocks, etc. for the selected pixel clock and display mode
  178. * - Enables the display (the display device handles this and will do different
  179. * things depending on the display type)
  180. * - Tells the uclass about the display resolution so that the console will
  181. * appear correctly
  182. *
  183. * @dev: VOP device that we want to connect to the display
  184. * @fbbase: Frame buffer address
  185. * @ep_node: Device tree node to process - this is the offset of an endpoint
  186. * node within the VOP's 'port' list.
  187. * @return 0 if OK, -ve if something went wrong
  188. */
  189. static int rk_display_init(struct udevice *dev, ulong fbbase, ofnode ep_node)
  190. {
  191. struct video_priv *uc_priv = dev_get_uclass_priv(dev);
  192. struct rk_vop_priv *priv = dev_get_priv(dev);
  193. int vop_id, remote_vop_id;
  194. struct rk3288_vop *regs = priv->regs;
  195. struct display_timing timing;
  196. struct udevice *disp;
  197. int ret;
  198. u32 remote_phandle;
  199. struct display_plat *disp_uc_plat;
  200. struct clk clk;
  201. enum video_log2_bpp l2bpp;
  202. ofnode remote;
  203. debug("%s(%s, %lu, %s)\n", __func__,
  204. dev_read_name(dev), fbbase, ofnode_get_name(ep_node));
  205. vop_id = ofnode_read_s32_default(ep_node, "reg", -1);
  206. debug("vop_id=%d\n", vop_id);
  207. ret = ofnode_read_u32(ep_node, "remote-endpoint", &remote_phandle);
  208. if (ret)
  209. return ret;
  210. remote = ofnode_get_by_phandle(remote_phandle);
  211. if (!ofnode_valid(remote))
  212. return -EINVAL;
  213. remote_vop_id = ofnode_read_u32_default(remote, "reg", -1);
  214. debug("remote vop_id=%d\n", remote_vop_id);
  215. /*
  216. * The remote-endpoint references into a subnode of the encoder
  217. * (i.e. HDMI, MIPI, etc.) with the DTS looking something like
  218. * the following (assume 'hdmi_in_vopl' to be referenced):
  219. *
  220. * hdmi: hdmi@ff940000 {
  221. * ports {
  222. * hdmi_in: port {
  223. * hdmi_in_vopb: endpoint@0 { ... };
  224. * hdmi_in_vopl: endpoint@1 { ... };
  225. * }
  226. * }
  227. * }
  228. *
  229. * The original code had 3 steps of "walking the parent", but
  230. * a much better (as in: less likely to break if the DTS
  231. * changes) way of doing this is to "find the enclosing device
  232. * of UCLASS_DISPLAY".
  233. */
  234. while (ofnode_valid(remote)) {
  235. remote = ofnode_get_parent(remote);
  236. if (!ofnode_valid(remote)) {
  237. debug("%s(%s): no UCLASS_DISPLAY for remote-endpoint\n",
  238. __func__, dev_read_name(dev));
  239. return -EINVAL;
  240. }
  241. uclass_find_device_by_ofnode(UCLASS_DISPLAY, remote, &disp);
  242. if (disp)
  243. break;
  244. };
  245. disp_uc_plat = dev_get_uclass_platdata(disp);
  246. debug("Found device '%s', disp_uc_priv=%p\n", disp->name, disp_uc_plat);
  247. if (display_in_use(disp)) {
  248. debug(" - device in use\n");
  249. return -EBUSY;
  250. }
  251. disp_uc_plat->source_id = remote_vop_id;
  252. disp_uc_plat->src_dev = dev;
  253. ret = device_probe(disp);
  254. if (ret) {
  255. debug("%s: device '%s' display won't probe (ret=%d)\n",
  256. __func__, dev->name, ret);
  257. return ret;
  258. }
  259. ret = display_read_timing(disp, &timing);
  260. if (ret) {
  261. debug("%s: Failed to read timings\n", __func__);
  262. return ret;
  263. }
  264. ret = clk_get_by_index(dev, 1, &clk);
  265. if (!ret)
  266. ret = clk_set_rate(&clk, timing.pixelclock.typ);
  267. if (IS_ERR_VALUE(ret)) {
  268. debug("%s: Failed to set pixel clock: ret=%d\n", __func__, ret);
  269. return ret;
  270. }
  271. /* Set bitwidth for vop display according to vop mode */
  272. switch (vop_id) {
  273. case VOP_MODE_EDP:
  274. #if defined(CONFIG_ROCKCHIP_RK3288)
  275. case VOP_MODE_LVDS:
  276. #endif
  277. l2bpp = VIDEO_BPP16;
  278. break;
  279. case VOP_MODE_HDMI:
  280. case VOP_MODE_MIPI:
  281. l2bpp = VIDEO_BPP32;
  282. break;
  283. default:
  284. l2bpp = VIDEO_BPP16;
  285. }
  286. rkvop_mode_set(dev, &timing, vop_id);
  287. rkvop_enable(regs, fbbase, 1 << l2bpp, &timing);
  288. ret = display_enable(disp, 1 << l2bpp, &timing);
  289. if (ret)
  290. return ret;
  291. uc_priv->xsize = timing.hactive.typ;
  292. uc_priv->ysize = timing.vactive.typ;
  293. uc_priv->bpix = l2bpp;
  294. debug("fb=%lx, size=%d %d\n", fbbase, uc_priv->xsize, uc_priv->ysize);
  295. return 0;
  296. }
  297. void rk_vop_probe_regulators(struct udevice *dev,
  298. const char * const *names, int cnt)
  299. {
  300. int i, ret;
  301. const char *name;
  302. struct udevice *reg;
  303. for (i = 0; i < cnt; ++i) {
  304. name = names[i];
  305. debug("%s: probing regulator '%s'\n", dev->name, name);
  306. ret = regulator_autoset_by_name(name, &reg);
  307. if (!ret)
  308. ret = regulator_set_enable(reg, true);
  309. }
  310. }
  311. int rk_vop_probe(struct udevice *dev)
  312. {
  313. struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
  314. struct rk_vop_priv *priv = dev_get_priv(dev);
  315. int ret = 0;
  316. ofnode port, node;
  317. /* Before relocation we don't need to do anything */
  318. if (!(gd->flags & GD_FLG_RELOC))
  319. return 0;
  320. priv->regs = (struct rk3288_vop *)dev_read_addr(dev);
  321. /*
  322. * Try all the ports until we find one that works. In practice this
  323. * tries EDP first if available, then HDMI.
  324. *
  325. * Note that rockchip_vop_set_clk() always uses NPLL as the source
  326. * clock so it is currently not possible to use more than one display
  327. * device simultaneously.
  328. */
  329. port = dev_read_subnode(dev, "port");
  330. if (!ofnode_valid(port)) {
  331. debug("%s(%s): 'port' subnode not found\n",
  332. __func__, dev_read_name(dev));
  333. return -EINVAL;
  334. }
  335. for (node = ofnode_first_subnode(port);
  336. ofnode_valid(node);
  337. node = dev_read_next_subnode(node)) {
  338. ret = rk_display_init(dev, plat->base, node);
  339. if (ret)
  340. debug("Device failed: ret=%d\n", ret);
  341. if (!ret)
  342. break;
  343. }
  344. video_set_flush_dcache(dev, 1);
  345. return ret;
  346. }
  347. int rk_vop_bind(struct udevice *dev)
  348. {
  349. struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
  350. plat->size = 4 * (CONFIG_VIDEO_ROCKCHIP_MAX_XRES *
  351. CONFIG_VIDEO_ROCKCHIP_MAX_YRES);
  352. return 0;
  353. }