rk_hdmi.c 3.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
  4. * Copyright (c) 2015 Google, Inc
  5. * Copyright 2014 Rockchip Inc.
  6. */
  7. #include <common.h>
  8. #include <clk.h>
  9. #include <display.h>
  10. #include <dm.h>
  11. #include <dw_hdmi.h>
  12. #include <edid.h>
  13. #include <log.h>
  14. #include <regmap.h>
  15. #include <syscon.h>
  16. #include <asm/gpio.h>
  17. #include <asm/io.h>
  18. #include <asm/arch-rockchip/clock.h>
  19. #include <asm/arch-rockchip/hardware.h>
  20. #include "rk_hdmi.h"
  21. #include "rk_vop.h" /* for rk_vop_probe_regulators */
  22. static const struct hdmi_phy_config rockchip_phy_config[] = {
  23. {
  24. .mpixelclock = 74250000,
  25. .sym_ctr = 0x8009, .term = 0x0004, .vlev_ctr = 0x0272,
  26. }, {
  27. .mpixelclock = 148500000,
  28. .sym_ctr = 0x802b, .term = 0x0004, .vlev_ctr = 0x028d,
  29. }, {
  30. .mpixelclock = 297000000,
  31. .sym_ctr = 0x8039, .term = 0x0005, .vlev_ctr = 0x028d,
  32. }, {
  33. .mpixelclock = 584000000,
  34. .sym_ctr = 0x8039, .term = 0x0000, .vlev_ctr = 0x019d,
  35. }, {
  36. .mpixelclock = ~0ul,
  37. .sym_ctr = 0x0000, .term = 0x0000, .vlev_ctr = 0x0000,
  38. }
  39. };
  40. static const struct hdmi_mpll_config rockchip_mpll_cfg[] = {
  41. {
  42. .mpixelclock = 40000000,
  43. .cpce = 0x00b3, .gmp = 0x0000, .curr = 0x0018,
  44. }, {
  45. .mpixelclock = 65000000,
  46. .cpce = 0x0072, .gmp = 0x0001, .curr = 0x0028,
  47. }, {
  48. .mpixelclock = 66000000,
  49. .cpce = 0x013e, .gmp = 0x0003, .curr = 0x0038,
  50. }, {
  51. .mpixelclock = 83500000,
  52. .cpce = 0x0072, .gmp = 0x0001, .curr = 0x0028,
  53. }, {
  54. .mpixelclock = 146250000,
  55. .cpce = 0x0051, .gmp = 0x0002, .curr = 0x0038,
  56. }, {
  57. .mpixelclock = 148500000,
  58. .cpce = 0x0051, .gmp = 0x0003, .curr = 0x0000,
  59. }, {
  60. .mpixelclock = 272000000,
  61. .cpce = 0x0040, .gmp = 0x0003, .curr = 0x0000,
  62. }, {
  63. .mpixelclock = 340000000,
  64. .cpce = 0x0040, .gmp = 0x0003, .curr = 0x0000,
  65. }, {
  66. .mpixelclock = ~0ul,
  67. .cpce = 0x0051, .gmp = 0x0003, .curr = 0x0000,
  68. }
  69. };
  70. int rk_hdmi_read_edid(struct udevice *dev, u8 *buf, int buf_size)
  71. {
  72. struct rk_hdmi_priv *priv = dev_get_priv(dev);
  73. return dw_hdmi_read_edid(&priv->hdmi, buf, buf_size);
  74. }
  75. int rk_hdmi_ofdata_to_platdata(struct udevice *dev)
  76. {
  77. struct rk_hdmi_priv *priv = dev_get_priv(dev);
  78. struct dw_hdmi *hdmi = &priv->hdmi;
  79. hdmi->ioaddr = (ulong)dev_read_addr(dev);
  80. hdmi->mpll_cfg = rockchip_mpll_cfg;
  81. hdmi->phy_cfg = rockchip_phy_config;
  82. /* hdmi->i2c_clk_{high,low} are set up by the SoC driver */
  83. hdmi->reg_io_width = 4;
  84. hdmi->phy_set = dw_hdmi_phy_cfg;
  85. priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
  86. uclass_get_device_by_phandle(UCLASS_I2C, dev, "ddc-i2c-bus",
  87. &hdmi->ddc_bus);
  88. return 0;
  89. }
  90. void rk_hdmi_probe_regulators(struct udevice *dev,
  91. const char * const *names, int cnt)
  92. {
  93. rk_vop_probe_regulators(dev, names, cnt);
  94. }
  95. int rk_hdmi_probe(struct udevice *dev)
  96. {
  97. struct rk_hdmi_priv *priv = dev_get_priv(dev);
  98. struct dw_hdmi *hdmi = &priv->hdmi;
  99. int ret;
  100. ret = dw_hdmi_phy_wait_for_hpd(hdmi);
  101. if (ret < 0) {
  102. debug("hdmi can not get hpd signal\n");
  103. return -1;
  104. }
  105. dw_hdmi_init(hdmi);
  106. dw_hdmi_phy_init(hdmi);
  107. return 0;
  108. }