rk_edp.c 26 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2015 Google, Inc
  4. * Copyright 2014 Rockchip Inc.
  5. */
  6. #include <common.h>
  7. #include <clk.h>
  8. #include <display.h>
  9. #include <dm.h>
  10. #include <edid.h>
  11. #include <log.h>
  12. #include <malloc.h>
  13. #include <panel.h>
  14. #include <regmap.h>
  15. #include <syscon.h>
  16. #include <asm/gpio.h>
  17. #include <asm/io.h>
  18. #include <asm/arch-rockchip/clock.h>
  19. #include <asm/arch-rockchip/edp_rk3288.h>
  20. #include <asm/arch-rockchip/grf_rk3288.h>
  21. #include <asm/arch-rockchip/hardware.h>
  22. #include <dt-bindings/clock/rk3288-cru.h>
  23. #include <linux/delay.h>
  24. #define MAX_CR_LOOP 5
  25. #define MAX_EQ_LOOP 5
  26. #define DP_LINK_STATUS_SIZE 6
  27. static const char * const voltage_names[] = {
  28. "0.4V", "0.6V", "0.8V", "1.2V"
  29. };
  30. static const char * const pre_emph_names[] = {
  31. "0dB", "3.5dB", "6dB", "9.5dB"
  32. };
  33. #define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_1200
  34. #define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPHASIS_9_5
  35. struct rk_edp_priv {
  36. struct rk3288_edp *regs;
  37. struct rk3288_grf *grf;
  38. struct udevice *panel;
  39. struct link_train link_train;
  40. u8 train_set[4];
  41. };
  42. static void rk_edp_init_refclk(struct rk3288_edp *regs)
  43. {
  44. writel(SEL_24M, &regs->analog_ctl_2);
  45. writel(REF_CLK_24M, &regs->pll_reg_1);
  46. writel(LDO_OUTPUT_V_SEL_145 | KVCO_DEFALUT | CHG_PUMP_CUR_SEL_5US |
  47. V2L_CUR_SEL_1MA, &regs->pll_reg_2);
  48. writel(LOCK_DET_CNT_SEL_256 | LOOP_FILTER_RESET | PALL_SSC_RESET |
  49. LOCK_DET_BYPASS | PLL_LOCK_DET_MODE | PLL_LOCK_DET_FORCE,
  50. &regs->pll_reg_3);
  51. writel(REGULATOR_V_SEL_950MV | STANDBY_CUR_SEL |
  52. CHG_PUMP_INOUT_CTRL_1200MV | CHG_PUMP_INPUT_CTRL_OP,
  53. &regs->pll_reg_5);
  54. writel(SSC_OFFSET | SSC_MODE | SSC_DEPTH, &regs->ssc_reg);
  55. writel(TX_SWING_PRE_EMP_MODE | PRE_DRIVER_PW_CTRL1 |
  56. LP_MODE_CLK_REGULATOR | RESISTOR_MSB_CTRL | RESISTOR_CTRL,
  57. &regs->tx_common);
  58. writel(DP_AUX_COMMON_MODE | DP_AUX_EN | AUX_TERM_50OHM,
  59. &regs->dp_aux);
  60. writel(DP_BG_OUT_SEL | DP_DB_CUR_CTRL | DP_BG_SEL | DP_RESISTOR_TUNE_BG,
  61. &regs->dp_bias);
  62. writel(CH1_CH3_SWING_EMP_CTRL | CH0_CH2_SWING_EMP_CTRL,
  63. &regs->dp_reserv2);
  64. }
  65. static void rk_edp_init_interrupt(struct rk3288_edp *regs)
  66. {
  67. /* Set interrupt pin assertion polarity as high */
  68. writel(INT_POL, &regs->int_ctl);
  69. /* Clear pending registers */
  70. writel(0xff, &regs->common_int_sta_1);
  71. writel(0x4f, &regs->common_int_sta_2);
  72. writel(0xff, &regs->common_int_sta_3);
  73. writel(0x27, &regs->common_int_sta_4);
  74. writel(0x7f, &regs->dp_int_sta);
  75. /* 0:mask,1: unmask */
  76. writel(0x00, &regs->common_int_mask_1);
  77. writel(0x00, &regs->common_int_mask_2);
  78. writel(0x00, &regs->common_int_mask_3);
  79. writel(0x00, &regs->common_int_mask_4);
  80. writel(0x00, &regs->int_sta_mask);
  81. }
  82. static void rk_edp_enable_sw_function(struct rk3288_edp *regs)
  83. {
  84. clrbits_le32(&regs->func_en_1, SW_FUNC_EN_N);
  85. }
  86. static bool rk_edp_get_pll_locked(struct rk3288_edp *regs)
  87. {
  88. u32 val;
  89. val = readl(&regs->dp_debug_ctl);
  90. return val & PLL_LOCK;
  91. }
  92. static int rk_edp_init_analog_func(struct rk3288_edp *regs)
  93. {
  94. ulong start;
  95. writel(0x00, &regs->dp_pd);
  96. writel(PLL_LOCK_CHG, &regs->common_int_sta_1);
  97. clrbits_le32(&regs->dp_debug_ctl, F_PLL_LOCK | PLL_LOCK_CTRL);
  98. start = get_timer(0);
  99. while (!rk_edp_get_pll_locked(regs)) {
  100. if (get_timer(start) > PLL_LOCK_TIMEOUT) {
  101. printf("%s: PLL is not locked\n", __func__);
  102. return -ETIMEDOUT;
  103. }
  104. }
  105. /* Enable Serdes FIFO function and Link symbol clock domain module */
  106. clrbits_le32(&regs->func_en_2, SERDES_FIFO_FUNC_EN_N |
  107. LS_CLK_DOMAIN_FUNC_EN_N | AUX_FUNC_EN_N |
  108. SSC_FUNC_EN_N);
  109. return 0;
  110. }
  111. static void rk_edp_init_aux(struct rk3288_edp *regs)
  112. {
  113. /* Clear inerrupts related to AUX channel */
  114. writel(AUX_FUNC_EN_N, &regs->dp_int_sta);
  115. /* Disable AUX channel module */
  116. setbits_le32(&regs->func_en_2, AUX_FUNC_EN_N);
  117. /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
  118. writel(DEFER_CTRL_EN | DEFER_COUNT(1), &regs->aux_ch_defer_dtl);
  119. /* Enable AUX channel module */
  120. clrbits_le32(&regs->func_en_2, AUX_FUNC_EN_N);
  121. }
  122. static int rk_edp_aux_enable(struct rk3288_edp *regs)
  123. {
  124. ulong start;
  125. setbits_le32(&regs->aux_ch_ctl_2, AUX_EN);
  126. start = get_timer(0);
  127. do {
  128. if (!(readl(&regs->aux_ch_ctl_2) & AUX_EN))
  129. return 0;
  130. } while (get_timer(start) < 20);
  131. return -ETIMEDOUT;
  132. }
  133. static int rk_edp_is_aux_reply(struct rk3288_edp *regs)
  134. {
  135. ulong start;
  136. start = get_timer(0);
  137. while (!(readl(&regs->dp_int_sta) & RPLY_RECEIV)) {
  138. if (get_timer(start) > 10)
  139. return -ETIMEDOUT;
  140. }
  141. writel(RPLY_RECEIV, &regs->dp_int_sta);
  142. return 0;
  143. }
  144. static int rk_edp_start_aux_transaction(struct rk3288_edp *regs)
  145. {
  146. int val, ret;
  147. /* Enable AUX CH operation */
  148. ret = rk_edp_aux_enable(regs);
  149. if (ret) {
  150. debug("AUX CH enable timeout!\n");
  151. return ret;
  152. }
  153. /* Is AUX CH command reply received? */
  154. if (rk_edp_is_aux_reply(regs)) {
  155. debug("AUX CH command reply failed!\n");
  156. return ret;
  157. }
  158. /* Clear interrupt source for AUX CH access error */
  159. val = readl(&regs->dp_int_sta);
  160. if (val & AUX_ERR) {
  161. writel(AUX_ERR, &regs->dp_int_sta);
  162. return -EIO;
  163. }
  164. /* Check AUX CH error access status */
  165. val = readl(&regs->dp_int_sta);
  166. if (val & AUX_STATUS_MASK) {
  167. debug("AUX CH error happens: %d\n\n", val & AUX_STATUS_MASK);
  168. return -EIO;
  169. }
  170. return 0;
  171. }
  172. static int rk_edp_dpcd_transfer(struct rk3288_edp *regs,
  173. unsigned int val_addr, u8 *in_data,
  174. unsigned int length,
  175. enum dpcd_request request)
  176. {
  177. int val;
  178. int i, try_times;
  179. u8 *data;
  180. int ret = 0;
  181. u32 len = 0;
  182. while (length) {
  183. len = min(length, 16U);
  184. for (try_times = 0; try_times < 10; try_times++) {
  185. data = in_data;
  186. /* Clear AUX CH data buffer */
  187. writel(BUF_CLR, &regs->buf_data_ctl);
  188. /* Select DPCD device address */
  189. writel(AUX_ADDR_7_0(val_addr), &regs->aux_addr_7_0);
  190. writel(AUX_ADDR_15_8(val_addr), &regs->aux_addr_15_8);
  191. writel(AUX_ADDR_19_16(val_addr), &regs->aux_addr_19_16);
  192. /*
  193. * Set DisplayPort transaction and read 1 byte
  194. * If bit 3 is 1, DisplayPort transaction.
  195. * If Bit 3 is 0, I2C transaction.
  196. */
  197. if (request == DPCD_WRITE) {
  198. val = AUX_LENGTH(len) |
  199. AUX_TX_COMM_DP_TRANSACTION |
  200. AUX_TX_COMM_WRITE;
  201. for (i = 0; i < len; i++)
  202. writel(*data++, &regs->buf_data[i]);
  203. } else
  204. val = AUX_LENGTH(len) |
  205. AUX_TX_COMM_DP_TRANSACTION |
  206. AUX_TX_COMM_READ;
  207. writel(val, &regs->aux_ch_ctl_1);
  208. /* Start AUX transaction */
  209. ret = rk_edp_start_aux_transaction(regs);
  210. if (ret == 0)
  211. break;
  212. else
  213. printf("read dpcd Aux Transaction fail!\n");
  214. }
  215. if (ret)
  216. return ret;
  217. if (request == DPCD_READ) {
  218. for (i = 0; i < len; i++)
  219. *data++ = (u8)readl(&regs->buf_data[i]);
  220. }
  221. length -= len;
  222. val_addr += len;
  223. in_data += len;
  224. }
  225. return 0;
  226. }
  227. static int rk_edp_dpcd_read(struct rk3288_edp *regs, u32 addr, u8 *values,
  228. size_t size)
  229. {
  230. return rk_edp_dpcd_transfer(regs, addr, values, size, DPCD_READ);
  231. }
  232. static int rk_edp_dpcd_write(struct rk3288_edp *regs, u32 addr, u8 *values,
  233. size_t size)
  234. {
  235. return rk_edp_dpcd_transfer(regs, addr, values, size, DPCD_WRITE);
  236. }
  237. static int rk_edp_link_power_up(struct rk_edp_priv *edp)
  238. {
  239. u8 value;
  240. int ret;
  241. /* DP_SET_POWER register is only available on DPCD v1.1 and later */
  242. if (edp->link_train.revision < 0x11)
  243. return 0;
  244. ret = rk_edp_dpcd_read(edp->regs, DPCD_LINK_POWER_STATE, &value, 1);
  245. if (ret)
  246. return ret;
  247. value &= ~DP_SET_POWER_MASK;
  248. value |= DP_SET_POWER_D0;
  249. ret = rk_edp_dpcd_write(edp->regs, DPCD_LINK_POWER_STATE, &value, 1);
  250. if (ret)
  251. return ret;
  252. /*
  253. * According to the DP 1.1 specification, a "Sink Device must exit the
  254. * power saving state within 1 ms" (Section 2.5.3.1, Table 5-52, "Sink
  255. * Control Field" (register 0x600).
  256. */
  257. mdelay(1);
  258. return 0;
  259. }
  260. static int rk_edp_link_configure(struct rk_edp_priv *edp)
  261. {
  262. u8 values[2];
  263. values[0] = edp->link_train.link_rate;
  264. values[1] = edp->link_train.lane_count;
  265. return rk_edp_dpcd_write(edp->regs, DPCD_LINK_BW_SET, values,
  266. sizeof(values));
  267. }
  268. static void rk_edp_set_link_training(struct rk_edp_priv *edp,
  269. const u8 *training_values)
  270. {
  271. int i;
  272. for (i = 0; i < edp->link_train.lane_count; i++)
  273. writel(training_values[i], &edp->regs->ln_link_trn_ctl[i]);
  274. }
  275. static u8 edp_link_status(const u8 *link_status, int r)
  276. {
  277. return link_status[r - DPCD_LANE0_1_STATUS];
  278. }
  279. static int rk_edp_dpcd_read_link_status(struct rk_edp_priv *edp,
  280. u8 *link_status)
  281. {
  282. return rk_edp_dpcd_read(edp->regs, DPCD_LANE0_1_STATUS, link_status,
  283. DP_LINK_STATUS_SIZE);
  284. }
  285. static u8 edp_get_lane_status(const u8 *link_status, int lane)
  286. {
  287. int i = DPCD_LANE0_1_STATUS + (lane >> 1);
  288. int s = (lane & 1) * 4;
  289. u8 l = edp_link_status(link_status, i);
  290. return (l >> s) & 0xf;
  291. }
  292. static int rk_edp_clock_recovery(const u8 *link_status, int lane_count)
  293. {
  294. int lane;
  295. u8 lane_status;
  296. for (lane = 0; lane < lane_count; lane++) {
  297. lane_status = edp_get_lane_status(link_status, lane);
  298. if ((lane_status & DP_LANE_CR_DONE) == 0)
  299. return -EIO;
  300. }
  301. return 0;
  302. }
  303. static int rk_edp_channel_eq(const u8 *link_status, int lane_count)
  304. {
  305. u8 lane_align;
  306. u8 lane_status;
  307. int lane;
  308. lane_align = edp_link_status(link_status,
  309. DPCD_LANE_ALIGN_STATUS_UPDATED);
  310. if (!(lane_align & DP_INTERLANE_ALIGN_DONE))
  311. return -EIO;
  312. for (lane = 0; lane < lane_count; lane++) {
  313. lane_status = edp_get_lane_status(link_status, lane);
  314. if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS)
  315. return -EIO;
  316. }
  317. return 0;
  318. }
  319. static uint rk_edp_get_adjust_request_voltage(const u8 *link_status, int lane)
  320. {
  321. int i = DPCD_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
  322. int s = ((lane & 1) ?
  323. DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
  324. DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
  325. u8 l = edp_link_status(link_status, i);
  326. return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
  327. }
  328. static uint rk_edp_get_adjust_request_pre_emphasis(const u8 *link_status,
  329. int lane)
  330. {
  331. int i = DPCD_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
  332. int s = ((lane & 1) ?
  333. DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
  334. DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
  335. u8 l = edp_link_status(link_status, i);
  336. return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
  337. }
  338. static void edp_get_adjust_train(const u8 *link_status, int lane_count,
  339. u8 train_set[])
  340. {
  341. uint v = 0;
  342. uint p = 0;
  343. int lane;
  344. for (lane = 0; lane < lane_count; lane++) {
  345. uint this_v, this_p;
  346. this_v = rk_edp_get_adjust_request_voltage(link_status, lane);
  347. this_p = rk_edp_get_adjust_request_pre_emphasis(link_status,
  348. lane);
  349. debug("requested signal parameters: lane %d voltage %s pre_emph %s\n",
  350. lane,
  351. voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
  352. pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
  353. if (this_v > v)
  354. v = this_v;
  355. if (this_p > p)
  356. p = this_p;
  357. }
  358. if (v >= DP_VOLTAGE_MAX)
  359. v |= DP_TRAIN_MAX_SWING_REACHED;
  360. if (p >= DP_PRE_EMPHASIS_MAX)
  361. p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
  362. debug("using signal parameters: voltage %s pre_emph %s\n",
  363. voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK)
  364. >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
  365. pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK)
  366. >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
  367. for (lane = 0; lane < 4; lane++)
  368. train_set[lane] = v | p;
  369. }
  370. static int rk_edp_link_train_cr(struct rk_edp_priv *edp)
  371. {
  372. struct rk3288_edp *regs = edp->regs;
  373. int clock_recovery;
  374. uint voltage, tries = 0;
  375. u8 status[DP_LINK_STATUS_SIZE];
  376. int i, ret;
  377. u8 value;
  378. value = DP_TRAINING_PATTERN_1;
  379. writel(value, &regs->dp_training_ptn_set);
  380. ret = rk_edp_dpcd_write(regs, DPCD_TRAINING_PATTERN_SET, &value, 1);
  381. if (ret)
  382. return ret;
  383. memset(edp->train_set, '\0', sizeof(edp->train_set));
  384. /* clock recovery loop */
  385. clock_recovery = 0;
  386. tries = 0;
  387. voltage = 0xff;
  388. while (1) {
  389. rk_edp_set_link_training(edp, edp->train_set);
  390. ret = rk_edp_dpcd_write(regs, DPCD_TRAINING_LANE0_SET,
  391. edp->train_set,
  392. edp->link_train.lane_count);
  393. if (ret)
  394. return ret;
  395. mdelay(1);
  396. ret = rk_edp_dpcd_read_link_status(edp, status);
  397. if (ret) {
  398. printf("displayport link status failed, ret=%d\n", ret);
  399. break;
  400. }
  401. clock_recovery = rk_edp_clock_recovery(status,
  402. edp->link_train.lane_count);
  403. if (!clock_recovery)
  404. break;
  405. for (i = 0; i < edp->link_train.lane_count; i++) {
  406. if ((edp->train_set[i] &
  407. DP_TRAIN_MAX_SWING_REACHED) == 0)
  408. break;
  409. }
  410. if (i == edp->link_train.lane_count) {
  411. printf("clock recovery reached max voltage\n");
  412. break;
  413. }
  414. if ((edp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) ==
  415. voltage) {
  416. if (++tries == MAX_CR_LOOP) {
  417. printf("clock recovery tried 5 times\n");
  418. break;
  419. }
  420. } else {
  421. tries = 0;
  422. }
  423. voltage = edp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
  424. /* Compute new train_set as requested by sink */
  425. edp_get_adjust_train(status, edp->link_train.lane_count,
  426. edp->train_set);
  427. }
  428. if (clock_recovery) {
  429. printf("clock recovery failed: %d\n", clock_recovery);
  430. return clock_recovery;
  431. } else {
  432. debug("clock recovery at voltage %d pre-emphasis %d\n",
  433. edp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
  434. (edp->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
  435. DP_TRAIN_PRE_EMPHASIS_SHIFT);
  436. return 0;
  437. }
  438. }
  439. static int rk_edp_link_train_ce(struct rk_edp_priv *edp)
  440. {
  441. struct rk3288_edp *regs = edp->regs;
  442. int channel_eq;
  443. u8 value;
  444. int tries;
  445. u8 status[DP_LINK_STATUS_SIZE];
  446. int ret;
  447. value = DP_TRAINING_PATTERN_2;
  448. writel(value, &regs->dp_training_ptn_set);
  449. ret = rk_edp_dpcd_write(regs, DPCD_TRAINING_PATTERN_SET, &value, 1);
  450. if (ret)
  451. return ret;
  452. /* channel equalization loop */
  453. channel_eq = 0;
  454. for (tries = 0; tries < 5; tries++) {
  455. rk_edp_set_link_training(edp, edp->train_set);
  456. udelay(400);
  457. if (rk_edp_dpcd_read_link_status(edp, status) < 0) {
  458. printf("displayport link status failed\n");
  459. return -1;
  460. }
  461. channel_eq = rk_edp_channel_eq(status,
  462. edp->link_train.lane_count);
  463. if (!channel_eq)
  464. break;
  465. edp_get_adjust_train(status, edp->link_train.lane_count,
  466. edp->train_set);
  467. }
  468. if (channel_eq) {
  469. printf("channel eq failed, ret=%d\n", channel_eq);
  470. return channel_eq;
  471. }
  472. debug("channel eq at voltage %d pre-emphasis %d\n",
  473. edp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
  474. (edp->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
  475. >> DP_TRAIN_PRE_EMPHASIS_SHIFT);
  476. return 0;
  477. }
  478. static int rk_edp_init_training(struct rk_edp_priv *edp)
  479. {
  480. u8 values[3];
  481. int ret;
  482. ret = rk_edp_dpcd_read(edp->regs, DPCD_DPCD_REV, values,
  483. sizeof(values));
  484. if (ret < 0)
  485. return ret;
  486. edp->link_train.revision = values[0];
  487. edp->link_train.link_rate = values[1];
  488. edp->link_train.lane_count = values[2] & DP_MAX_LANE_COUNT_MASK;
  489. debug("max link rate:%d.%dGps max number of lanes:%d\n",
  490. edp->link_train.link_rate * 27 / 100,
  491. edp->link_train.link_rate * 27 % 100,
  492. edp->link_train.lane_count);
  493. if ((edp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
  494. (edp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
  495. debug("Rx Max Link Rate is abnormal :%x\n",
  496. edp->link_train.link_rate);
  497. return -EPERM;
  498. }
  499. if (edp->link_train.lane_count == 0) {
  500. debug("Rx Max Lane count is abnormal :%x\n",
  501. edp->link_train.lane_count);
  502. return -EPERM;
  503. }
  504. ret = rk_edp_link_power_up(edp);
  505. if (ret)
  506. return ret;
  507. return rk_edp_link_configure(edp);
  508. }
  509. static int rk_edp_hw_link_training(struct rk_edp_priv *edp)
  510. {
  511. ulong start;
  512. u32 val;
  513. int ret;
  514. /* Set link rate and count as you want to establish */
  515. writel(edp->link_train.link_rate, &edp->regs->link_bw_set);
  516. writel(edp->link_train.lane_count, &edp->regs->lane_count_set);
  517. ret = rk_edp_link_train_cr(edp);
  518. if (ret)
  519. return ret;
  520. ret = rk_edp_link_train_ce(edp);
  521. if (ret)
  522. return ret;
  523. writel(HW_LT_EN, &edp->regs->dp_hw_link_training);
  524. start = get_timer(0);
  525. do {
  526. val = readl(&edp->regs->dp_hw_link_training);
  527. if (!(val & HW_LT_EN))
  528. break;
  529. } while (get_timer(start) < 10);
  530. if (val & HW_LT_ERR_CODE_MASK) {
  531. printf("edp hw link training error: %d\n",
  532. val >> HW_LT_ERR_CODE_SHIFT);
  533. return -EIO;
  534. }
  535. return 0;
  536. }
  537. static int rk_edp_select_i2c_device(struct rk3288_edp *regs,
  538. unsigned int device_addr,
  539. unsigned int val_addr)
  540. {
  541. int ret;
  542. /* Set EDID device address */
  543. writel(device_addr, &regs->aux_addr_7_0);
  544. writel(0x0, &regs->aux_addr_15_8);
  545. writel(0x0, &regs->aux_addr_19_16);
  546. /* Set offset from base address of EDID device */
  547. writel(val_addr, &regs->buf_data[0]);
  548. /*
  549. * Set I2C transaction and write address
  550. * If bit 3 is 1, DisplayPort transaction.
  551. * If Bit 3 is 0, I2C transaction.
  552. */
  553. writel(AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT |
  554. AUX_TX_COMM_WRITE, &regs->aux_ch_ctl_1);
  555. /* Start AUX transaction */
  556. ret = rk_edp_start_aux_transaction(regs);
  557. if (ret != 0) {
  558. debug("select_i2c_device Aux Transaction fail!\n");
  559. return ret;
  560. }
  561. return 0;
  562. }
  563. static int rk_edp_i2c_read(struct rk3288_edp *regs, unsigned int device_addr,
  564. unsigned int val_addr, unsigned int count, u8 edid[])
  565. {
  566. u32 val;
  567. unsigned int i, j;
  568. unsigned int cur_data_idx;
  569. unsigned int defer = 0;
  570. int ret = 0;
  571. for (i = 0; i < count; i += 16) {
  572. for (j = 0; j < 10; j++) { /* try 10 times */
  573. /* Clear AUX CH data buffer */
  574. writel(BUF_CLR, &regs->buf_data_ctl);
  575. /* Set normal AUX CH command */
  576. clrbits_le32(&regs->aux_ch_ctl_2, ADDR_ONLY);
  577. /*
  578. * If Rx sends defer, Tx sends only reads
  579. * request without sending addres
  580. */
  581. if (!defer) {
  582. ret = rk_edp_select_i2c_device(regs,
  583. device_addr,
  584. val_addr + i);
  585. } else {
  586. defer = 0;
  587. }
  588. /*
  589. * Set I2C transaction and write data
  590. * If bit 3 is 1, DisplayPort transaction.
  591. * If Bit 3 is 0, I2C transaction.
  592. */
  593. writel(AUX_LENGTH(16) | AUX_TX_COMM_I2C_TRANSACTION |
  594. AUX_TX_COMM_READ, &regs->aux_ch_ctl_1);
  595. /* Start AUX transaction */
  596. ret = rk_edp_start_aux_transaction(regs);
  597. if (ret == 0) {
  598. break;
  599. } else {
  600. debug("Aux Transaction fail!\n");
  601. continue;
  602. }
  603. /* Check if Rx sends defer */
  604. val = readl(&regs->aux_rx_comm);
  605. if (val == AUX_RX_COMM_AUX_DEFER ||
  606. val == AUX_RX_COMM_I2C_DEFER) {
  607. debug("Defer: %d\n\n", val);
  608. defer = 1;
  609. }
  610. }
  611. if (ret)
  612. return ret;
  613. for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) {
  614. val = readl(&regs->buf_data[cur_data_idx]);
  615. edid[i + cur_data_idx] = (u8)val;
  616. }
  617. }
  618. return 0;
  619. }
  620. static int rk_edp_set_link_train(struct rk_edp_priv *edp)
  621. {
  622. int ret;
  623. ret = rk_edp_init_training(edp);
  624. if (ret) {
  625. printf("DP LT init failed!\n");
  626. return ret;
  627. }
  628. ret = rk_edp_hw_link_training(edp);
  629. if (ret)
  630. return ret;
  631. return 0;
  632. }
  633. static void rk_edp_init_video(struct rk3288_edp *regs)
  634. {
  635. writel(VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG,
  636. &regs->common_int_sta_1);
  637. writel(CHA_CRI(4) | CHA_CTRL, &regs->sys_ctl_2);
  638. writel(VID_HRES_TH(2) | VID_VRES_TH(0), &regs->video_ctl_8);
  639. }
  640. static void rk_edp_config_video_slave_mode(struct rk3288_edp *regs)
  641. {
  642. clrbits_le32(&regs->func_en_1, VID_FIFO_FUNC_EN_N | VID_CAP_FUNC_EN_N);
  643. }
  644. static void rk_edp_set_video_cr_mn(struct rk3288_edp *regs,
  645. enum clock_recovery_m_value_type type,
  646. u32 m_value,
  647. u32 n_value)
  648. {
  649. if (type == REGISTER_M) {
  650. setbits_le32(&regs->sys_ctl_4, FIX_M_VID);
  651. writel(m_value & 0xff, &regs->m_vid_0);
  652. writel((m_value >> 8) & 0xff, &regs->m_vid_1);
  653. writel((m_value >> 16) & 0xff, &regs->m_vid_2);
  654. writel(n_value & 0xf, &regs->n_vid_0);
  655. writel((n_value >> 8) & 0xff, &regs->n_vid_1);
  656. writel((n_value >> 16) & 0xff, &regs->n_vid_2);
  657. } else {
  658. clrbits_le32(&regs->sys_ctl_4, FIX_M_VID);
  659. writel(0x00, &regs->n_vid_0);
  660. writel(0x80, &regs->n_vid_1);
  661. writel(0x00, &regs->n_vid_2);
  662. }
  663. }
  664. static int rk_edp_is_video_stream_clock_on(struct rk3288_edp *regs)
  665. {
  666. ulong start;
  667. u32 val;
  668. start = get_timer(0);
  669. do {
  670. val = readl(&regs->sys_ctl_1);
  671. /* must write value to update DET_STA bit status */
  672. writel(val, &regs->sys_ctl_1);
  673. val = readl(&regs->sys_ctl_1);
  674. if (!(val & DET_STA))
  675. continue;
  676. val = readl(&regs->sys_ctl_2);
  677. /* must write value to update CHA_STA bit status */
  678. writel(val, &regs->sys_ctl_2);
  679. val = readl(&regs->sys_ctl_2);
  680. if (!(val & CHA_STA))
  681. return 0;
  682. } while (get_timer(start) < 100);
  683. return -ETIMEDOUT;
  684. }
  685. static int rk_edp_is_video_stream_on(struct rk_edp_priv *edp)
  686. {
  687. ulong start;
  688. u32 val;
  689. start = get_timer(0);
  690. do {
  691. val = readl(&edp->regs->sys_ctl_3);
  692. /* must write value to update STRM_VALID bit status */
  693. writel(val, &edp->regs->sys_ctl_3);
  694. val = readl(&edp->regs->sys_ctl_3);
  695. if (!(val & STRM_VALID))
  696. return 0;
  697. } while (get_timer(start) < 100);
  698. return -ETIMEDOUT;
  699. }
  700. static int rk_edp_config_video(struct rk_edp_priv *edp)
  701. {
  702. int ret;
  703. rk_edp_config_video_slave_mode(edp->regs);
  704. if (!rk_edp_get_pll_locked(edp->regs)) {
  705. debug("PLL is not locked yet.\n");
  706. return -ETIMEDOUT;
  707. }
  708. ret = rk_edp_is_video_stream_clock_on(edp->regs);
  709. if (ret)
  710. return ret;
  711. /* Set to use the register calculated M/N video */
  712. rk_edp_set_video_cr_mn(edp->regs, CALCULATED_M, 0, 0);
  713. /* For video bist, Video timing must be generated by register */
  714. clrbits_le32(&edp->regs->video_ctl_10, F_SEL);
  715. /* Disable video mute */
  716. clrbits_le32(&edp->regs->video_ctl_1, VIDEO_MUTE);
  717. /* Enable video at next frame */
  718. setbits_le32(&edp->regs->video_ctl_1, VIDEO_EN);
  719. return rk_edp_is_video_stream_on(edp);
  720. }
  721. static void rockchip_edp_force_hpd(struct rk_edp_priv *edp)
  722. {
  723. setbits_le32(&edp->regs->sys_ctl_3, F_HPD | HPD_CTRL);
  724. }
  725. static int rockchip_edp_get_plug_in_status(struct rk_edp_priv *edp)
  726. {
  727. u32 val;
  728. val = readl(&edp->regs->sys_ctl_3);
  729. if (val & HPD_STATUS)
  730. return 1;
  731. return 0;
  732. }
  733. /*
  734. * support edp HPD function
  735. * some hardware version do not support edp hdp,
  736. * we use 200ms to try to get the hpd single now,
  737. * if we can not get edp hpd single, it will delay 200ms,
  738. * also meet the edp power timing request, to compatible
  739. * all of the hardware version
  740. */
  741. static void rockchip_edp_wait_hpd(struct rk_edp_priv *edp)
  742. {
  743. ulong start;
  744. start = get_timer(0);
  745. do {
  746. if (rockchip_edp_get_plug_in_status(edp))
  747. return;
  748. udelay(100);
  749. } while (get_timer(start) < 200);
  750. debug("do not get hpd single, force hpd\n");
  751. rockchip_edp_force_hpd(edp);
  752. }
  753. static int rk_edp_enable(struct udevice *dev, int panel_bpp,
  754. const struct display_timing *edid)
  755. {
  756. struct rk_edp_priv *priv = dev_get_priv(dev);
  757. int ret = 0;
  758. ret = rk_edp_set_link_train(priv);
  759. if (ret) {
  760. printf("link train failed!\n");
  761. return ret;
  762. }
  763. rk_edp_init_video(priv->regs);
  764. ret = rk_edp_config_video(priv);
  765. if (ret) {
  766. printf("config video failed\n");
  767. return ret;
  768. }
  769. ret = panel_enable_backlight(priv->panel);
  770. if (ret) {
  771. debug("%s: backlight error: %d\n", __func__, ret);
  772. return ret;
  773. }
  774. return 0;
  775. }
  776. static int rk_edp_read_edid(struct udevice *dev, u8 *buf, int buf_size)
  777. {
  778. struct rk_edp_priv *priv = dev_get_priv(dev);
  779. u32 edid_size = EDID_LENGTH;
  780. int ret;
  781. int i;
  782. for (i = 0; i < 3; i++) {
  783. ret = rk_edp_i2c_read(priv->regs, EDID_ADDR, EDID_HEADER,
  784. EDID_LENGTH, &buf[EDID_HEADER]);
  785. if (ret) {
  786. debug("EDID read failed\n");
  787. continue;
  788. }
  789. /*
  790. * check if the EDID has an extension flag, and read additional
  791. * EDID data if needed
  792. */
  793. if (buf[EDID_EXTENSION_FLAG]) {
  794. edid_size += EDID_LENGTH;
  795. ret = rk_edp_i2c_read(priv->regs, EDID_ADDR,
  796. EDID_LENGTH, EDID_LENGTH,
  797. &buf[EDID_LENGTH]);
  798. if (ret) {
  799. debug("EDID Read failed!\n");
  800. continue;
  801. }
  802. }
  803. goto done;
  804. }
  805. /* After 3 attempts, give up */
  806. return ret;
  807. done:
  808. return edid_size;
  809. }
  810. static int rk_edp_ofdata_to_platdata(struct udevice *dev)
  811. {
  812. struct rk_edp_priv *priv = dev_get_priv(dev);
  813. priv->regs = dev_read_addr_ptr(dev);
  814. priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
  815. return 0;
  816. }
  817. static int rk_edp_remove(struct udevice *dev)
  818. {
  819. struct rk_edp_priv *priv = dev_get_priv(dev);
  820. struct rk3288_edp *regs = priv->regs;
  821. setbits_le32(&regs->video_ctl_1, VIDEO_MUTE);
  822. clrbits_le32(&regs->video_ctl_1, VIDEO_EN);
  823. clrbits_le32(&regs->sys_ctl_3, F_HPD | HPD_CTRL);
  824. setbits_le32(&regs->func_en_1, SW_FUNC_EN_N);
  825. return 0;
  826. }
  827. static int rk_edp_probe(struct udevice *dev)
  828. {
  829. struct display_plat *uc_plat = dev_get_uclass_platdata(dev);
  830. struct rk_edp_priv *priv = dev_get_priv(dev);
  831. struct rk3288_edp *regs = priv->regs;
  832. struct clk clk;
  833. int ret;
  834. ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev, "rockchip,panel",
  835. &priv->panel);
  836. if (ret) {
  837. debug("%s: Cannot find panel for '%s' (ret=%d)\n", __func__,
  838. dev->name, ret);
  839. return ret;
  840. }
  841. int vop_id = uc_plat->source_id;
  842. debug("%s, uc_plat=%p, vop_id=%u\n", __func__, uc_plat, vop_id);
  843. ret = clk_get_by_index(dev, 1, &clk);
  844. if (ret >= 0) {
  845. ret = clk_set_rate(&clk, 0);
  846. clk_free(&clk);
  847. }
  848. if (ret) {
  849. debug("%s: Failed to set EDP clock: ret=%d\n", __func__, ret);
  850. return ret;
  851. }
  852. ret = clk_get_by_index(uc_plat->src_dev, 0, &clk);
  853. if (ret >= 0) {
  854. ret = clk_set_rate(&clk, 192000000);
  855. clk_free(&clk);
  856. }
  857. if (ret < 0) {
  858. debug("%s: Failed to set clock in source device '%s': ret=%d\n",
  859. __func__, uc_plat->src_dev->name, ret);
  860. return ret;
  861. }
  862. /* grf_edp_ref_clk_sel: from internal 24MHz or 27MHz clock */
  863. rk_setreg(&priv->grf->soc_con12, 1 << 4);
  864. /* select epd signal from vop0 or vop1 */
  865. rk_clrsetreg(&priv->grf->soc_con6, (1 << 5),
  866. (vop_id == 1) ? (1 << 5) : (0 << 5));
  867. rockchip_edp_wait_hpd(priv);
  868. rk_edp_init_refclk(regs);
  869. rk_edp_init_interrupt(regs);
  870. rk_edp_enable_sw_function(regs);
  871. ret = rk_edp_init_analog_func(regs);
  872. if (ret)
  873. return ret;
  874. rk_edp_init_aux(regs);
  875. return 0;
  876. }
  877. static const struct dm_display_ops dp_rockchip_ops = {
  878. .read_edid = rk_edp_read_edid,
  879. .enable = rk_edp_enable,
  880. };
  881. static const struct udevice_id rockchip_dp_ids[] = {
  882. { .compatible = "rockchip,rk3288-edp" },
  883. { }
  884. };
  885. U_BOOT_DRIVER(dp_rockchip) = {
  886. .name = "edp_rockchip",
  887. .id = UCLASS_DISPLAY,
  888. .of_match = rockchip_dp_ids,
  889. .ops = &dp_rockchip_ops,
  890. .ofdata_to_platdata = rk_edp_ofdata_to_platdata,
  891. .probe = rk_edp_probe,
  892. .remove = rk_edp_remove,
  893. .priv_auto_alloc_size = sizeof(struct rk_edp_priv),
  894. };