mvebu_lcd.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Video driver for Marvell Armada XP SoC
  4. *
  5. * Initialization of LCD interface and setup of SPLASH screen image
  6. */
  7. #include <common.h>
  8. #include <dm.h>
  9. #include <part.h>
  10. #include <video.h>
  11. #include <asm/cache.h>
  12. #include <dm/device_compat.h>
  13. #include <linux/delay.h>
  14. #include <linux/mbus.h>
  15. #include <asm/io.h>
  16. #include <asm/arch/cpu.h>
  17. #include <asm/arch/soc.h>
  18. #define MVEBU_LCD_WIN_CONTROL(w) (0xf000 + ((w) << 4))
  19. #define MVEBU_LCD_WIN_BASE(w) (0xf004 + ((w) << 4))
  20. #define MVEBU_LCD_WIN_REMAP(w) (0xf00c + ((w) << 4))
  21. #define MVEBU_LCD_CFG_DMA_START_ADDR_0 0x00cc
  22. #define MVEBU_LCD_CFG_DMA_START_ADDR_1 0x00dc
  23. #define MVEBU_LCD_CFG_GRA_START_ADDR0 0x00f4
  24. #define MVEBU_LCD_CFG_GRA_START_ADDR1 0x00f8
  25. #define MVEBU_LCD_CFG_GRA_PITCH 0x00fc
  26. #define MVEBU_LCD_SPU_GRA_OVSA_HPXL_VLN 0x0100
  27. #define MVEBU_LCD_SPU_GRA_HPXL_VLN 0x0104
  28. #define MVEBU_LCD_SPU_GZM_HPXL_VLN 0x0108
  29. #define MVEBU_LCD_SPU_HWC_OVSA_HPXL_VLN 0x010c
  30. #define MVEBU_LCD_SPU_HWC_HPXL_VLN 0x0110
  31. #define MVEBU_LCD_SPUT_V_H_TOTAL 0x0114
  32. #define MVEBU_LCD_SPU_V_H_ACTIVE 0x0118
  33. #define MVEBU_LCD_SPU_H_PORCH 0x011c
  34. #define MVEBU_LCD_SPU_V_PORCH 0x0120
  35. #define MVEBU_LCD_SPU_BLANKCOLOR 0x0124
  36. #define MVEBU_LCD_SPU_ALPHA_COLOR1 0x0128
  37. #define MVEBU_LCD_SPU_ALPHA_COLOR2 0x012c
  38. #define MVEBU_LCD_SPU_COLORKEY_Y 0x0130
  39. #define MVEBU_LCD_SPU_COLORKEY_U 0x0134
  40. #define MVEBU_LCD_SPU_COLORKEY_V 0x0138
  41. #define MVEBU_LCD_CFG_RDREG4F 0x013c
  42. #define MVEBU_LCD_SPU_SPI_RXDATA 0x0140
  43. #define MVEBU_LCD_SPU_ISA_RXDATA 0x0144
  44. #define MVEBU_LCD_SPU_DBG_ISA 0x0148
  45. #define MVEBU_LCD_SPU_HWC_RDDAT 0x0158
  46. #define MVEBU_LCD_SPU_GAMMA_RDDAT 0x015c
  47. #define MVEBU_LCD_SPU_PALETTE_RDDAT 0x0160
  48. #define MVEBU_LCD_SPU_IOPAD_IN 0x0178
  49. #define MVEBU_LCD_FRAME_COUNT 0x017c
  50. #define MVEBU_LCD_SPU_DMA_CTRL0 0x0190
  51. #define MVEBU_LCD_SPU_DMA_CTRL1 0x0194
  52. #define MVEBU_LCD_SPU_SRAM_CTRL 0x0198
  53. #define MVEBU_LCD_SPU_SRAM_WRDAT 0x019c
  54. #define MVEBU_LCD_SPU_SRAM_PARA0 0x01a0
  55. #define MVEBU_LCD_SPU_SRAM_PARA1 0x01a4
  56. #define MVEBU_LCD_CFG_SCLK_DIV 0x01a8
  57. #define MVEBU_LCD_SPU_CONTRAST 0x01ac
  58. #define MVEBU_LCD_SPU_SATURATION 0x01b0
  59. #define MVEBU_LCD_SPU_CBSH_HUE 0x01b4
  60. #define MVEBU_LCD_SPU_DUMB_CTRL 0x01b8
  61. #define MVEBU_LCD_SPU_IOPAD_CONTROL 0x01bc
  62. #define MVEBU_LCD_SPU_IRQ_ENA_2 0x01d8
  63. #define MVEBU_LCD_SPU_IRQ_ISR_2 0x01dc
  64. #define MVEBU_LCD_SPU_IRQ_ENA 0x01c0
  65. #define MVEBU_LCD_SPU_IRQ_ISR 0x01c4
  66. #define MVEBU_LCD_ADLL_CTRL 0x01c8
  67. #define MVEBU_LCD_CLK_DIS 0x01cc
  68. #define MVEBU_LCD_VGA_HVSYNC_DELAY 0x01d4
  69. #define MVEBU_LCD_CLK_CFG_0 0xf0a0
  70. #define MVEBU_LCD_CLK_CFG_1 0xf0a4
  71. #define MVEBU_LCD_LVDS_CLK_CFG 0xf0ac
  72. #define MVEBU_LVDS_PADS_REG (MVEBU_SYSTEM_REG_BASE + 0xf0)
  73. enum {
  74. /* Maximum LCD size we support */
  75. LCD_MAX_WIDTH = 640,
  76. LCD_MAX_HEIGHT = 480,
  77. LCD_MAX_LOG2_BPP = VIDEO_BPP16,
  78. };
  79. struct mvebu_lcd_info {
  80. u32 fb_base;
  81. int x_res;
  82. int y_res;
  83. int x_fp;
  84. int y_fp;
  85. int x_bp;
  86. int y_bp;
  87. };
  88. struct mvebu_video_priv {
  89. uintptr_t regs;
  90. };
  91. /* Setup Mbus Bridge Windows for LCD */
  92. static void mvebu_lcd_conf_mbus_registers(uintptr_t regs)
  93. {
  94. const struct mbus_dram_target_info *dram;
  95. int i;
  96. dram = mvebu_mbus_dram_info();
  97. /* Disable windows, set size/base/remap to 0 */
  98. for (i = 0; i < 6; i++) {
  99. writel(0, regs + MVEBU_LCD_WIN_CONTROL(i));
  100. writel(0, regs + MVEBU_LCD_WIN_BASE(i));
  101. writel(0, regs + MVEBU_LCD_WIN_REMAP(i));
  102. }
  103. /* Write LCD bridge window registers */
  104. for (i = 0; i < dram->num_cs; i++) {
  105. const struct mbus_dram_window *cs = dram->cs + i;
  106. writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
  107. (dram->mbus_dram_target_id << 4) | 1,
  108. regs + MVEBU_LCD_WIN_CONTROL(i));
  109. writel(cs->base & 0xffff0000, regs + MVEBU_LCD_WIN_BASE(i));
  110. }
  111. }
  112. /* Initialize LCD registers */
  113. static void mvebu_lcd_register_init(struct mvebu_lcd_info *lcd_info,
  114. uintptr_t regs)
  115. {
  116. /* Local variable for easier handling */
  117. int x = lcd_info->x_res;
  118. int y = lcd_info->y_res;
  119. u32 val;
  120. /* Setup Mbus Bridge Windows */
  121. mvebu_lcd_conf_mbus_registers(regs);
  122. /*
  123. * Set LVDS Pads Control Register
  124. * wr 0 182F0 FFE00000
  125. */
  126. clrbits_le32(MVEBU_LVDS_PADS_REG, 0x1f << 16);
  127. /*
  128. * Set the LCD_CFG_GRA_START_ADDR0/1 Registers
  129. * This is supposed to point to the "physical" memory at memory
  130. * end (currently 1GB-64MB but also may be 2GB-64MB).
  131. * See also the Window 0 settings!
  132. */
  133. writel(lcd_info->fb_base, regs + MVEBU_LCD_CFG_GRA_START_ADDR0);
  134. writel(lcd_info->fb_base, regs + MVEBU_LCD_CFG_GRA_START_ADDR1);
  135. /*
  136. * Set the LCD_CFG_GRA_PITCH Register
  137. * Bits 31-28: Duty Cycle of Backlight. value/16=High (0x8=Mid Setting)
  138. * Bits 25-16: Backlight divider from 32kHz Clock
  139. * (here 16=0x10 for 1kHz)
  140. * Bits 15-00: Line Length in Bytes
  141. * 240*2 (for RGB1555)=480=0x1E0
  142. */
  143. writel(0x80100000 + 2 * x, regs + MVEBU_LCD_CFG_GRA_PITCH);
  144. /*
  145. * Set the LCD_SPU_GRA_OVSA_HPXL_VLN Register
  146. * Bits 31-16: Vertical start of graphical overlay on screen
  147. * Bits 15-00: Horizontal start of graphical overlay on screen
  148. */
  149. writel(0x00000000, regs + MVEBU_LCD_SPU_GRA_OVSA_HPXL_VLN);
  150. /*
  151. * Set the LCD_SPU_GRA_HPXL_VLN Register
  152. * Bits 31-16: Vertical size of graphical overlay 320=0x140
  153. * Bits 15-00: Horizontal size of graphical overlay 240=0xF0
  154. * Values before zooming
  155. */
  156. writel((y << 16) | x, regs + MVEBU_LCD_SPU_GRA_HPXL_VLN);
  157. /*
  158. * Set the LCD_SPU_GZM_HPXL_VLN Register
  159. * Bits 31-16: Vertical size of graphical overlay 320=0x140
  160. * Bits 15-00: Horizontal size of graphical overlay 240=0xF0
  161. * Values after zooming
  162. */
  163. writel((y << 16) | x, regs + MVEBU_LCD_SPU_GZM_HPXL_VLN);
  164. /*
  165. * Set the LCD_SPU_HWC_OVSA_HPXL_VLN Register
  166. * Bits 31-16: Vertical position of HW Cursor 320=0x140
  167. * Bits 15-00: Horizontal position of HW Cursor 240=0xF0
  168. */
  169. writel((y << 16) | x, regs + MVEBU_LCD_SPU_HWC_OVSA_HPXL_VLN);
  170. /*
  171. * Set the LCD_SPU_HWC_OVSA_HPXL_VLN Register
  172. * Bits 31-16: Vertical size of HW Cursor
  173. * Bits 15-00: Horizontal size of HW Cursor
  174. */
  175. writel(0x00000000, regs + MVEBU_LCD_SPU_HWC_HPXL_VLN);
  176. /*
  177. * Set the LCD_SPU_HWC_OVSA_HPXL_VLN Register
  178. * Bits 31-16: Screen total vertical lines:
  179. * VSYNC = 1
  180. * Vertical Front Porch = 2
  181. * Vertical Lines = 320
  182. * Vertical Back Porch = 2
  183. * SUM = 325 = 0x0145
  184. * Bits 15-00: Screen total horizontal pixels:
  185. * HSYNC = 1
  186. * Horizontal Front Porch = 44
  187. * Horizontal Lines = 240
  188. * Horizontal Back Porch = 2
  189. * SUM = 287 = 0x011F
  190. * Note: For the display the backporch is between SYNC and
  191. * the start of the pixels.
  192. * This is not certain for the Marvell (!?)
  193. */
  194. val = ((y + lcd_info->y_fp + lcd_info->y_bp + 1) << 16) |
  195. (x + lcd_info->x_fp + lcd_info->x_bp + 1);
  196. writel(val, regs + MVEBU_LCD_SPUT_V_H_TOTAL);
  197. /*
  198. * Set the LCD_SPU_V_H_ACTIVE Register
  199. * Bits 31-16: Screen active vertical lines 320=0x140
  200. * Bits 15-00: Screen active horizontakl pixels 240=0x00F0
  201. */
  202. writel((y << 16) | x, regs + MVEBU_LCD_SPU_V_H_ACTIVE);
  203. /*
  204. * Set the LCD_SPU_H_PORCH Register
  205. * Bits 31-16: Screen horizontal backporch 44=0x2c
  206. * Bits 15-00: Screen horizontal frontporch 2=0x02
  207. * Note: The terms "front" and "back" for the Marvell seem to be
  208. * exactly opposite to the display.
  209. */
  210. writel((lcd_info->x_fp << 16) | lcd_info->x_bp,
  211. regs + MVEBU_LCD_SPU_H_PORCH);
  212. /*
  213. * Set the LCD_SPU_V_PORCH Register
  214. * Bits 31-16: Screen vertical backporch 2=0x02
  215. * Bits 15-00: Screen vertical frontporch 2=0x02
  216. * Note: The terms "front" and "back" for the Marvell seem to be exactly
  217. * opposite to the display.
  218. */
  219. writel((lcd_info->y_fp << 16) | lcd_info->y_bp,
  220. regs + MVEBU_LCD_SPU_V_PORCH);
  221. /*
  222. * Set the LCD_SPU_BLANKCOLOR Register
  223. * This should be black = 0
  224. * For tests this is magenta=00FF00FF
  225. */
  226. writel(0x00FF00FF, regs + MVEBU_LCD_SPU_BLANKCOLOR);
  227. /*
  228. * Registers in the range of 0x0128 to 0x012C are colors for the cursor
  229. * Registers in the range of 0x0130 to 0x0138 are colors for video
  230. * color keying
  231. */
  232. /*
  233. * Set the LCD_SPU_RDREG4F Register
  234. * Bits 31-12: Reservd
  235. * Bit 11: SRAM Wait
  236. * Bit 10: Smart display fast TX (must be 1)
  237. * Bit 9: DMA Arbitration Video/Graphics overlay: 0=interleaved
  238. * Bit 8: FIFO watermark for DMA: 0=disable
  239. * Bits 07-00: Empty 8B FIFO entries to trigger DMA, default=0x80
  240. */
  241. writel(0x00000780, regs + MVEBU_LCD_CFG_RDREG4F);
  242. /*
  243. * Set the LCD_SPU_DMACTRL 0 Register
  244. * Bit 31: Disable overlay blending 1=disable
  245. * Bit 30: Gamma correction enable, 0=disable
  246. * Bit 29: Video Contrast/Saturation/Hue Adjust enable, 0=disable
  247. * Bit 28: Color palette enable, 0=disable
  248. * Bit 27: DMA AXI Arbiter, 1=default
  249. * Bit 26: HW Cursor 1-bit mode
  250. * Bit 25: HW Cursor or 1- or 2-bit mode
  251. * Bit 24: HW Cursor enabled, 0=disable
  252. * Bits 23-20: Graphics Memory Color Format: 0x1=RGB1555
  253. * Bits 19-16: Video Memory Color Format: 0x1=RGB1555
  254. * Bit 15: Memory Toggle between frame 0 and 1: 0=disable
  255. * Bit 14: Graphics horizontal scaling enable: 0=disable
  256. * Bit 13: Graphics test mode: 0=disable
  257. * Bit 12: Graphics SWAP R and B: 0=disable
  258. * Bit 11: Graphics SWAP U and V: 0=disable
  259. * Bit 10: Graphics SWAP Y and U/V: 0=disable
  260. * Bit 09: Graphic YUV to RGB Conversion: 0=disable
  261. * Bit 08: Graphic Transfer: 1=enable
  262. * Bit 07: Memory Toggle: 0=disable
  263. * Bit 06: Video horizontal scaling enable: 0=disable
  264. * Bit 05: Video test mode: 0=disable
  265. * Bit 04: Video SWAP R and B: 0=disable
  266. * Bit 03: Video SWAP U and V: 0=disable
  267. * Bit 02: Video SWAP Y and U/V: 0=disable
  268. * Bit 01: Video YUV to RGB Conversion: 0=disable
  269. * Bit 00: Video Transfer: 0=disable
  270. */
  271. writel(0x88111100, regs + MVEBU_LCD_SPU_DMA_CTRL0);
  272. /*
  273. * Set the LCD_SPU_DMA_CTRL1 Register
  274. * Bit 31: Manual DMA Trigger = 0
  275. * Bits 30-28: DMA Trigger Source: 0x2 VSYNC
  276. * Bit 28: VSYNC_INV: 0=Rising Edge, 1=Falling Edge
  277. * Bits 26-24: Color Key Mode: 0=disable
  278. * Bit 23: Fill low bits: 0=fill with zeroes
  279. * Bit 22: Reserved
  280. * Bit 21: Gated Clock: 0=disable
  281. * Bit 20: Power Save enable: 0=disable
  282. * Bits 19-18: Reserved
  283. * Bits 17-16: Configure Video/Graphic Path: 0x1: Graphic path alpha.
  284. * Bits 15-08: Configure Alpha: 0x00.
  285. * Bits 07-00: Reserved.
  286. */
  287. writel(0x20010000, regs + MVEBU_LCD_SPU_DMA_CTRL1);
  288. /*
  289. * Set the LCD_SPU_SRAM_CTRL Register
  290. * Reset to default = 0000C000
  291. * Bits 15-14: SRAM control: init=0x3, Read=0, Write=2
  292. * Bits 11-08: SRAM address ID: 0=gamma_yr, 1=gammy_ug, 2=gamma_vb,
  293. * 3=palette, 15=cursor
  294. */
  295. writel(0x0000C000, regs + MVEBU_LCD_SPU_SRAM_CTRL);
  296. /*
  297. * LCD_SPU_SRAM_WRDAT register: 019C
  298. * LCD_SPU_SRAM_PARA0 register: 01A0
  299. * LCD_SPU_SRAM_PARA1 register: 01A4 - Cursor control/Power settings
  300. */
  301. writel(0x00000000, regs + MVEBU_LCD_SPU_SRAM_PARA1);
  302. /* Clock settings in the at 01A8 and in the range F0A0 see below */
  303. /*
  304. * Set LCD_SPU_CONTRAST
  305. * Bits 31-16: Brightness sign ext. 8-bit value +255 to -255: default=0
  306. * Bits 15-00: Contrast sign ext. 8-bit value +255 to -255: default=0
  307. */
  308. writel(0x00000000, regs + MVEBU_LCD_SPU_CONTRAST);
  309. /*
  310. * Set LCD_SPU_SATURATION
  311. * Bits 31-16: Multiplier signed 4.12 fixed point value
  312. * Bits 15-00: Saturation signed 4.12 fixed point value
  313. */
  314. writel(0x10001000, regs + MVEBU_LCD_SPU_SATURATION);
  315. /*
  316. * Set LCD_SPU_HUE
  317. * Bits 31-16: Sine signed 2.14 fixed point value
  318. * Bits 15-00: Cosine signed 2.14 fixed point value
  319. */
  320. writel(0x00000000, regs + MVEBU_LCD_SPU_CBSH_HUE);
  321. /*
  322. * Set LCD_SPU_DUMB_CTRL
  323. * Bits 31-28: LCD Type: 3=18 bit RGB | 6=24 bit RGB888
  324. * Bits 27-12: Reserved
  325. * Bit 11: LCD DMA Pipeline Enable: 1=Enable
  326. * Bits 10-09: Reserved
  327. * Bit 8: LCD GPIO pin (??)
  328. * Bit 7: Reverse RGB
  329. * Bit 6: Invert composite blank signal DE/EN (??)
  330. * Bit 5: Invert composite sync signal
  331. * Bit 4: Invert Pixel Valid Enable DE/EN (??)
  332. * Bit 3: Invert VSYNC
  333. * Bit 2: Invert HSYNC
  334. * Bit 1: Invert Pixel Clock
  335. * Bit 0: Enable LCD Panel: 1=Enable
  336. * Question: Do we have to disable Smart and Dumb LCD
  337. * and separately enable LVDS?
  338. */
  339. writel(0x6000080F, regs + MVEBU_LCD_SPU_DUMB_CTRL);
  340. /*
  341. * Set LCD_SPU_IOPAD_CTRL
  342. * Bits 31-20: Reserved
  343. * Bits 19-18: Vertical Interpolation: 0=Disable
  344. * Bits 17-16: Reserved
  345. * Bit 15: Graphics Vertical Mirror enable: 0=disable
  346. * Bit 14: Reserved
  347. * Bit 13: Video Vertical Mirror enable: 0=disable
  348. * Bit 12: Reserved
  349. * Bit 11: Command Vertical Mirror enable: 0=disable
  350. * Bit 10: Reserved
  351. * Bits 09-08: YUV to RGB Color space conversion: 0 (Not used)
  352. * Bits 07-04: AXI Bus Master: 0x4: no crossing of 4k boundary,
  353. * 128 Bytes burst
  354. * Bits 03-00: LCD pins: ??? 0=24-bit Dump panel ??
  355. */
  356. writel(0x000000C0, regs + MVEBU_LCD_SPU_IOPAD_CONTROL);
  357. /*
  358. * Set SUP_IRQ_ENA_2: Disable all interrupts
  359. */
  360. writel(0x00000000, regs + MVEBU_LCD_SPU_IRQ_ENA_2);
  361. /*
  362. * Set SUP_IRQ_ENA: Disable all interrupts.
  363. */
  364. writel(0x00000000, regs + MVEBU_LCD_SPU_IRQ_ENA);
  365. /*
  366. * Set up ADDL Control Register
  367. * Bits 31-29: 0x0 = Fastest Delay Line (default)
  368. * 0x3 = Slowest Delay Line (default)
  369. * Bit 28: Calibration done status.
  370. * Bit 27: Reserved
  371. * Bit 26: Set Pixel Clock to ADDL output
  372. * Bit 25: Reduce CAL Enable
  373. * Bits 24-22: Manual calibration value.
  374. * Bit 21: Manual calibration enable.
  375. * Bit 20: Restart Auto Cal
  376. * Bits 19-16: Calibration Threshold voltage, default= 0x2
  377. * Bite 15-14: Reserved
  378. * Bits 13-11: Divisor for ADDL Clock: 0x1=/2, 0x3=/8, 0x5=/16
  379. * Bit 10: Power Down ADDL module, default = 1!
  380. * Bits 09-08: Test point configuration: 0x2=Bias, 0x3=High-z
  381. * Bit 07: Reset ADDL
  382. * Bit 06: Invert ADLL Clock
  383. * Bits 05-00: Delay taps, 0x3F=Half Cycle, 0x00=No delay
  384. * Note: ADLL is used for a VGA interface with DAC - not used here
  385. */
  386. writel(0x00000000, regs + MVEBU_LCD_ADLL_CTRL);
  387. /*
  388. * Set the LCD_CLK_DIS Register:
  389. * Bits 3 and 4 must be 1
  390. */
  391. writel(0x00000018, regs + MVEBU_LCD_CLK_DIS);
  392. /*
  393. * Set the LCD_VGA_HSYNC/VSYNC Delay Register:
  394. * Bits 03-00: Sets the delay for the HSYNC and VSYNC signals
  395. */
  396. writel(0x00000000, regs + MVEBU_LCD_VGA_HVSYNC_DELAY);
  397. /*
  398. * Clock registers
  399. * See page 475 in the functional spec.
  400. */
  401. /* Step 1 and 2: Disable the PLL */
  402. /*
  403. * Disable PLL, see "LCD Clock Configuration 1 Register" below
  404. */
  405. writel(0x8FF40007, regs + MVEBU_LCD_CLK_CFG_1);
  406. /*
  407. * Powerdown, see "LCD Clock Configuration 0 Register" below
  408. */
  409. writel(0x94000174, regs + MVEBU_LCD_CLK_CFG_0);
  410. /*
  411. * Set the LCD_CFG_SCLK_DIV Register
  412. * This is set fix to 0x40000001 for the LVDS output:
  413. * Bits 31-30: SCLCK Source: 0=AXIBus, 1=AHBus, 2=PLLDivider0
  414. * Bits 15-01: Clock Divider: Bypass for LVDS=0x0001
  415. * See page 475 in section 28.5.
  416. */
  417. writel(0x80000001, regs + MVEBU_LCD_CFG_SCLK_DIV);
  418. /*
  419. * Set the LCD Clock Configuration 0 Register:
  420. * Bit 31: Powerdown: 0=Power up
  421. * Bits 30-29: Reserved
  422. * Bits 28-26: PLL_KDIV: This encodes K
  423. * K=16 => 0x5
  424. * Bits 25-17: PLL_MDIV: This is M-1:
  425. * M=1 => 0x0
  426. * Bits 16-13: VCO band: 0x1 for 700-920MHz
  427. * Bits 12-04: PLL_NDIV: This is N-1 and corresponds to R1_CTRL!
  428. * N=28=0x1C => 0x1B
  429. * Bits 03-00: R1_CTRL (for N=28 => 0x4)
  430. */
  431. writel(0x940021B4, regs + MVEBU_LCD_CLK_CFG_0);
  432. /*
  433. * Set the LCD Clock Configuration 1 Register:
  434. * Bits 31-19: Reserved
  435. * Bit 18: Select PLL: Core PLL, 1=Dedicated PPL
  436. * Bit 17: Clock Output Enable: 0=disable, 1=enable
  437. * Bit 16: Select RefClk: 0=RefClk (25MHz), 1=External
  438. * Bit 15: Half-Div, Device Clock by DIV+0.5*Half-Dev
  439. * Bits 14-13: Reserved
  440. * Bits 12-00: PLL Full Divider [Note: Assumed to be the Post-Divider
  441. * M' for LVDS=7!]
  442. */
  443. writel(0x8FF40007, regs + MVEBU_LCD_CLK_CFG_1);
  444. /*
  445. * Set the LVDS Clock Configuration Register:
  446. * Bit 31: Clock Gating for the input clock to the LVDS
  447. * Bit 30: LVDS Serializer enable: 1=Enabled
  448. * Bits 29-11: Reserved
  449. * Bit 11-08: LVDS Clock delay: 0x02 (default): by 2 pixel clock/7
  450. * Bits 07-02: Reserved
  451. * Bit 01: 24bbp Option: 0=Option_1,1=Option2
  452. * Bit 00: 1=24bbp Panel: 0=18bpp Panel
  453. * Note: Bits 0 and must be verified with the help of the
  454. * Interface/display
  455. */
  456. writel(0xC0000201, regs + MVEBU_LCD_LVDS_CLK_CFG);
  457. /*
  458. * Power up PLL (Clock Config 0)
  459. */
  460. writel(0x140021B4, regs + MVEBU_LCD_CLK_CFG_0);
  461. /* wait 10 ms */
  462. mdelay(10);
  463. /*
  464. * Enable PLL (Clock Config 1)
  465. */
  466. writel(0x8FF60007, regs + MVEBU_LCD_CLK_CFG_1);
  467. }
  468. static int mvebu_video_probe(struct udevice *dev)
  469. {
  470. struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
  471. struct video_priv *uc_priv = dev_get_uclass_priv(dev);
  472. struct mvebu_video_priv *priv = dev_get_priv(dev);
  473. struct mvebu_lcd_info lcd_info;
  474. struct display_timing timings;
  475. u32 fb_start, fb_end;
  476. int ret;
  477. priv->regs = dev_read_addr(dev);
  478. if (priv->regs == FDT_ADDR_T_NONE) {
  479. dev_err(dev, "failed to get LCD address\n");
  480. return -ENXIO;
  481. }
  482. ret = ofnode_decode_display_timing(dev_ofnode(dev), 0, &timings);
  483. if (ret) {
  484. dev_err(dev, "failed to get any display timings\n");
  485. return -EINVAL;
  486. }
  487. /* Use DT timing (resolution) in internal info struct */
  488. lcd_info.fb_base = plat->base;
  489. lcd_info.x_res = timings.hactive.typ;
  490. lcd_info.x_fp = timings.hfront_porch.typ;
  491. lcd_info.x_bp = timings.hback_porch.typ;
  492. lcd_info.y_res = timings.vactive.typ;
  493. lcd_info.y_fp = timings.vfront_porch.typ;
  494. lcd_info.y_bp = timings.vback_porch.typ;
  495. /* Initialize the LCD controller */
  496. mvebu_lcd_register_init(&lcd_info, priv->regs);
  497. /* Enable dcache for the frame buffer */
  498. fb_start = plat->base & ~(MMU_SECTION_SIZE - 1);
  499. fb_end = plat->base + plat->size;
  500. fb_end = ALIGN(fb_end, 1 << MMU_SECTION_SHIFT);
  501. mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start,
  502. DCACHE_WRITEBACK);
  503. video_set_flush_dcache(dev, true);
  504. uc_priv->xsize = lcd_info.x_res;
  505. uc_priv->ysize = lcd_info.y_res;
  506. uc_priv->bpix = VIDEO_BPP16; /* Uses RGB555 format */
  507. return 0;
  508. }
  509. static int mvebu_video_bind(struct udevice *dev)
  510. {
  511. struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
  512. plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
  513. (1 << LCD_MAX_LOG2_BPP) / 8;
  514. return 0;
  515. }
  516. static const struct udevice_id mvebu_video_ids[] = {
  517. { .compatible = "marvell,armada-xp-lcd" },
  518. { }
  519. };
  520. U_BOOT_DRIVER(mvebu_video) = {
  521. .name = "mvebu_video",
  522. .id = UCLASS_VIDEO,
  523. .of_match = mvebu_video_ids,
  524. .bind = mvebu_video_bind,
  525. .probe = mvebu_video_probe,
  526. .priv_auto_alloc_size = sizeof(struct mvebu_video_priv),
  527. };