broadwell_igd.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * From coreboot src/soc/intel/broadwell/igd.c
  4. *
  5. * Copyright (C) 2016 Google, Inc
  6. */
  7. #include <common.h>
  8. #include <bios_emul.h>
  9. #include <bootstage.h>
  10. #include <dm.h>
  11. #include <init.h>
  12. #include <log.h>
  13. #include <vbe.h>
  14. #include <video.h>
  15. #include <asm/cpu.h>
  16. #include <asm/intel_regs.h>
  17. #include <asm/io.h>
  18. #include <asm/mtrr.h>
  19. #include <asm/arch/cpu.h>
  20. #include <asm/arch/iomap.h>
  21. #include <asm/arch/pch.h>
  22. #include <linux/delay.h>
  23. #include "i915_reg.h"
  24. struct broadwell_igd_priv {
  25. u8 *regs;
  26. };
  27. struct broadwell_igd_plat {
  28. u32 dp_hotplug[3];
  29. int port_select;
  30. int power_up_delay;
  31. int power_backlight_on_delay;
  32. int power_down_delay;
  33. int power_backlight_off_delay;
  34. int power_cycle_delay;
  35. int cpu_backlight;
  36. int pch_backlight;
  37. int cdclk;
  38. int pre_graphics_delay;
  39. };
  40. #define GT_RETRY 1000
  41. #define GT_CDCLK_337 0
  42. #define GT_CDCLK_450 1
  43. #define GT_CDCLK_540 2
  44. #define GT_CDCLK_675 3
  45. u32 board_map_oprom_vendev(u32 vendev)
  46. {
  47. return SA_IGD_OPROM_VENDEV;
  48. }
  49. static int poll32(u8 *addr, uint mask, uint value)
  50. {
  51. ulong start;
  52. start = get_timer(0);
  53. debug("%s: addr %p = %x\n", __func__, addr, readl(addr));
  54. while ((readl(addr) & mask) != value) {
  55. if (get_timer(start) > GT_RETRY) {
  56. debug("poll32: timeout: %x\n", readl(addr));
  57. return -ETIMEDOUT;
  58. }
  59. }
  60. return 0;
  61. }
  62. static int haswell_early_init(struct udevice *dev)
  63. {
  64. struct broadwell_igd_priv *priv = dev_get_priv(dev);
  65. u8 *regs = priv->regs;
  66. int ret;
  67. /* Enable Force Wake */
  68. writel(0x00000020, regs + 0xa180);
  69. writel(0x00010001, regs + 0xa188);
  70. ret = poll32(regs + 0x130044, 1, 1);
  71. if (ret)
  72. goto err;
  73. /* Enable Counters */
  74. setbits_le32(regs + 0xa248, 0x00000016);
  75. /* GFXPAUSE settings */
  76. writel(0x00070020, regs + 0xa000);
  77. /* ECO Settings */
  78. clrsetbits_le32(regs + 0xa180, ~0xff3fffff, 0x15000000);
  79. /* Enable DOP Clock Gating */
  80. writel(0x000003fd, regs + 0x9424);
  81. /* Enable Unit Level Clock Gating */
  82. writel(0x00000080, regs + 0x9400);
  83. writel(0x40401000, regs + 0x9404);
  84. writel(0x00000000, regs + 0x9408);
  85. writel(0x02000001, regs + 0x940c);
  86. /*
  87. * RC6 Settings
  88. */
  89. /* Wake Rate Limits */
  90. setbits_le32(regs + 0xa090, 0x00000000);
  91. setbits_le32(regs + 0xa098, 0x03e80000);
  92. setbits_le32(regs + 0xa09c, 0x00280000);
  93. setbits_le32(regs + 0xa0a8, 0x0001e848);
  94. setbits_le32(regs + 0xa0ac, 0x00000019);
  95. /* Render/Video/Blitter Idle Max Count */
  96. writel(0x0000000a, regs + 0x02054);
  97. writel(0x0000000a, regs + 0x12054);
  98. writel(0x0000000a, regs + 0x22054);
  99. writel(0x0000000a, regs + 0x1a054);
  100. /* RC Sleep / RCx Thresholds */
  101. setbits_le32(regs + 0xa0b0, 0x00000000);
  102. setbits_le32(regs + 0xa0b4, 0x000003e8);
  103. setbits_le32(regs + 0xa0b8, 0x0000c350);
  104. /* RP Settings */
  105. setbits_le32(regs + 0xa010, 0x000f4240);
  106. setbits_le32(regs + 0xa014, 0x12060000);
  107. setbits_le32(regs + 0xa02c, 0x0000e808);
  108. setbits_le32(regs + 0xa030, 0x0003bd08);
  109. setbits_le32(regs + 0xa068, 0x000101d0);
  110. setbits_le32(regs + 0xa06c, 0x00055730);
  111. setbits_le32(regs + 0xa070, 0x0000000a);
  112. /* RP Control */
  113. writel(0x00000b92, regs + 0xa024);
  114. /* HW RC6 Control */
  115. writel(0x88040000, regs + 0xa090);
  116. /* Video Frequency Request */
  117. writel(0x08000000, regs + 0xa00c);
  118. /* Set RC6 VIDs */
  119. ret = poll32(regs + 0x138124, (1 << 31), 0);
  120. if (ret)
  121. goto err;
  122. writel(0, regs + 0x138128);
  123. writel(0x80000004, regs + 0x138124);
  124. ret = poll32(regs + 0x138124, (1 << 31), 0);
  125. if (ret)
  126. goto err;
  127. /* Enable PM Interrupts */
  128. writel(0x03000076, regs + 0x4402c);
  129. /* Enable RC6 in idle */
  130. writel(0x00040000, regs + 0xa094);
  131. return 0;
  132. err:
  133. debug("%s: ret=%d\n", __func__, ret);
  134. return ret;
  135. };
  136. static int haswell_late_init(struct udevice *dev)
  137. {
  138. struct broadwell_igd_priv *priv = dev_get_priv(dev);
  139. u8 *regs = priv->regs;
  140. int ret;
  141. /* Lock settings */
  142. setbits_le32(regs + 0x0a248, (1 << 31));
  143. setbits_le32(regs + 0x0a004, (1 << 4));
  144. setbits_le32(regs + 0x0a080, (1 << 2));
  145. setbits_le32(regs + 0x0a180, (1 << 31));
  146. /* Disable Force Wake */
  147. writel(0x00010000, regs + 0xa188);
  148. ret = poll32(regs + 0x130044, 1, 0);
  149. if (ret)
  150. goto err;
  151. writel(0x00000001, regs + 0xa188);
  152. /* Enable power well for DP and Audio */
  153. setbits_le32(regs + 0x45400, (1 << 31));
  154. ret = poll32(regs + 0x45400, 1 << 30, 1 << 30);
  155. if (ret)
  156. goto err;
  157. return 0;
  158. err:
  159. debug("%s: ret=%d\n", __func__, ret);
  160. return ret;
  161. };
  162. static int broadwell_early_init(struct udevice *dev)
  163. {
  164. struct broadwell_igd_priv *priv = dev_get_priv(dev);
  165. u8 *regs = priv->regs;
  166. int ret;
  167. /* Enable Force Wake */
  168. writel(0x00010001, regs + 0xa188);
  169. ret = poll32(regs + 0x130044, 1, 1);
  170. if (ret)
  171. goto err;
  172. /* Enable push bus metric control and shift */
  173. writel(0x00000004, regs + 0xa248);
  174. writel(0x000000ff, regs + 0xa250);
  175. writel(0x00000010, regs + 0xa25c);
  176. /* GFXPAUSE settings (set based on stepping) */
  177. /* ECO Settings */
  178. writel(0x45200000, regs + 0xa180);
  179. /* Enable DOP Clock Gating */
  180. writel(0x000000fd, regs + 0x9424);
  181. /* Enable Unit Level Clock Gating */
  182. writel(0x00000000, regs + 0x9400);
  183. writel(0x40401000, regs + 0x9404);
  184. writel(0x00000000, regs + 0x9408);
  185. writel(0x02000001, regs + 0x940c);
  186. writel(0x0000000a, regs + 0x1a054);
  187. /* Video Frequency Request */
  188. writel(0x08000000, regs + 0xa00c);
  189. writel(0x00000009, regs + 0x138158);
  190. writel(0x0000000d, regs + 0x13815c);
  191. /*
  192. * RC6 Settings
  193. */
  194. /* Wake Rate Limits */
  195. clrsetbits_le32(regs + 0x0a090, ~0, 0);
  196. setbits_le32(regs + 0x0a098, 0x03e80000);
  197. setbits_le32(regs + 0x0a09c, 0x00280000);
  198. setbits_le32(regs + 0x0a0a8, 0x0001e848);
  199. setbits_le32(regs + 0x0a0ac, 0x00000019);
  200. /* Render/Video/Blitter Idle Max Count */
  201. writel(0x0000000a, regs + 0x02054);
  202. writel(0x0000000a, regs + 0x12054);
  203. writel(0x0000000a, regs + 0x22054);
  204. /* RC Sleep / RCx Thresholds */
  205. setbits_le32(regs + 0x0a0b0, 0x00000000);
  206. setbits_le32(regs + 0x0a0b8, 0x00000271);
  207. /* RP Settings */
  208. setbits_le32(regs + 0x0a010, 0x000f4240);
  209. setbits_le32(regs + 0x0a014, 0x12060000);
  210. setbits_le32(regs + 0x0a02c, 0x0000e808);
  211. setbits_le32(regs + 0x0a030, 0x0003bd08);
  212. setbits_le32(regs + 0x0a068, 0x000101d0);
  213. setbits_le32(regs + 0x0a06c, 0x00055730);
  214. setbits_le32(regs + 0x0a070, 0x0000000a);
  215. setbits_le32(regs + 0x0a168, 0x00000006);
  216. /* RP Control */
  217. writel(0x00000b92, regs + 0xa024);
  218. /* HW RC6 Control */
  219. writel(0x90040000, regs + 0xa090);
  220. /* Set RC6 VIDs */
  221. ret = poll32(regs + 0x138124, (1 << 31), 0);
  222. if (ret)
  223. goto err;
  224. writel(0, regs + 0x138128);
  225. writel(0x80000004, regs + 0x138124);
  226. ret = poll32(regs + 0x138124, (1 << 31), 0);
  227. if (ret)
  228. goto err;
  229. /* Enable PM Interrupts */
  230. writel(0x03000076, regs + 0x4402c);
  231. /* Enable RC6 in idle */
  232. writel(0x00040000, regs + 0xa094);
  233. return 0;
  234. err:
  235. debug("%s: ret=%d\n", __func__, ret);
  236. return ret;
  237. }
  238. static int broadwell_late_init(struct udevice *dev)
  239. {
  240. struct broadwell_igd_priv *priv = dev_get_priv(dev);
  241. u8 *regs = priv->regs;
  242. int ret;
  243. /* Lock settings */
  244. setbits_le32(regs + 0x0a248, 1 << 31);
  245. setbits_le32(regs + 0x0a000, 1 << 18);
  246. setbits_le32(regs + 0x0a180, 1 << 31);
  247. /* Disable Force Wake */
  248. writel(0x00010000, regs + 0xa188);
  249. ret = poll32(regs + 0x130044, 1, 0);
  250. if (ret)
  251. goto err;
  252. /* Enable power well for DP and Audio */
  253. setbits_le32(regs + 0x45400, 1 << 31);
  254. ret = poll32(regs + 0x45400, 1 << 30, 1 << 30);
  255. if (ret)
  256. goto err;
  257. return 0;
  258. err:
  259. debug("%s: ret=%d\n", __func__, ret);
  260. return ret;
  261. };
  262. static unsigned long gtt_read(struct broadwell_igd_priv *priv,
  263. unsigned long reg)
  264. {
  265. return readl(priv->regs + reg);
  266. }
  267. static void gtt_write(struct broadwell_igd_priv *priv, unsigned long reg,
  268. unsigned long data)
  269. {
  270. writel(data, priv->regs + reg);
  271. }
  272. static inline void gtt_clrsetbits(struct broadwell_igd_priv *priv, u32 reg,
  273. u32 bic, u32 or)
  274. {
  275. clrsetbits_le32(priv->regs + reg, bic, or);
  276. }
  277. static int gtt_poll(struct broadwell_igd_priv *priv, u32 reg, u32 mask,
  278. u32 value)
  279. {
  280. unsigned try = GT_RETRY;
  281. u32 data;
  282. while (try--) {
  283. data = gtt_read(priv, reg);
  284. if ((data & mask) == value)
  285. return 0;
  286. udelay(10);
  287. }
  288. debug("GT init timeout\n");
  289. return -ETIMEDOUT;
  290. }
  291. static void igd_setup_panel(struct udevice *dev)
  292. {
  293. struct broadwell_igd_plat *plat = dev_get_platdata(dev);
  294. struct broadwell_igd_priv *priv = dev_get_priv(dev);
  295. u32 reg32;
  296. /* Setup Digital Port Hotplug */
  297. reg32 = (plat->dp_hotplug[0] & 0x7) << 2;
  298. reg32 |= (plat->dp_hotplug[1] & 0x7) << 10;
  299. reg32 |= (plat->dp_hotplug[2] & 0x7) << 18;
  300. gtt_write(priv, PCH_PORT_HOTPLUG, reg32);
  301. /* Setup Panel Power On Delays */
  302. reg32 = (plat->port_select & 0x3) << 30;
  303. reg32 |= (plat->power_up_delay & 0x1fff) << 16;
  304. reg32 |= (plat->power_backlight_on_delay & 0x1fff);
  305. gtt_write(priv, PCH_PP_ON_DELAYS, reg32);
  306. /* Setup Panel Power Off Delays */
  307. reg32 = (plat->power_down_delay & 0x1fff) << 16;
  308. reg32 |= (plat->power_backlight_off_delay & 0x1fff);
  309. gtt_write(priv, PCH_PP_OFF_DELAYS, reg32);
  310. /* Setup Panel Power Cycle Delay */
  311. if (plat->power_cycle_delay) {
  312. reg32 = gtt_read(priv, PCH_PP_DIVISOR);
  313. reg32 &= ~0xff;
  314. reg32 |= plat->power_cycle_delay & 0xff;
  315. gtt_write(priv, PCH_PP_DIVISOR, reg32);
  316. }
  317. /* Enable Backlight if needed */
  318. if (plat->cpu_backlight) {
  319. gtt_write(priv, BLC_PWM_CPU_CTL2, BLC_PWM2_ENABLE);
  320. gtt_write(priv, BLC_PWM_CPU_CTL, plat->cpu_backlight);
  321. }
  322. if (plat->pch_backlight) {
  323. gtt_write(priv, BLC_PWM_PCH_CTL1, BLM_PCH_PWM_ENABLE);
  324. gtt_write(priv, BLC_PWM_PCH_CTL2, plat->pch_backlight);
  325. }
  326. }
  327. static int igd_cdclk_init_haswell(struct udevice *dev)
  328. {
  329. struct broadwell_igd_plat *plat = dev_get_platdata(dev);
  330. struct broadwell_igd_priv *priv = dev_get_priv(dev);
  331. int cdclk = plat->cdclk;
  332. u16 devid;
  333. int gpu_is_ulx = 0;
  334. u32 dpdiv, lpcll;
  335. int ret;
  336. dm_pci_read_config16(dev, PCI_DEVICE_ID, &devid);
  337. /* Check for ULX GT1 or GT2 */
  338. if (devid == 0x0a0e || devid == 0x0a1e)
  339. gpu_is_ulx = 1;
  340. /* 675MHz is not supported on haswell */
  341. if (cdclk == GT_CDCLK_675)
  342. cdclk = GT_CDCLK_337;
  343. /* If CD clock is fixed or ULT then set to 450MHz */
  344. if ((gtt_read(priv, 0x42014) & 0x1000000) || cpu_is_ult())
  345. cdclk = GT_CDCLK_450;
  346. /* 540MHz is not supported on ULX */
  347. if (gpu_is_ulx && cdclk == GT_CDCLK_540)
  348. cdclk = GT_CDCLK_337;
  349. /* 337.5MHz is not supported on non-ULT/ULX */
  350. if (!gpu_is_ulx && !cpu_is_ult() && cdclk == GT_CDCLK_337)
  351. cdclk = GT_CDCLK_450;
  352. /* Set variables based on CD Clock setting */
  353. switch (cdclk) {
  354. case GT_CDCLK_337:
  355. dpdiv = 169;
  356. lpcll = (1 << 26);
  357. break;
  358. case GT_CDCLK_450:
  359. dpdiv = 225;
  360. lpcll = 0;
  361. break;
  362. case GT_CDCLK_540:
  363. dpdiv = 270;
  364. lpcll = (1 << 26);
  365. break;
  366. default:
  367. ret = -EDOM;
  368. goto err;
  369. }
  370. /* Set LPCLL_CTL CD Clock Frequency Select */
  371. gtt_clrsetbits(priv, 0x130040, ~0xf3ffffff, lpcll);
  372. /* ULX: Inform power controller of selected frequency */
  373. if (gpu_is_ulx) {
  374. if (cdclk == GT_CDCLK_450)
  375. gtt_write(priv, 0x138128, 0x00000000); /* 450MHz */
  376. else
  377. gtt_write(priv, 0x138128, 0x00000001); /* 337.5MHz */
  378. gtt_write(priv, 0x13812c, 0x00000000);
  379. gtt_write(priv, 0x138124, 0x80000017);
  380. }
  381. /* Set CPU DP AUX 2X bit clock dividers */
  382. gtt_clrsetbits(priv, 0x64010, ~0xfffff800, dpdiv);
  383. gtt_clrsetbits(priv, 0x64810, ~0xfffff800, dpdiv);
  384. return 0;
  385. err:
  386. debug("%s: ret=%d\n", __func__, ret);
  387. return ret;
  388. }
  389. static int igd_cdclk_init_broadwell(struct udevice *dev)
  390. {
  391. struct broadwell_igd_plat *plat = dev_get_platdata(dev);
  392. struct broadwell_igd_priv *priv = dev_get_priv(dev);
  393. int cdclk = plat->cdclk;
  394. u32 dpdiv, lpcll, pwctl, cdset;
  395. int ret;
  396. /* Inform power controller of upcoming frequency change */
  397. gtt_write(priv, 0x138128, 0);
  398. gtt_write(priv, 0x13812c, 0);
  399. gtt_write(priv, 0x138124, 0x80000018);
  400. /* Poll GT driver mailbox for run/busy clear */
  401. if (gtt_poll(priv, 0x138124, 1 << 31, 0 << 31))
  402. cdclk = GT_CDCLK_450;
  403. if (gtt_read(priv, 0x42014) & 0x1000000) {
  404. /* If CD clock is fixed then set to 450MHz */
  405. cdclk = GT_CDCLK_450;
  406. } else {
  407. /* Program CD clock to highest supported freq */
  408. if (cpu_is_ult())
  409. cdclk = GT_CDCLK_540;
  410. else
  411. cdclk = GT_CDCLK_675;
  412. }
  413. /* CD clock frequency 675MHz not supported on ULT */
  414. if (cpu_is_ult() && cdclk == GT_CDCLK_675)
  415. cdclk = GT_CDCLK_540;
  416. /* Set variables based on CD Clock setting */
  417. switch (cdclk) {
  418. case GT_CDCLK_337:
  419. cdset = 337;
  420. lpcll = (1 << 27);
  421. pwctl = 2;
  422. dpdiv = 169;
  423. break;
  424. case GT_CDCLK_450:
  425. cdset = 449;
  426. lpcll = 0;
  427. pwctl = 0;
  428. dpdiv = 225;
  429. break;
  430. case GT_CDCLK_540:
  431. cdset = 539;
  432. lpcll = (1 << 26);
  433. pwctl = 1;
  434. dpdiv = 270;
  435. break;
  436. case GT_CDCLK_675:
  437. cdset = 674;
  438. lpcll = (1 << 26) | (1 << 27);
  439. pwctl = 3;
  440. dpdiv = 338;
  441. break;
  442. default:
  443. ret = -EDOM;
  444. goto err;
  445. }
  446. debug("%s: frequency = %d\n", __func__, cdclk);
  447. /* Set LPCLL_CTL CD Clock Frequency Select */
  448. gtt_clrsetbits(priv, 0x130040, ~0xf3ffffff, lpcll);
  449. /* Inform power controller of selected frequency */
  450. gtt_write(priv, 0x138128, pwctl);
  451. gtt_write(priv, 0x13812c, 0);
  452. gtt_write(priv, 0x138124, 0x80000017);
  453. /* Program CD Clock Frequency */
  454. gtt_clrsetbits(priv, 0x46200, ~0xfffffc00, cdset);
  455. /* Set CPU DP AUX 2X bit clock dividers */
  456. gtt_clrsetbits(priv, 0x64010, ~0xfffff800, dpdiv);
  457. gtt_clrsetbits(priv, 0x64810, ~0xfffff800, dpdiv);
  458. return 0;
  459. err:
  460. debug("%s: ret=%d\n", __func__, ret);
  461. return ret;
  462. }
  463. u8 systemagent_revision(struct udevice *bus)
  464. {
  465. ulong val;
  466. pci_bus_read_config(bus, PCI_BDF(0, 0, 0), PCI_REVISION_ID, &val,
  467. PCI_SIZE_32);
  468. return val;
  469. }
  470. static int igd_pre_init(struct udevice *dev, bool is_broadwell)
  471. {
  472. struct broadwell_igd_plat *plat = dev_get_platdata(dev);
  473. struct broadwell_igd_priv *priv = dev_get_priv(dev);
  474. u32 rp1_gfx_freq;
  475. int ret;
  476. mdelay(plat->pre_graphics_delay);
  477. /* Early init steps */
  478. if (is_broadwell) {
  479. ret = broadwell_early_init(dev);
  480. if (ret)
  481. goto err;
  482. /* Set GFXPAUSE based on stepping */
  483. if (cpu_get_stepping() <= (CPUID_BROADWELL_E0 & 0xf) &&
  484. systemagent_revision(pci_get_controller(dev)) <= 9) {
  485. gtt_write(priv, 0xa000, 0x300ff);
  486. } else {
  487. gtt_write(priv, 0xa000, 0x30020);
  488. }
  489. } else {
  490. ret = haswell_early_init(dev);
  491. if (ret)
  492. goto err;
  493. }
  494. /* Set RP1 graphics frequency */
  495. rp1_gfx_freq = (readl(MCHBAR_REG(0x5998)) >> 8) & 0xff;
  496. gtt_write(priv, 0xa008, rp1_gfx_freq << 24);
  497. /* Post VBIOS panel setup */
  498. igd_setup_panel(dev);
  499. return 0;
  500. err:
  501. debug("%s: ret=%d\n", __func__, ret);
  502. return ret;
  503. }
  504. static int igd_post_init(struct udevice *dev, bool is_broadwell)
  505. {
  506. int ret;
  507. /* Late init steps */
  508. if (is_broadwell) {
  509. ret = igd_cdclk_init_broadwell(dev);
  510. if (ret)
  511. return ret;
  512. ret = broadwell_late_init(dev);
  513. if (ret)
  514. return ret;
  515. } else {
  516. igd_cdclk_init_haswell(dev);
  517. ret = haswell_late_init(dev);
  518. if (ret)
  519. return ret;
  520. }
  521. return 0;
  522. }
  523. static int broadwell_igd_int15_handler(void)
  524. {
  525. int res = 0;
  526. debug("%s: INT15 function %04x!\n", __func__, M.x86.R_AX);
  527. switch (M.x86.R_AX) {
  528. case 0x5f35:
  529. /*
  530. * Boot Display Device Hook:
  531. * bit 0 = CRT
  532. * bit 1 = TV (eDP)
  533. * bit 2 = EFP
  534. * bit 3 = LFP
  535. * bit 4 = CRT2
  536. * bit 5 = TV2 (eDP)
  537. * bit 6 = EFP2
  538. * bit 7 = LFP2
  539. */
  540. M.x86.R_AX = 0x005f;
  541. M.x86.R_CX = 0x0000; /* Use video bios default */
  542. res = 1;
  543. break;
  544. default:
  545. debug("Unknown INT15 function %04x!\n", M.x86.R_AX);
  546. break;
  547. }
  548. return res;
  549. }
  550. static int broadwell_igd_probe(struct udevice *dev)
  551. {
  552. struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
  553. struct video_priv *uc_priv = dev_get_uclass_priv(dev);
  554. bool is_broadwell;
  555. ulong fbbase;
  556. int ret;
  557. if (!ll_boot_init()) {
  558. /*
  559. * If we are running from EFI or coreboot, this driver can't
  560. * work.
  561. */
  562. printf("Not available (previous bootloader prevents it)\n");
  563. return -EPERM;
  564. }
  565. is_broadwell = cpu_get_family_model() == BROADWELL_FAMILY_ULT;
  566. bootstage_start(BOOTSTAGE_ID_ACCUM_LCD, "vesa display");
  567. debug("%s: is_broadwell=%d\n", __func__, is_broadwell);
  568. ret = igd_pre_init(dev, is_broadwell);
  569. if (!ret) {
  570. ret = vbe_setup_video(dev, broadwell_igd_int15_handler);
  571. if (ret)
  572. debug("failed to run video BIOS: %d\n", ret);
  573. }
  574. if (!ret)
  575. ret = igd_post_init(dev, is_broadwell);
  576. bootstage_accum(BOOTSTAGE_ID_ACCUM_LCD);
  577. if (ret)
  578. return ret;
  579. /* Use write-combining for the graphics memory, 256MB */
  580. fbbase = IS_ENABLED(CONFIG_VIDEO_COPY) ? plat->copy_base : plat->base;
  581. ret = mtrr_add_request(MTRR_TYPE_WRCOMB, fbbase, 256 << 20);
  582. if (!ret)
  583. ret = mtrr_commit(true);
  584. if (ret && ret != -ENOSYS) {
  585. printf("Failed to add MTRR: Display will be slow (err %d)\n",
  586. ret);
  587. }
  588. debug("fb=%lx, size %x, display size=%d %d %d\n", plat->base,
  589. plat->size, uc_priv->xsize, uc_priv->ysize, uc_priv->bpix);
  590. return 0;
  591. }
  592. static int broadwell_igd_ofdata_to_platdata(struct udevice *dev)
  593. {
  594. struct broadwell_igd_plat *plat = dev_get_platdata(dev);
  595. struct broadwell_igd_priv *priv = dev_get_priv(dev);
  596. int node = dev_of_offset(dev);
  597. const void *blob = gd->fdt_blob;
  598. if (fdtdec_get_int_array(blob, node, "intel,dp-hotplug",
  599. plat->dp_hotplug,
  600. ARRAY_SIZE(plat->dp_hotplug)))
  601. return -EINVAL;
  602. plat->port_select = fdtdec_get_int(blob, node, "intel,port-select", 0);
  603. plat->power_cycle_delay = fdtdec_get_int(blob, node,
  604. "intel,power-cycle-delay", 0);
  605. plat->power_up_delay = fdtdec_get_int(blob, node,
  606. "intel,power-up-delay", 0);
  607. plat->power_down_delay = fdtdec_get_int(blob, node,
  608. "intel,power-down-delay", 0);
  609. plat->power_backlight_on_delay = fdtdec_get_int(blob, node,
  610. "intel,power-backlight-on-delay", 0);
  611. plat->power_backlight_off_delay = fdtdec_get_int(blob, node,
  612. "intel,power-backlight-off-delay", 0);
  613. plat->cpu_backlight = fdtdec_get_int(blob, node,
  614. "intel,cpu-backlight", 0);
  615. plat->pch_backlight = fdtdec_get_int(blob, node,
  616. "intel,pch-backlight", 0);
  617. plat->pre_graphics_delay = fdtdec_get_int(blob, node,
  618. "intel,pre-graphics-delay", 0);
  619. priv->regs = (u8 *)dm_pci_read_bar32(dev, 0);
  620. debug("%s: regs at %p\n", __func__, priv->regs);
  621. debug("dp_hotplug %d %d %d\n", plat->dp_hotplug[0], plat->dp_hotplug[1],
  622. plat->dp_hotplug[2]);
  623. debug("port_select = %d\n", plat->port_select);
  624. debug("power_up_delay = %d\n", plat->power_up_delay);
  625. debug("power_backlight_on_delay = %d\n",
  626. plat->power_backlight_on_delay);
  627. debug("power_down_delay = %d\n", plat->power_down_delay);
  628. debug("power_backlight_off_delay = %d\n",
  629. plat->power_backlight_off_delay);
  630. debug("power_cycle_delay = %d\n", plat->power_cycle_delay);
  631. debug("cpu_backlight = %x\n", plat->cpu_backlight);
  632. debug("pch_backlight = %x\n", plat->pch_backlight);
  633. debug("cdclk = %d\n", plat->cdclk);
  634. debug("pre_graphics_delay = %d\n", plat->pre_graphics_delay);
  635. return 0;
  636. }
  637. static int broadwell_igd_bind(struct udevice *dev)
  638. {
  639. struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
  640. /* Set the maximum supported resolution */
  641. uc_plat->size = 2560 * 1600 * 4;
  642. log_debug("%s: Frame buffer size %x\n", __func__, uc_plat->size);
  643. return 0;
  644. }
  645. static const struct video_ops broadwell_igd_ops = {
  646. };
  647. static const struct udevice_id broadwell_igd_ids[] = {
  648. { .compatible = "intel,broadwell-igd" },
  649. { }
  650. };
  651. U_BOOT_DRIVER(broadwell_igd) = {
  652. .name = "broadwell_igd",
  653. .id = UCLASS_VIDEO,
  654. .of_match = broadwell_igd_ids,
  655. .ops = &broadwell_igd_ops,
  656. .ofdata_to_platdata = broadwell_igd_ofdata_to_platdata,
  657. .bind = broadwell_igd_bind,
  658. .probe = broadwell_igd_probe,
  659. .priv_auto_alloc_size = sizeof(struct broadwell_igd_priv),
  660. .platdata_auto_alloc_size = sizeof(struct broadwell_igd_plat),
  661. };