tsc_timer.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2012 The Chromium OS Authors.
  4. *
  5. * TSC calibration codes are adapted from Linux kernel
  6. * arch/x86/kernel/tsc_msr.c and arch/x86/kernel/tsc.c
  7. */
  8. #include <common.h>
  9. #include <bootstage.h>
  10. #include <dm.h>
  11. #include <log.h>
  12. #include <malloc.h>
  13. #include <time.h>
  14. #include <timer.h>
  15. #include <asm/cpu.h>
  16. #include <asm/io.h>
  17. #include <asm/i8254.h>
  18. #include <asm/ibmpc.h>
  19. #include <asm/msr.h>
  20. #include <asm/u-boot-x86.h>
  21. #include <linux/delay.h>
  22. #define MAX_NUM_FREQS 9
  23. #define INTEL_FAM6_SKYLAKE_MOBILE 0x4E
  24. #define INTEL_FAM6_ATOM_GOLDMONT 0x5C /* Apollo Lake */
  25. #define INTEL_FAM6_SKYLAKE_DESKTOP 0x5E
  26. #define INTEL_FAM6_ATOM_GOLDMONT_X 0x5F /* Denverton */
  27. #define INTEL_FAM6_KABYLAKE_MOBILE 0x8E
  28. #define INTEL_FAM6_KABYLAKE_DESKTOP 0x9E
  29. DECLARE_GLOBAL_DATA_PTR;
  30. /*
  31. * native_calibrate_tsc
  32. * Determine TSC frequency via CPUID, else return 0.
  33. */
  34. static unsigned long native_calibrate_tsc(void)
  35. {
  36. struct cpuid_result tsc_info;
  37. unsigned int crystal_freq;
  38. if (gd->arch.x86_vendor != X86_VENDOR_INTEL)
  39. return 0;
  40. if (cpuid_eax(0) < 0x15)
  41. return 0;
  42. tsc_info = cpuid(0x15);
  43. if (tsc_info.ebx == 0 || tsc_info.eax == 0)
  44. return 0;
  45. crystal_freq = tsc_info.ecx / 1000;
  46. if (!CONFIG_IS_ENABLED(X86_TSC_TIMER_NATIVE) && !crystal_freq) {
  47. switch (gd->arch.x86_model) {
  48. case INTEL_FAM6_SKYLAKE_MOBILE:
  49. case INTEL_FAM6_SKYLAKE_DESKTOP:
  50. case INTEL_FAM6_KABYLAKE_MOBILE:
  51. case INTEL_FAM6_KABYLAKE_DESKTOP:
  52. crystal_freq = 24000; /* 24.0 MHz */
  53. break;
  54. case INTEL_FAM6_ATOM_GOLDMONT_X:
  55. crystal_freq = 25000; /* 25.0 MHz */
  56. break;
  57. case INTEL_FAM6_ATOM_GOLDMONT:
  58. crystal_freq = 19200; /* 19.2 MHz */
  59. break;
  60. default:
  61. return 0;
  62. }
  63. }
  64. return (crystal_freq * tsc_info.ebx / tsc_info.eax) / 1000;
  65. }
  66. static unsigned long cpu_mhz_from_cpuid(void)
  67. {
  68. if (gd->arch.x86_vendor != X86_VENDOR_INTEL)
  69. return 0;
  70. if (cpuid_eax(0) < 0x16)
  71. return 0;
  72. return cpuid_eax(0x16);
  73. }
  74. /*
  75. * According to Intel 64 and IA-32 System Programming Guide,
  76. * if MSR_PERF_STAT[31] is set, the maximum resolved bus ratio can be
  77. * read in MSR_PLATFORM_ID[12:8], otherwise in MSR_PERF_STAT[44:40].
  78. * Unfortunately some Intel Atom SoCs aren't quite compliant to this,
  79. * so we need manually differentiate SoC families. This is what the
  80. * field msr_plat does.
  81. */
  82. struct freq_desc {
  83. u8 x86_family; /* CPU family */
  84. u8 x86_model; /* model */
  85. /* 2: use 100MHz, 1: use MSR_PLATFORM_INFO, 0: MSR_IA32_PERF_STATUS */
  86. u8 msr_plat;
  87. u32 freqs[MAX_NUM_FREQS];
  88. };
  89. static struct freq_desc freq_desc_tables[] = {
  90. /* PNW */
  91. { 6, 0x27, 0, { 0, 0, 0, 0, 0, 99840, 0, 83200, 0 } },
  92. /* CLV+ */
  93. { 6, 0x35, 0, { 0, 133200, 0, 0, 0, 99840, 0, 83200, 0 } },
  94. /* TNG - Intel Atom processor Z3400 series */
  95. { 6, 0x4a, 1, { 0, 100000, 133300, 0, 0, 0, 0, 0, 0 } },
  96. /* VLV2 - Intel Atom processor E3000, Z3600, Z3700 series */
  97. { 6, 0x37, 1, { 83300, 100000, 133300, 116700, 80000, 0, 0, 0, 0 } },
  98. /* ANN - Intel Atom processor Z3500 series */
  99. { 6, 0x5a, 1, { 83300, 100000, 133300, 100000, 0, 0, 0, 0, 0 } },
  100. /* AMT - Intel Atom processor X7-Z8000 and X5-Z8000 series */
  101. { 6, 0x4c, 1, { 83300, 100000, 133300, 116700,
  102. 80000, 93300, 90000, 88900, 87500 } },
  103. /* Ivybridge */
  104. { 6, 0x3a, 2, { 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
  105. };
  106. static int match_cpu(u8 family, u8 model)
  107. {
  108. int i;
  109. for (i = 0; i < ARRAY_SIZE(freq_desc_tables); i++) {
  110. if ((family == freq_desc_tables[i].x86_family) &&
  111. (model == freq_desc_tables[i].x86_model))
  112. return i;
  113. }
  114. return -1;
  115. }
  116. /* Map CPU reference clock freq ID(0-7) to CPU reference clock freq(KHz) */
  117. #define id_to_freq(cpu_index, freq_id) \
  118. (freq_desc_tables[cpu_index].freqs[freq_id])
  119. /*
  120. * TSC on Intel Atom SoCs capable of determining TSC frequency by MSR is
  121. * reliable and the frequency is known (provided by HW).
  122. *
  123. * On these platforms PIT/HPET is generally not available so calibration won't
  124. * work at all and there is no other clocksource to act as a watchdog for the
  125. * TSC, so we have no other choice than to trust it.
  126. *
  127. * Returns the TSC frequency in MHz or 0 if HW does not provide it.
  128. */
  129. static unsigned long __maybe_unused cpu_mhz_from_msr(void)
  130. {
  131. u32 lo, hi, ratio, freq_id, freq;
  132. unsigned long res;
  133. int cpu_index;
  134. if (gd->arch.x86_vendor != X86_VENDOR_INTEL)
  135. return 0;
  136. cpu_index = match_cpu(gd->arch.x86, gd->arch.x86_model);
  137. if (cpu_index < 0)
  138. return 0;
  139. if (freq_desc_tables[cpu_index].msr_plat) {
  140. rdmsr(MSR_PLATFORM_INFO, lo, hi);
  141. ratio = (lo >> 8) & 0xff;
  142. } else {
  143. rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
  144. ratio = (hi >> 8) & 0x1f;
  145. }
  146. debug("Maximum core-clock to bus-clock ratio: 0x%x\n", ratio);
  147. if (freq_desc_tables[cpu_index].msr_plat == 2) {
  148. /* TODO: Figure out how best to deal with this */
  149. freq = 100000;
  150. debug("Using frequency: %u KHz\n", freq);
  151. } else {
  152. /* Get FSB FREQ ID */
  153. rdmsr(MSR_FSB_FREQ, lo, hi);
  154. freq_id = lo & 0x7;
  155. freq = id_to_freq(cpu_index, freq_id);
  156. debug("Resolved frequency ID: %u, frequency: %u KHz\n",
  157. freq_id, freq);
  158. }
  159. /* TSC frequency = maximum resolved freq * maximum resolved bus ratio */
  160. res = freq * ratio / 1000;
  161. debug("TSC runs at %lu MHz\n", res);
  162. return res;
  163. }
  164. /*
  165. * This reads the current MSB of the PIT counter, and
  166. * checks if we are running on sufficiently fast and
  167. * non-virtualized hardware.
  168. *
  169. * Our expectations are:
  170. *
  171. * - the PIT is running at roughly 1.19MHz
  172. *
  173. * - each IO is going to take about 1us on real hardware,
  174. * but we allow it to be much faster (by a factor of 10) or
  175. * _slightly_ slower (ie we allow up to a 2us read+counter
  176. * update - anything else implies a unacceptably slow CPU
  177. * or PIT for the fast calibration to work.
  178. *
  179. * - with 256 PIT ticks to read the value, we have 214us to
  180. * see the same MSB (and overhead like doing a single TSC
  181. * read per MSB value etc).
  182. *
  183. * - We're doing 2 reads per loop (LSB, MSB), and we expect
  184. * them each to take about a microsecond on real hardware.
  185. * So we expect a count value of around 100. But we'll be
  186. * generous, and accept anything over 50.
  187. *
  188. * - if the PIT is stuck, and we see *many* more reads, we
  189. * return early (and the next caller of pit_expect_msb()
  190. * then consider it a failure when they don't see the
  191. * next expected value).
  192. *
  193. * These expectations mean that we know that we have seen the
  194. * transition from one expected value to another with a fairly
  195. * high accuracy, and we didn't miss any events. We can thus
  196. * use the TSC value at the transitions to calculate a pretty
  197. * good value for the TSC frequencty.
  198. */
  199. static inline int pit_verify_msb(unsigned char val)
  200. {
  201. /* Ignore LSB */
  202. inb(0x42);
  203. return inb(0x42) == val;
  204. }
  205. static inline int pit_expect_msb(unsigned char val, u64 *tscp,
  206. unsigned long *deltap)
  207. {
  208. int count;
  209. u64 tsc = 0, prev_tsc = 0;
  210. for (count = 0; count < 50000; count++) {
  211. if (!pit_verify_msb(val))
  212. break;
  213. prev_tsc = tsc;
  214. tsc = rdtsc();
  215. }
  216. *deltap = rdtsc() - prev_tsc;
  217. *tscp = tsc;
  218. /*
  219. * We require _some_ success, but the quality control
  220. * will be based on the error terms on the TSC values.
  221. */
  222. return count > 5;
  223. }
  224. /*
  225. * How many MSB values do we want to see? We aim for
  226. * a maximum error rate of 500ppm (in practice the
  227. * real error is much smaller), but refuse to spend
  228. * more than 50ms on it.
  229. */
  230. #define MAX_QUICK_PIT_MS 50
  231. #define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256)
  232. static unsigned long __maybe_unused quick_pit_calibrate(void)
  233. {
  234. int i;
  235. u64 tsc, delta;
  236. unsigned long d1, d2;
  237. /* Set the Gate high, disable speaker */
  238. outb((inb(0x61) & ~0x02) | 0x01, 0x61);
  239. /*
  240. * Counter 2, mode 0 (one-shot), binary count
  241. *
  242. * NOTE! Mode 2 decrements by two (and then the
  243. * output is flipped each time, giving the same
  244. * final output frequency as a decrement-by-one),
  245. * so mode 0 is much better when looking at the
  246. * individual counts.
  247. */
  248. outb(0xb0, 0x43);
  249. /* Start at 0xffff */
  250. outb(0xff, 0x42);
  251. outb(0xff, 0x42);
  252. /*
  253. * The PIT starts counting at the next edge, so we
  254. * need to delay for a microsecond. The easiest way
  255. * to do that is to just read back the 16-bit counter
  256. * once from the PIT.
  257. */
  258. pit_verify_msb(0);
  259. if (pit_expect_msb(0xff, &tsc, &d1)) {
  260. for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) {
  261. if (!pit_expect_msb(0xff-i, &delta, &d2))
  262. break;
  263. /*
  264. * Iterate until the error is less than 500 ppm
  265. */
  266. delta -= tsc;
  267. if (d1+d2 >= delta >> 11)
  268. continue;
  269. /*
  270. * Check the PIT one more time to verify that
  271. * all TSC reads were stable wrt the PIT.
  272. *
  273. * This also guarantees serialization of the
  274. * last cycle read ('d2') in pit_expect_msb.
  275. */
  276. if (!pit_verify_msb(0xfe - i))
  277. break;
  278. goto success;
  279. }
  280. }
  281. debug("Fast TSC calibration failed\n");
  282. return 0;
  283. success:
  284. /*
  285. * Ok, if we get here, then we've seen the
  286. * MSB of the PIT decrement 'i' times, and the
  287. * error has shrunk to less than 500 ppm.
  288. *
  289. * As a result, we can depend on there not being
  290. * any odd delays anywhere, and the TSC reads are
  291. * reliable (within the error).
  292. *
  293. * kHz = ticks / time-in-seconds / 1000;
  294. * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000
  295. * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000)
  296. */
  297. delta *= PIT_TICK_RATE;
  298. delta /= (i*256*1000);
  299. debug("Fast TSC calibration using PIT\n");
  300. return delta / 1000;
  301. }
  302. /* Get the speed of the TSC timer in MHz */
  303. unsigned notrace long get_tbclk_mhz(void)
  304. {
  305. return get_tbclk() / 1000000;
  306. }
  307. static ulong get_ms_timer(void)
  308. {
  309. return (get_ticks() * 1000) / get_tbclk();
  310. }
  311. ulong get_timer(ulong base)
  312. {
  313. return get_ms_timer() - base;
  314. }
  315. ulong notrace timer_get_us(void)
  316. {
  317. return get_ticks() / get_tbclk_mhz();
  318. }
  319. ulong timer_get_boot_us(void)
  320. {
  321. return timer_get_us();
  322. }
  323. void __udelay(unsigned long usec)
  324. {
  325. u64 now = get_ticks();
  326. u64 stop;
  327. stop = now + usec * get_tbclk_mhz();
  328. while ((int64_t)(stop - get_ticks()) > 0)
  329. #if defined(CONFIG_QEMU) && defined(CONFIG_SMP)
  330. /*
  331. * Add a 'pause' instruction on qemu target,
  332. * to give other VCPUs a chance to run.
  333. */
  334. asm volatile("pause");
  335. #else
  336. ;
  337. #endif
  338. }
  339. static int tsc_timer_get_count(struct udevice *dev, u64 *count)
  340. {
  341. u64 now_tick = rdtsc();
  342. *count = now_tick - gd->arch.tsc_base;
  343. return 0;
  344. }
  345. static void tsc_timer_ensure_setup(bool early)
  346. {
  347. if (gd->arch.tsc_inited)
  348. return;
  349. if (IS_ENABLED(CONFIG_X86_TSC_READ_BASE))
  350. gd->arch.tsc_base = rdtsc();
  351. if (!gd->arch.clock_rate) {
  352. unsigned long fast_calibrate;
  353. fast_calibrate = native_calibrate_tsc();
  354. if (fast_calibrate)
  355. goto done;
  356. /* Reduce code size by dropping other methods */
  357. if (CONFIG_IS_ENABLED(X86_TSC_TIMER_NATIVE))
  358. panic("no timer");
  359. fast_calibrate = cpu_mhz_from_cpuid();
  360. if (fast_calibrate)
  361. goto done;
  362. fast_calibrate = cpu_mhz_from_msr();
  363. if (fast_calibrate)
  364. goto done;
  365. fast_calibrate = quick_pit_calibrate();
  366. if (fast_calibrate)
  367. goto done;
  368. if (early)
  369. fast_calibrate = CONFIG_X86_TSC_TIMER_EARLY_FREQ;
  370. else
  371. return;
  372. done:
  373. gd->arch.clock_rate = fast_calibrate * 1000000;
  374. }
  375. gd->arch.tsc_inited = true;
  376. }
  377. static int tsc_timer_probe(struct udevice *dev)
  378. {
  379. struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
  380. /* Try hardware calibration first */
  381. tsc_timer_ensure_setup(false);
  382. if (!gd->arch.clock_rate) {
  383. /*
  384. * Use the clock frequency specified in the
  385. * device tree as last resort
  386. */
  387. if (!uc_priv->clock_rate)
  388. panic("TSC frequency is ZERO");
  389. } else {
  390. uc_priv->clock_rate = gd->arch.clock_rate;
  391. }
  392. return 0;
  393. }
  394. unsigned long notrace timer_early_get_rate(void)
  395. {
  396. /*
  397. * When TSC timer is used as the early timer, be warned that the timer
  398. * clock rate can only be calibrated via some hardware ways. Specifying
  399. * it in the device tree won't work for the early timer.
  400. */
  401. tsc_timer_ensure_setup(true);
  402. return gd->arch.clock_rate;
  403. }
  404. u64 notrace timer_early_get_count(void)
  405. {
  406. tsc_timer_ensure_setup(true);
  407. return rdtsc() - gd->arch.tsc_base;
  408. }
  409. static const struct timer_ops tsc_timer_ops = {
  410. .get_count = tsc_timer_get_count,
  411. };
  412. static const struct udevice_id tsc_timer_ids[] = {
  413. { .compatible = "x86,tsc-timer", },
  414. { }
  415. };
  416. U_BOOT_DRIVER(tsc_timer) = {
  417. .name = "tsc_timer",
  418. .id = UCLASS_TIMER,
  419. .of_match = tsc_timer_ids,
  420. .probe = tsc_timer_probe,
  421. .ops = &tsc_timer_ops,
  422. };