atcpit100_timer.c 2.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Andestech ATCPIT100 timer driver
  4. *
  5. * (C) Copyright 2016
  6. * Rick Chen, NDS32 Software Engineering, rick@andestech.com
  7. */
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <errno.h>
  11. #include <timer.h>
  12. #include <linux/io.h>
  13. #define REG32_TMR(x) (*(u32 *) ((plat->regs) + (x>>2)))
  14. /*
  15. * Definition of register offsets
  16. */
  17. /* ID and Revision Register */
  18. #define ID_REV 0x0
  19. /* Configuration Register */
  20. #define CFG 0x10
  21. /* Interrupt Enable Register */
  22. #define INT_EN 0x14
  23. #define CH_INT_EN(c , i) ((1<<i)<<(4*c))
  24. /* Interrupt Status Register */
  25. #define INT_STA 0x18
  26. #define CH_INT_STA(c , i) ((1<<i)<<(4*c))
  27. /* Channel Enable Register */
  28. #define CH_EN 0x1C
  29. #define CH_TMR_EN(c , t) ((1<<t)<<(4*c))
  30. /* Ch n Control REgister */
  31. #define CH_CTL(n) (0x20+0x10*n)
  32. /* Channel clock source , bit 3 , 0:External clock , 1:APB clock */
  33. #define APB_CLK (1<<3)
  34. /* Channel mode , bit 0~2 */
  35. #define TMR_32 1
  36. #define TMR_16 2
  37. #define TMR_8 3
  38. #define PWM 4
  39. #define CH_REL(n) (0x24+0x10*n)
  40. #define CH_CNT(n) (0x28+0x10*n)
  41. struct atctmr_timer_regs {
  42. u32 id_rev; /* 0x00 */
  43. u32 reservd[3]; /* 0x04 ~ 0x0c */
  44. u32 cfg; /* 0x10 */
  45. u32 int_en; /* 0x14 */
  46. u32 int_st; /* 0x18 */
  47. u32 ch_en; /* 0x1c */
  48. u32 ch0_ctrl; /* 0x20 */
  49. u32 ch0_reload; /* 0x24 */
  50. u32 ch0_cntr; /* 0x28 */
  51. u32 reservd1; /* 0x2c */
  52. u32 ch1_ctrl; /* 0x30 */
  53. u32 ch1_reload; /* 0x34 */
  54. u32 int_mask; /* 0x38 */
  55. };
  56. struct atcpit_timer_platdata {
  57. u32 *regs;
  58. };
  59. static int atcpit_timer_get_count(struct udevice *dev, u64 *count)
  60. {
  61. struct atcpit_timer_platdata *plat = dev_get_platdata(dev);
  62. u32 val;
  63. val = ~(REG32_TMR(CH_CNT(1))+0xffffffff);
  64. *count = timer_conv_64(val);
  65. return 0;
  66. }
  67. static int atcpit_timer_probe(struct udevice *dev)
  68. {
  69. struct atcpit_timer_platdata *plat = dev_get_platdata(dev);
  70. REG32_TMR(CH_REL(1)) = 0xffffffff;
  71. REG32_TMR(CH_CTL(1)) = APB_CLK|TMR_32;
  72. REG32_TMR(CH_EN) |= CH_TMR_EN(1 , 0);
  73. return 0;
  74. }
  75. static int atcpit_timer_ofdata_to_platdata(struct udevice *dev)
  76. {
  77. struct atcpit_timer_platdata *plat = dev_get_platdata(dev);
  78. plat->regs = map_physmem(dev_read_addr(dev), 0x100 , MAP_NOCACHE);
  79. return 0;
  80. }
  81. static const struct timer_ops atcpit_timer_ops = {
  82. .get_count = atcpit_timer_get_count,
  83. };
  84. static const struct udevice_id atcpit_timer_ids[] = {
  85. { .compatible = "andestech,atcpit100" },
  86. {}
  87. };
  88. U_BOOT_DRIVER(atcpit100_timer) = {
  89. .name = "atcpit100_timer",
  90. .id = UCLASS_TIMER,
  91. .of_match = atcpit_timer_ids,
  92. .ofdata_to_platdata = atcpit_timer_ofdata_to_platdata,
  93. .platdata_auto_alloc_size = sizeof(struct atcpit_timer_platdata),
  94. .probe = atcpit_timer_probe,
  95. .ops = &atcpit_timer_ops,
  96. };