zynq_qspi.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2013 Xilinx, Inc.
  4. * (C) Copyright 2015 Jagan Teki <jteki@openedev.com>
  5. *
  6. * Xilinx Zynq Quad-SPI(QSPI) controller driver (master mode only)
  7. */
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <log.h>
  11. #include <malloc.h>
  12. #include <spi.h>
  13. #include <asm/io.h>
  14. #include <linux/bitops.h>
  15. DECLARE_GLOBAL_DATA_PTR;
  16. /* zynq qspi register bit masks ZYNQ_QSPI_<REG>_<BIT>_MASK */
  17. #define ZYNQ_QSPI_CR_IFMODE_MASK BIT(31) /* Flash intrface mode*/
  18. #define ZYNQ_QSPI_CR_MSA_MASK BIT(15) /* Manual start enb */
  19. #define ZYNQ_QSPI_CR_MCS_MASK BIT(14) /* Manual chip select */
  20. #define ZYNQ_QSPI_CR_PCS_MASK BIT(10) /* Peri chip select */
  21. #define ZYNQ_QSPI_CR_FW_MASK GENMASK(7, 6) /* FIFO width */
  22. #define ZYNQ_QSPI_CR_SS_MASK GENMASK(13, 10) /* Slave Select */
  23. #define ZYNQ_QSPI_CR_BAUD_MASK GENMASK(5, 3) /* Baud rate div */
  24. #define ZYNQ_QSPI_CR_CPHA_MASK BIT(2) /* Clock phase */
  25. #define ZYNQ_QSPI_CR_CPOL_MASK BIT(1) /* Clock polarity */
  26. #define ZYNQ_QSPI_CR_MSTREN_MASK BIT(0) /* Mode select */
  27. #define ZYNQ_QSPI_IXR_RXNEMPTY_MASK BIT(4) /* RX_FIFO_not_empty */
  28. #define ZYNQ_QSPI_IXR_TXOW_MASK BIT(2) /* TX_FIFO_not_full */
  29. #define ZYNQ_QSPI_IXR_ALL_MASK GENMASK(6, 0) /* All IXR bits */
  30. #define ZYNQ_QSPI_ENR_SPI_EN_MASK BIT(0) /* SPI Enable */
  31. #define ZYNQ_QSPI_LQSPICFG_LQMODE_MASK BIT(31) /* Linear QSPI Mode */
  32. /* zynq qspi Transmit Data Register */
  33. #define ZYNQ_QSPI_TXD_00_00_OFFSET 0x1C /* Transmit 4-byte inst */
  34. #define ZYNQ_QSPI_TXD_00_01_OFFSET 0x80 /* Transmit 1-byte inst */
  35. #define ZYNQ_QSPI_TXD_00_10_OFFSET 0x84 /* Transmit 2-byte inst */
  36. #define ZYNQ_QSPI_TXD_00_11_OFFSET 0x88 /* Transmit 3-byte inst */
  37. #define ZYNQ_QSPI_TXFIFO_THRESHOLD 1 /* Tx FIFO threshold level*/
  38. #define ZYNQ_QSPI_RXFIFO_THRESHOLD 32 /* Rx FIFO threshold level */
  39. #define ZYNQ_QSPI_CR_BAUD_MAX 8 /* Baud rate divisor max val */
  40. #define ZYNQ_QSPI_CR_BAUD_SHIFT 3 /* Baud rate divisor shift */
  41. #define ZYNQ_QSPI_CR_SS_SHIFT 10 /* Slave select shift */
  42. #define ZYNQ_QSPI_FIFO_DEPTH 63
  43. #define ZYNQ_QSPI_WAIT (CONFIG_SYS_HZ / 100) /* 10 ms */
  44. /* zynq qspi register set */
  45. struct zynq_qspi_regs {
  46. u32 cr; /* 0x00 */
  47. u32 isr; /* 0x04 */
  48. u32 ier; /* 0x08 */
  49. u32 idr; /* 0x0C */
  50. u32 imr; /* 0x10 */
  51. u32 enr; /* 0x14 */
  52. u32 dr; /* 0x18 */
  53. u32 txd0r; /* 0x1C */
  54. u32 drxr; /* 0x20 */
  55. u32 sicr; /* 0x24 */
  56. u32 txftr; /* 0x28 */
  57. u32 rxftr; /* 0x2C */
  58. u32 gpior; /* 0x30 */
  59. u32 reserved0[19];
  60. u32 txd1r; /* 0x80 */
  61. u32 txd2r; /* 0x84 */
  62. u32 txd3r; /* 0x88 */
  63. u32 reserved1[5];
  64. u32 lqspicfg; /* 0xA0 */
  65. u32 lqspists; /* 0xA4 */
  66. };
  67. /* zynq qspi platform data */
  68. struct zynq_qspi_platdata {
  69. struct zynq_qspi_regs *regs;
  70. u32 frequency; /* input frequency */
  71. u32 speed_hz;
  72. };
  73. /* zynq qspi priv */
  74. struct zynq_qspi_priv {
  75. struct zynq_qspi_regs *regs;
  76. u8 cs;
  77. u8 mode;
  78. u8 fifo_depth;
  79. u32 freq; /* required frequency */
  80. const void *tx_buf;
  81. void *rx_buf;
  82. unsigned len;
  83. int bytes_to_transfer;
  84. int bytes_to_receive;
  85. unsigned int is_inst;
  86. unsigned cs_change:1;
  87. };
  88. static int zynq_qspi_ofdata_to_platdata(struct udevice *bus)
  89. {
  90. struct zynq_qspi_platdata *plat = bus->platdata;
  91. const void *blob = gd->fdt_blob;
  92. int node = dev_of_offset(bus);
  93. plat->regs = (struct zynq_qspi_regs *)fdtdec_get_addr(blob,
  94. node, "reg");
  95. /* FIXME: Use 166MHz as a suitable default */
  96. plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
  97. 166666666);
  98. plat->speed_hz = plat->frequency / 2;
  99. debug("%s: regs=%p max-frequency=%d\n", __func__,
  100. plat->regs, plat->frequency);
  101. return 0;
  102. }
  103. static void zynq_qspi_init_hw(struct zynq_qspi_priv *priv)
  104. {
  105. struct zynq_qspi_regs *regs = priv->regs;
  106. u32 confr;
  107. /* Disable QSPI */
  108. writel(~ZYNQ_QSPI_ENR_SPI_EN_MASK, &regs->enr);
  109. /* Disable Interrupts */
  110. writel(ZYNQ_QSPI_IXR_ALL_MASK, &regs->idr);
  111. /* Clear the TX and RX threshold reg */
  112. writel(ZYNQ_QSPI_TXFIFO_THRESHOLD, &regs->txftr);
  113. writel(ZYNQ_QSPI_RXFIFO_THRESHOLD, &regs->rxftr);
  114. /* Clear the RX FIFO */
  115. while (readl(&regs->isr) & ZYNQ_QSPI_IXR_RXNEMPTY_MASK)
  116. readl(&regs->drxr);
  117. /* Clear Interrupts */
  118. writel(ZYNQ_QSPI_IXR_ALL_MASK, &regs->isr);
  119. /* Manual slave select and Auto start */
  120. confr = readl(&regs->cr);
  121. confr &= ~ZYNQ_QSPI_CR_MSA_MASK;
  122. confr |= ZYNQ_QSPI_CR_IFMODE_MASK | ZYNQ_QSPI_CR_MCS_MASK |
  123. ZYNQ_QSPI_CR_PCS_MASK | ZYNQ_QSPI_CR_FW_MASK |
  124. ZYNQ_QSPI_CR_MSTREN_MASK;
  125. writel(confr, &regs->cr);
  126. /* Disable the LQSPI feature */
  127. confr = readl(&regs->lqspicfg);
  128. confr &= ~ZYNQ_QSPI_LQSPICFG_LQMODE_MASK;
  129. writel(confr, &regs->lqspicfg);
  130. /* Enable SPI */
  131. writel(ZYNQ_QSPI_ENR_SPI_EN_MASK, &regs->enr);
  132. }
  133. static int zynq_qspi_probe(struct udevice *bus)
  134. {
  135. struct zynq_qspi_platdata *plat = dev_get_platdata(bus);
  136. struct zynq_qspi_priv *priv = dev_get_priv(bus);
  137. priv->regs = plat->regs;
  138. priv->fifo_depth = ZYNQ_QSPI_FIFO_DEPTH;
  139. /* init the zynq spi hw */
  140. zynq_qspi_init_hw(priv);
  141. return 0;
  142. }
  143. /*
  144. * zynq_qspi_read_data - Copy data to RX buffer
  145. * @zqspi: Pointer to the zynq_qspi structure
  146. * @data: The 32 bit variable where data is stored
  147. * @size: Number of bytes to be copied from data to RX buffer
  148. */
  149. static void zynq_qspi_read_data(struct zynq_qspi_priv *priv, u32 data, u8 size)
  150. {
  151. u8 byte3;
  152. debug("%s: data 0x%04x rx_buf addr: 0x%08x size %d\n", __func__ ,
  153. data, (unsigned)(priv->rx_buf), size);
  154. if (priv->rx_buf) {
  155. switch (size) {
  156. case 1:
  157. *((u8 *)priv->rx_buf) = data;
  158. priv->rx_buf += 1;
  159. break;
  160. case 2:
  161. *((u16 *)priv->rx_buf) = data;
  162. priv->rx_buf += 2;
  163. break;
  164. case 3:
  165. *((u16 *)priv->rx_buf) = data;
  166. priv->rx_buf += 2;
  167. byte3 = (u8)(data >> 16);
  168. *((u8 *)priv->rx_buf) = byte3;
  169. priv->rx_buf += 1;
  170. break;
  171. case 4:
  172. /* Can not assume word aligned buffer */
  173. memcpy(priv->rx_buf, &data, size);
  174. priv->rx_buf += 4;
  175. break;
  176. default:
  177. /* This will never execute */
  178. break;
  179. }
  180. }
  181. priv->bytes_to_receive -= size;
  182. if (priv->bytes_to_receive < 0)
  183. priv->bytes_to_receive = 0;
  184. }
  185. /*
  186. * zynq_qspi_write_data - Copy data from TX buffer
  187. * @zqspi: Pointer to the zynq_qspi structure
  188. * @data: Pointer to the 32 bit variable where data is to be copied
  189. * @size: Number of bytes to be copied from TX buffer to data
  190. */
  191. static void zynq_qspi_write_data(struct zynq_qspi_priv *priv,
  192. u32 *data, u8 size)
  193. {
  194. if (priv->tx_buf) {
  195. switch (size) {
  196. case 1:
  197. *data = *((u8 *)priv->tx_buf);
  198. priv->tx_buf += 1;
  199. *data |= 0xFFFFFF00;
  200. break;
  201. case 2:
  202. *data = *((u16 *)priv->tx_buf);
  203. priv->tx_buf += 2;
  204. *data |= 0xFFFF0000;
  205. break;
  206. case 3:
  207. *data = *((u16 *)priv->tx_buf);
  208. priv->tx_buf += 2;
  209. *data |= (*((u8 *)priv->tx_buf) << 16);
  210. priv->tx_buf += 1;
  211. *data |= 0xFF000000;
  212. break;
  213. case 4:
  214. /* Can not assume word aligned buffer */
  215. memcpy(data, priv->tx_buf, size);
  216. priv->tx_buf += 4;
  217. break;
  218. default:
  219. /* This will never execute */
  220. break;
  221. }
  222. } else {
  223. *data = 0;
  224. }
  225. debug("%s: data 0x%08x tx_buf addr: 0x%08x size %d\n", __func__,
  226. *data, (u32)priv->tx_buf, size);
  227. priv->bytes_to_transfer -= size;
  228. if (priv->bytes_to_transfer < 0)
  229. priv->bytes_to_transfer = 0;
  230. }
  231. static void zynq_qspi_chipselect(struct zynq_qspi_priv *priv, int is_on)
  232. {
  233. u32 confr;
  234. struct zynq_qspi_regs *regs = priv->regs;
  235. confr = readl(&regs->cr);
  236. if (is_on) {
  237. /* Select the slave */
  238. confr &= ~ZYNQ_QSPI_CR_SS_MASK;
  239. confr |= (~(1 << priv->cs) << ZYNQ_QSPI_CR_SS_SHIFT) &
  240. ZYNQ_QSPI_CR_SS_MASK;
  241. } else
  242. /* Deselect the slave */
  243. confr |= ZYNQ_QSPI_CR_SS_MASK;
  244. writel(confr, &regs->cr);
  245. }
  246. /*
  247. * zynq_qspi_fill_tx_fifo - Fills the TX FIFO with as many bytes as possible
  248. * @zqspi: Pointer to the zynq_qspi structure
  249. */
  250. static void zynq_qspi_fill_tx_fifo(struct zynq_qspi_priv *priv, u32 size)
  251. {
  252. u32 data = 0;
  253. u32 fifocount = 0;
  254. unsigned len, offset;
  255. struct zynq_qspi_regs *regs = priv->regs;
  256. static const unsigned offsets[4] = {
  257. ZYNQ_QSPI_TXD_00_00_OFFSET, ZYNQ_QSPI_TXD_00_01_OFFSET,
  258. ZYNQ_QSPI_TXD_00_10_OFFSET, ZYNQ_QSPI_TXD_00_11_OFFSET };
  259. while ((fifocount < size) &&
  260. (priv->bytes_to_transfer > 0)) {
  261. if (priv->bytes_to_transfer >= 4) {
  262. if (priv->tx_buf) {
  263. memcpy(&data, priv->tx_buf, 4);
  264. priv->tx_buf += 4;
  265. } else {
  266. data = 0;
  267. }
  268. writel(data, &regs->txd0r);
  269. priv->bytes_to_transfer -= 4;
  270. fifocount++;
  271. } else {
  272. /* Write TXD1, TXD2, TXD3 only if TxFIFO is empty. */
  273. if (!(readl(&regs->isr)
  274. & ZYNQ_QSPI_IXR_TXOW_MASK) &&
  275. !priv->rx_buf)
  276. return;
  277. len = priv->bytes_to_transfer;
  278. zynq_qspi_write_data(priv, &data, len);
  279. offset = (priv->rx_buf) ? offsets[0] : offsets[len];
  280. writel(data, &regs->cr + (offset / 4));
  281. }
  282. }
  283. }
  284. /*
  285. * zynq_qspi_irq_poll - Interrupt service routine of the QSPI controller
  286. * @zqspi: Pointer to the zynq_qspi structure
  287. *
  288. * This function handles TX empty and Mode Fault interrupts only.
  289. * On TX empty interrupt this function reads the received data from RX FIFO and
  290. * fills the TX FIFO if there is any data remaining to be transferred.
  291. * On Mode Fault interrupt this function indicates that transfer is completed,
  292. * the SPI subsystem will identify the error as the remaining bytes to be
  293. * transferred is non-zero.
  294. *
  295. * returns: 0 for poll timeout
  296. * 1 transfer operation complete
  297. */
  298. static int zynq_qspi_irq_poll(struct zynq_qspi_priv *priv)
  299. {
  300. struct zynq_qspi_regs *regs = priv->regs;
  301. u32 rxindex = 0;
  302. u32 rxcount;
  303. u32 status, timeout;
  304. /* Poll until any of the interrupt status bits are set */
  305. timeout = get_timer(0);
  306. do {
  307. status = readl(&regs->isr);
  308. } while ((status == 0) &&
  309. (get_timer(timeout) < ZYNQ_QSPI_WAIT));
  310. if (status == 0) {
  311. printf("zynq_qspi_irq_poll: Timeout!\n");
  312. return -ETIMEDOUT;
  313. }
  314. writel(status, &regs->isr);
  315. /* Disable all interrupts */
  316. writel(ZYNQ_QSPI_IXR_ALL_MASK, &regs->idr);
  317. if ((status & ZYNQ_QSPI_IXR_TXOW_MASK) ||
  318. (status & ZYNQ_QSPI_IXR_RXNEMPTY_MASK)) {
  319. /*
  320. * This bit is set when Tx FIFO has < THRESHOLD entries. We have
  321. * the THRESHOLD value set to 1, so this bit indicates Tx FIFO
  322. * is empty
  323. */
  324. rxcount = priv->bytes_to_receive - priv->bytes_to_transfer;
  325. rxcount = (rxcount % 4) ? ((rxcount/4)+1) : (rxcount/4);
  326. while ((rxindex < rxcount) &&
  327. (rxindex < ZYNQ_QSPI_RXFIFO_THRESHOLD)) {
  328. /* Read out the data from the RX FIFO */
  329. u32 data;
  330. data = readl(&regs->drxr);
  331. if (priv->bytes_to_receive >= 4) {
  332. if (priv->rx_buf) {
  333. memcpy(priv->rx_buf, &data, 4);
  334. priv->rx_buf += 4;
  335. }
  336. priv->bytes_to_receive -= 4;
  337. } else {
  338. zynq_qspi_read_data(priv, data,
  339. priv->bytes_to_receive);
  340. }
  341. rxindex++;
  342. }
  343. if (priv->bytes_to_transfer) {
  344. /* There is more data to send */
  345. zynq_qspi_fill_tx_fifo(priv,
  346. ZYNQ_QSPI_RXFIFO_THRESHOLD);
  347. writel(ZYNQ_QSPI_IXR_ALL_MASK, &regs->ier);
  348. } else {
  349. /*
  350. * If transfer and receive is completed then only send
  351. * complete signal
  352. */
  353. if (!priv->bytes_to_receive) {
  354. /* return operation complete */
  355. writel(ZYNQ_QSPI_IXR_ALL_MASK,
  356. &regs->idr);
  357. return 1;
  358. }
  359. }
  360. }
  361. return 0;
  362. }
  363. /*
  364. * zynq_qspi_start_transfer - Initiates the QSPI transfer
  365. * @qspi: Pointer to the spi_device structure
  366. * @transfer: Pointer to the spi_transfer structure which provide information
  367. * about next transfer parameters
  368. *
  369. * This function fills the TX FIFO, starts the QSPI transfer, and waits for the
  370. * transfer to be completed.
  371. *
  372. * returns: Number of bytes transferred in the last transfer
  373. */
  374. static int zynq_qspi_start_transfer(struct zynq_qspi_priv *priv)
  375. {
  376. u32 data = 0;
  377. struct zynq_qspi_regs *regs = priv->regs;
  378. debug("%s: qspi: 0x%08x transfer: 0x%08x len: %d\n", __func__,
  379. (u32)priv, (u32)priv, priv->len);
  380. priv->bytes_to_transfer = priv->len;
  381. priv->bytes_to_receive = priv->len;
  382. if (priv->len < 4)
  383. zynq_qspi_fill_tx_fifo(priv, priv->len);
  384. else
  385. zynq_qspi_fill_tx_fifo(priv, priv->fifo_depth);
  386. writel(ZYNQ_QSPI_IXR_ALL_MASK, &regs->ier);
  387. /* wait for completion */
  388. do {
  389. data = zynq_qspi_irq_poll(priv);
  390. } while (data == 0);
  391. return (priv->len) - (priv->bytes_to_transfer);
  392. }
  393. static int zynq_qspi_transfer(struct zynq_qspi_priv *priv)
  394. {
  395. unsigned cs_change = 1;
  396. int status = 0;
  397. while (1) {
  398. /* Select the chip if required */
  399. if (cs_change)
  400. zynq_qspi_chipselect(priv, 1);
  401. cs_change = priv->cs_change;
  402. if (!priv->tx_buf && !priv->rx_buf && priv->len) {
  403. status = -1;
  404. break;
  405. }
  406. /* Request the transfer */
  407. if (priv->len) {
  408. status = zynq_qspi_start_transfer(priv);
  409. priv->is_inst = 0;
  410. }
  411. if (status != priv->len) {
  412. if (status > 0)
  413. status = -EMSGSIZE;
  414. debug("zynq_qspi_transfer:%d len:%d\n",
  415. status, priv->len);
  416. break;
  417. }
  418. status = 0;
  419. if (cs_change)
  420. /* Deselect the chip */
  421. zynq_qspi_chipselect(priv, 0);
  422. break;
  423. }
  424. return status;
  425. }
  426. static int zynq_qspi_claim_bus(struct udevice *dev)
  427. {
  428. struct udevice *bus = dev->parent;
  429. struct zynq_qspi_priv *priv = dev_get_priv(bus);
  430. struct zynq_qspi_regs *regs = priv->regs;
  431. writel(ZYNQ_QSPI_ENR_SPI_EN_MASK, &regs->enr);
  432. return 0;
  433. }
  434. static int zynq_qspi_release_bus(struct udevice *dev)
  435. {
  436. struct udevice *bus = dev->parent;
  437. struct zynq_qspi_priv *priv = dev_get_priv(bus);
  438. struct zynq_qspi_regs *regs = priv->regs;
  439. writel(~ZYNQ_QSPI_ENR_SPI_EN_MASK, &regs->enr);
  440. return 0;
  441. }
  442. static int zynq_qspi_xfer(struct udevice *dev, unsigned int bitlen,
  443. const void *dout, void *din, unsigned long flags)
  444. {
  445. struct udevice *bus = dev->parent;
  446. struct zynq_qspi_priv *priv = dev_get_priv(bus);
  447. struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
  448. priv->cs = slave_plat->cs;
  449. priv->tx_buf = dout;
  450. priv->rx_buf = din;
  451. priv->len = bitlen / 8;
  452. debug("zynq_qspi_xfer: bus:%i cs:%i bitlen:%i len:%i flags:%lx\n",
  453. bus->seq, slave_plat->cs, bitlen, priv->len, flags);
  454. /*
  455. * Festering sore.
  456. * Assume that the beginning of a transfer with bits to
  457. * transmit must contain a device command.
  458. */
  459. if (dout && flags & SPI_XFER_BEGIN)
  460. priv->is_inst = 1;
  461. else
  462. priv->is_inst = 0;
  463. if (flags & SPI_XFER_END)
  464. priv->cs_change = 1;
  465. else
  466. priv->cs_change = 0;
  467. zynq_qspi_transfer(priv);
  468. return 0;
  469. }
  470. static int zynq_qspi_set_speed(struct udevice *bus, uint speed)
  471. {
  472. struct zynq_qspi_platdata *plat = bus->platdata;
  473. struct zynq_qspi_priv *priv = dev_get_priv(bus);
  474. struct zynq_qspi_regs *regs = priv->regs;
  475. uint32_t confr;
  476. u8 baud_rate_val = 0;
  477. if (speed > plat->frequency)
  478. speed = plat->frequency;
  479. /* Set the clock frequency */
  480. confr = readl(&regs->cr);
  481. if (speed == 0) {
  482. /* Set baudrate x8, if the freq is 0 */
  483. baud_rate_val = 0x2;
  484. } else if (plat->speed_hz != speed) {
  485. while ((baud_rate_val < ZYNQ_QSPI_CR_BAUD_MAX) &&
  486. ((plat->frequency /
  487. (2 << baud_rate_val)) > speed))
  488. baud_rate_val++;
  489. plat->speed_hz = speed / (2 << baud_rate_val);
  490. }
  491. confr &= ~ZYNQ_QSPI_CR_BAUD_MASK;
  492. confr |= (baud_rate_val << ZYNQ_QSPI_CR_BAUD_SHIFT);
  493. writel(confr, &regs->cr);
  494. priv->freq = speed;
  495. debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
  496. return 0;
  497. }
  498. static int zynq_qspi_set_mode(struct udevice *bus, uint mode)
  499. {
  500. struct zynq_qspi_priv *priv = dev_get_priv(bus);
  501. struct zynq_qspi_regs *regs = priv->regs;
  502. uint32_t confr;
  503. /* Set the SPI Clock phase and polarities */
  504. confr = readl(&regs->cr);
  505. confr &= ~(ZYNQ_QSPI_CR_CPHA_MASK | ZYNQ_QSPI_CR_CPOL_MASK);
  506. if (mode & SPI_CPHA)
  507. confr |= ZYNQ_QSPI_CR_CPHA_MASK;
  508. if (mode & SPI_CPOL)
  509. confr |= ZYNQ_QSPI_CR_CPOL_MASK;
  510. writel(confr, &regs->cr);
  511. priv->mode = mode;
  512. debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
  513. return 0;
  514. }
  515. static const struct dm_spi_ops zynq_qspi_ops = {
  516. .claim_bus = zynq_qspi_claim_bus,
  517. .release_bus = zynq_qspi_release_bus,
  518. .xfer = zynq_qspi_xfer,
  519. .set_speed = zynq_qspi_set_speed,
  520. .set_mode = zynq_qspi_set_mode,
  521. };
  522. static const struct udevice_id zynq_qspi_ids[] = {
  523. { .compatible = "xlnx,zynq-qspi-1.0" },
  524. { }
  525. };
  526. U_BOOT_DRIVER(zynq_qspi) = {
  527. .name = "zynq_qspi",
  528. .id = UCLASS_SPI,
  529. .of_match = zynq_qspi_ids,
  530. .ops = &zynq_qspi_ops,
  531. .ofdata_to_platdata = zynq_qspi_ofdata_to_platdata,
  532. .platdata_auto_alloc_size = sizeof(struct zynq_qspi_platdata),
  533. .priv_auto_alloc_size = sizeof(struct zynq_qspi_priv),
  534. .probe = zynq_qspi_probe,
  535. };