ti_qspi.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * TI QSPI driver
  4. *
  5. * Copyright (C) 2013, Texas Instruments, Incorporated
  6. */
  7. #include <common.h>
  8. #include <cpu_func.h>
  9. #include <log.h>
  10. #include <asm/cache.h>
  11. #include <asm/io.h>
  12. #include <asm/arch/omap.h>
  13. #include <malloc.h>
  14. #include <spi.h>
  15. #include <spi-mem.h>
  16. #include <dm.h>
  17. #include <asm/gpio.h>
  18. #include <asm/omap_gpio.h>
  19. #include <asm/omap_common.h>
  20. #include <asm/ti-common/ti-edma3.h>
  21. #include <linux/bitops.h>
  22. #include <linux/err.h>
  23. #include <linux/kernel.h>
  24. #include <regmap.h>
  25. #include <syscon.h>
  26. DECLARE_GLOBAL_DATA_PTR;
  27. /* ti qpsi register bit masks */
  28. #define QSPI_TIMEOUT 2000000
  29. #define QSPI_FCLK 192000000
  30. #define QSPI_DRA7XX_FCLK 76800000
  31. #define QSPI_WLEN_MAX_BITS 128
  32. #define QSPI_WLEN_MAX_BYTES (QSPI_WLEN_MAX_BITS >> 3)
  33. #define QSPI_WLEN_MASK QSPI_WLEN(QSPI_WLEN_MAX_BITS)
  34. /* clock control */
  35. #define QSPI_CLK_EN BIT(31)
  36. #define QSPI_CLK_DIV_MAX 0xffff
  37. /* command */
  38. #define QSPI_EN_CS(n) (n << 28)
  39. #define QSPI_WLEN(n) ((n-1) << 19)
  40. #define QSPI_3_PIN BIT(18)
  41. #define QSPI_RD_SNGL BIT(16)
  42. #define QSPI_WR_SNGL (2 << 16)
  43. #define QSPI_INVAL (4 << 16)
  44. #define QSPI_RD_QUAD (7 << 16)
  45. /* device control */
  46. #define QSPI_CKPHA(n) (1 << (2 + n*8))
  47. #define QSPI_CSPOL(n) (1 << (1 + n*8))
  48. #define QSPI_CKPOL(n) (1 << (n*8))
  49. /* status */
  50. #define QSPI_WC BIT(1)
  51. #define QSPI_BUSY BIT(0)
  52. #define QSPI_WC_BUSY (QSPI_WC | QSPI_BUSY)
  53. #define QSPI_XFER_DONE QSPI_WC
  54. #define MM_SWITCH 0x01
  55. #define MEM_CS(cs) ((cs + 1) << 8)
  56. #define MEM_CS_UNSELECT 0xfffff8ff
  57. #define QSPI_SETUP0_READ_NORMAL (0x0 << 12)
  58. #define QSPI_SETUP0_READ_DUAL (0x1 << 12)
  59. #define QSPI_SETUP0_READ_QUAD (0x3 << 12)
  60. #define QSPI_SETUP0_ADDR_SHIFT (8)
  61. #define QSPI_SETUP0_DBITS_SHIFT (10)
  62. #define TI_QSPI_SETUP_REG(priv, cs) (&(priv)->base->setup0 + (cs))
  63. /* ti qspi register set */
  64. struct ti_qspi_regs {
  65. u32 pid;
  66. u32 pad0[3];
  67. u32 sysconfig;
  68. u32 pad1[3];
  69. u32 int_stat_raw;
  70. u32 int_stat_en;
  71. u32 int_en_set;
  72. u32 int_en_ctlr;
  73. u32 intc_eoi;
  74. u32 pad2[3];
  75. u32 clk_ctrl;
  76. u32 dc;
  77. u32 cmd;
  78. u32 status;
  79. u32 data;
  80. u32 setup0;
  81. u32 setup1;
  82. u32 setup2;
  83. u32 setup3;
  84. u32 memswitch;
  85. u32 data1;
  86. u32 data2;
  87. u32 data3;
  88. };
  89. /* ti qspi priv */
  90. struct ti_qspi_priv {
  91. void *memory_map;
  92. size_t mmap_size;
  93. uint max_hz;
  94. u32 num_cs;
  95. struct ti_qspi_regs *base;
  96. void *ctrl_mod_mmap;
  97. ulong fclk;
  98. unsigned int mode;
  99. u32 cmd;
  100. u32 dc;
  101. };
  102. static int ti_qspi_set_speed(struct udevice *bus, uint hz)
  103. {
  104. struct ti_qspi_priv *priv = dev_get_priv(bus);
  105. uint clk_div;
  106. if (!hz)
  107. clk_div = 0;
  108. else
  109. clk_div = DIV_ROUND_UP(priv->fclk, hz) - 1;
  110. /* truncate clk_div value to QSPI_CLK_DIV_MAX */
  111. if (clk_div > QSPI_CLK_DIV_MAX)
  112. clk_div = QSPI_CLK_DIV_MAX;
  113. debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
  114. /* disable SCLK */
  115. writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN,
  116. &priv->base->clk_ctrl);
  117. /* enable SCLK and program the clk divider */
  118. writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl);
  119. return 0;
  120. }
  121. static void ti_qspi_cs_deactivate(struct ti_qspi_priv *priv)
  122. {
  123. writel(priv->cmd | QSPI_INVAL, &priv->base->cmd);
  124. /* dummy readl to ensure bus sync */
  125. readl(&priv->base->cmd);
  126. }
  127. static void ti_qspi_ctrl_mode_mmap(void *ctrl_mod_mmap, int cs, bool enable)
  128. {
  129. u32 val;
  130. val = readl(ctrl_mod_mmap);
  131. if (enable)
  132. val |= MEM_CS(cs);
  133. else
  134. val &= MEM_CS_UNSELECT;
  135. writel(val, ctrl_mod_mmap);
  136. }
  137. static int ti_qspi_xfer(struct udevice *dev, unsigned int bitlen,
  138. const void *dout, void *din, unsigned long flags)
  139. {
  140. struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
  141. struct ti_qspi_priv *priv;
  142. struct udevice *bus;
  143. uint words = bitlen >> 3; /* fixed 8-bit word length */
  144. const uchar *txp = dout;
  145. uchar *rxp = din;
  146. uint status;
  147. int timeout;
  148. unsigned int cs = slave->cs;
  149. bus = dev->parent;
  150. priv = dev_get_priv(bus);
  151. if (cs > priv->num_cs) {
  152. debug("invalid qspi chip select\n");
  153. return -EINVAL;
  154. }
  155. if (bitlen == 0)
  156. return -1;
  157. if (bitlen % 8) {
  158. debug("spi_xfer: Non byte aligned SPI transfer\n");
  159. return -1;
  160. }
  161. /* Setup command reg */
  162. priv->cmd = 0;
  163. priv->cmd |= QSPI_WLEN(8);
  164. priv->cmd |= QSPI_EN_CS(cs);
  165. if (priv->mode & SPI_3WIRE)
  166. priv->cmd |= QSPI_3_PIN;
  167. priv->cmd |= 0xfff;
  168. while (words) {
  169. u8 xfer_len = 0;
  170. if (txp) {
  171. u32 cmd = priv->cmd;
  172. if (words >= QSPI_WLEN_MAX_BYTES) {
  173. u32 *txbuf = (u32 *)txp;
  174. u32 data;
  175. data = cpu_to_be32(*txbuf++);
  176. writel(data, &priv->base->data3);
  177. data = cpu_to_be32(*txbuf++);
  178. writel(data, &priv->base->data2);
  179. data = cpu_to_be32(*txbuf++);
  180. writel(data, &priv->base->data1);
  181. data = cpu_to_be32(*txbuf++);
  182. writel(data, &priv->base->data);
  183. cmd &= ~QSPI_WLEN_MASK;
  184. cmd |= QSPI_WLEN(QSPI_WLEN_MAX_BITS);
  185. xfer_len = QSPI_WLEN_MAX_BYTES;
  186. } else {
  187. writeb(*txp, &priv->base->data);
  188. xfer_len = 1;
  189. }
  190. debug("tx cmd %08x dc %08x\n",
  191. cmd | QSPI_WR_SNGL, priv->dc);
  192. writel(cmd | QSPI_WR_SNGL, &priv->base->cmd);
  193. status = readl(&priv->base->status);
  194. timeout = QSPI_TIMEOUT;
  195. while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
  196. if (--timeout < 0) {
  197. printf("spi_xfer: TX timeout!\n");
  198. return -1;
  199. }
  200. status = readl(&priv->base->status);
  201. }
  202. txp += xfer_len;
  203. debug("tx done, status %08x\n", status);
  204. }
  205. if (rxp) {
  206. debug("rx cmd %08x dc %08x\n",
  207. ((u32)(priv->cmd | QSPI_RD_SNGL)), priv->dc);
  208. writel(priv->cmd | QSPI_RD_SNGL, &priv->base->cmd);
  209. status = readl(&priv->base->status);
  210. timeout = QSPI_TIMEOUT;
  211. while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
  212. if (--timeout < 0) {
  213. printf("spi_xfer: RX timeout!\n");
  214. return -1;
  215. }
  216. status = readl(&priv->base->status);
  217. }
  218. *rxp++ = readl(&priv->base->data);
  219. xfer_len = 1;
  220. debug("rx done, status %08x, read %02x\n",
  221. status, *(rxp-1));
  222. }
  223. words -= xfer_len;
  224. }
  225. /* Terminate frame */
  226. if (flags & SPI_XFER_END)
  227. ti_qspi_cs_deactivate(priv);
  228. return 0;
  229. }
  230. /* TODO: control from sf layer to here through dm-spi */
  231. static void ti_qspi_copy_mmap(void *data, void *offset, size_t len)
  232. {
  233. #if defined(CONFIG_TI_EDMA3) && !defined(CONFIG_DMA)
  234. unsigned int addr = (unsigned int) (data);
  235. unsigned int edma_slot_num = 1;
  236. /* Invalidate the area, so no writeback into the RAM races with DMA */
  237. invalidate_dcache_range(addr, addr + roundup(len, ARCH_DMA_MINALIGN));
  238. /* enable edma3 clocks */
  239. enable_edma3_clocks();
  240. /* Call edma3 api to do actual DMA transfer */
  241. edma3_transfer(EDMA3_BASE, edma_slot_num, data, offset, len);
  242. /* disable edma3 clocks */
  243. disable_edma3_clocks();
  244. #else
  245. memcpy_fromio(data, offset, len);
  246. #endif
  247. *((unsigned int *)offset) += len;
  248. }
  249. static void ti_qspi_setup_mmap_read(struct ti_qspi_priv *priv, int cs,
  250. u8 opcode, u8 data_nbits, u8 addr_width,
  251. u8 dummy_bytes)
  252. {
  253. u32 memval = opcode;
  254. switch (data_nbits) {
  255. case 4:
  256. memval |= QSPI_SETUP0_READ_QUAD;
  257. break;
  258. case 2:
  259. memval |= QSPI_SETUP0_READ_DUAL;
  260. break;
  261. default:
  262. memval |= QSPI_SETUP0_READ_NORMAL;
  263. break;
  264. }
  265. memval |= ((addr_width - 1) << QSPI_SETUP0_ADDR_SHIFT |
  266. dummy_bytes << QSPI_SETUP0_DBITS_SHIFT);
  267. writel(memval, TI_QSPI_SETUP_REG(priv, cs));
  268. }
  269. static int ti_qspi_set_mode(struct udevice *bus, uint mode)
  270. {
  271. struct ti_qspi_priv *priv = dev_get_priv(bus);
  272. priv->dc = 0;
  273. if (mode & SPI_CPHA)
  274. priv->dc |= QSPI_CKPHA(0);
  275. if (mode & SPI_CPOL)
  276. priv->dc |= QSPI_CKPOL(0);
  277. if (mode & SPI_CS_HIGH)
  278. priv->dc |= QSPI_CSPOL(0);
  279. return 0;
  280. }
  281. static int ti_qspi_exec_mem_op(struct spi_slave *slave,
  282. const struct spi_mem_op *op)
  283. {
  284. struct dm_spi_slave_platdata *slave_plat;
  285. struct ti_qspi_priv *priv;
  286. struct udevice *bus;
  287. u32 from = 0;
  288. int ret = 0;
  289. bus = slave->dev->parent;
  290. priv = dev_get_priv(bus);
  291. slave_plat = dev_get_parent_platdata(slave->dev);
  292. /* Only optimize read path. */
  293. if (!op->data.nbytes || op->data.dir != SPI_MEM_DATA_IN ||
  294. !op->addr.nbytes || op->addr.nbytes > 4)
  295. return -ENOTSUPP;
  296. /* Address exceeds MMIO window size, fall back to regular mode. */
  297. from = op->addr.val;
  298. if (from + op->data.nbytes > priv->mmap_size)
  299. return -ENOTSUPP;
  300. ti_qspi_setup_mmap_read(priv, slave_plat->cs, op->cmd.opcode,
  301. op->data.buswidth, op->addr.nbytes,
  302. op->dummy.nbytes);
  303. ti_qspi_copy_mmap((void *)op->data.buf.in,
  304. (void *)priv->memory_map + from, op->data.nbytes);
  305. return ret;
  306. }
  307. static int ti_qspi_claim_bus(struct udevice *dev)
  308. {
  309. struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
  310. struct ti_qspi_priv *priv;
  311. struct udevice *bus;
  312. bus = dev->parent;
  313. priv = dev_get_priv(bus);
  314. if (slave_plat->cs > priv->num_cs) {
  315. debug("invalid qspi chip select\n");
  316. return -EINVAL;
  317. }
  318. writel(MM_SWITCH, &priv->base->memswitch);
  319. if (priv->ctrl_mod_mmap)
  320. ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap,
  321. slave_plat->cs, true);
  322. writel(priv->dc, &priv->base->dc);
  323. writel(0, &priv->base->cmd);
  324. writel(0, &priv->base->data);
  325. priv->dc <<= slave_plat->cs * 8;
  326. writel(priv->dc, &priv->base->dc);
  327. return 0;
  328. }
  329. static int ti_qspi_release_bus(struct udevice *dev)
  330. {
  331. struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
  332. struct ti_qspi_priv *priv;
  333. struct udevice *bus;
  334. bus = dev->parent;
  335. priv = dev_get_priv(bus);
  336. writel(~MM_SWITCH, &priv->base->memswitch);
  337. if (priv->ctrl_mod_mmap)
  338. ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap,
  339. slave_plat->cs, false);
  340. writel(0, &priv->base->dc);
  341. writel(0, &priv->base->cmd);
  342. writel(0, &priv->base->data);
  343. writel(0, TI_QSPI_SETUP_REG(priv, slave_plat->cs));
  344. return 0;
  345. }
  346. static int ti_qspi_probe(struct udevice *bus)
  347. {
  348. struct ti_qspi_priv *priv = dev_get_priv(bus);
  349. priv->fclk = dev_get_driver_data(bus);
  350. return 0;
  351. }
  352. static void *map_syscon_chipselects(struct udevice *bus)
  353. {
  354. #if CONFIG_IS_ENABLED(SYSCON)
  355. struct udevice *syscon;
  356. struct regmap *regmap;
  357. const fdt32_t *cell;
  358. int len, err;
  359. err = uclass_get_device_by_phandle(UCLASS_SYSCON, bus,
  360. "syscon-chipselects", &syscon);
  361. if (err) {
  362. debug("%s: unable to find syscon device (%d)\n", __func__,
  363. err);
  364. return NULL;
  365. }
  366. regmap = syscon_get_regmap(syscon);
  367. if (IS_ERR(regmap)) {
  368. debug("%s: unable to find regmap (%ld)\n", __func__,
  369. PTR_ERR(regmap));
  370. return NULL;
  371. }
  372. cell = fdt_getprop(gd->fdt_blob, dev_of_offset(bus),
  373. "syscon-chipselects", &len);
  374. if (len < 2*sizeof(fdt32_t)) {
  375. debug("%s: offset not available\n", __func__);
  376. return NULL;
  377. }
  378. return fdtdec_get_number(cell + 1, 1) + regmap_get_range(regmap, 0);
  379. #else
  380. fdt_addr_t addr;
  381. addr = devfdt_get_addr_index(bus, 2);
  382. return (addr == FDT_ADDR_T_NONE) ? NULL :
  383. map_physmem(addr, 0, MAP_NOCACHE);
  384. #endif
  385. }
  386. static int ti_qspi_ofdata_to_platdata(struct udevice *bus)
  387. {
  388. struct ti_qspi_priv *priv = dev_get_priv(bus);
  389. const void *blob = gd->fdt_blob;
  390. int node = dev_of_offset(bus);
  391. fdt_addr_t mmap_addr;
  392. fdt_addr_t mmap_size;
  393. priv->ctrl_mod_mmap = map_syscon_chipselects(bus);
  394. priv->base = map_physmem(dev_read_addr(bus),
  395. sizeof(struct ti_qspi_regs), MAP_NOCACHE);
  396. mmap_addr = devfdt_get_addr_size_index(bus, 1, &mmap_size);
  397. priv->memory_map = map_physmem(mmap_addr, mmap_size, MAP_NOCACHE);
  398. priv->mmap_size = mmap_size;
  399. priv->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", -1);
  400. if (priv->max_hz < 0) {
  401. debug("Error: Max frequency missing\n");
  402. return -ENODEV;
  403. }
  404. priv->num_cs = fdtdec_get_int(blob, node, "num-cs", 4);
  405. debug("%s: regs=<0x%x>, max-frequency=%d\n", __func__,
  406. (int)priv->base, priv->max_hz);
  407. return 0;
  408. }
  409. static const struct spi_controller_mem_ops ti_qspi_mem_ops = {
  410. .exec_op = ti_qspi_exec_mem_op,
  411. };
  412. static const struct dm_spi_ops ti_qspi_ops = {
  413. .claim_bus = ti_qspi_claim_bus,
  414. .release_bus = ti_qspi_release_bus,
  415. .xfer = ti_qspi_xfer,
  416. .set_speed = ti_qspi_set_speed,
  417. .set_mode = ti_qspi_set_mode,
  418. .mem_ops = &ti_qspi_mem_ops,
  419. };
  420. static const struct udevice_id ti_qspi_ids[] = {
  421. { .compatible = "ti,dra7xxx-qspi", .data = QSPI_DRA7XX_FCLK},
  422. { .compatible = "ti,am4372-qspi", .data = QSPI_FCLK},
  423. { }
  424. };
  425. U_BOOT_DRIVER(ti_qspi) = {
  426. .name = "ti_qspi",
  427. .id = UCLASS_SPI,
  428. .of_match = ti_qspi_ids,
  429. .ops = &ti_qspi_ops,
  430. .ofdata_to_platdata = ti_qspi_ofdata_to_platdata,
  431. .priv_auto_alloc_size = sizeof(struct ti_qspi_priv),
  432. .probe = ti_qspi_probe,
  433. };