stm32_qspi.c 12 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2016
  4. *
  5. * Michael Kurz, <michi.kurz@gmail.com>
  6. *
  7. * STM32 QSPI driver
  8. */
  9. #include <common.h>
  10. #include <clk.h>
  11. #include <dm.h>
  12. #include <log.h>
  13. #include <reset.h>
  14. #include <spi.h>
  15. #include <spi-mem.h>
  16. #include <dm/device_compat.h>
  17. #include <linux/bitops.h>
  18. #include <linux/delay.h>
  19. #include <linux/iopoll.h>
  20. #include <linux/ioport.h>
  21. #include <linux/sizes.h>
  22. struct stm32_qspi_regs {
  23. u32 cr; /* 0x00 */
  24. u32 dcr; /* 0x04 */
  25. u32 sr; /* 0x08 */
  26. u32 fcr; /* 0x0C */
  27. u32 dlr; /* 0x10 */
  28. u32 ccr; /* 0x14 */
  29. u32 ar; /* 0x18 */
  30. u32 abr; /* 0x1C */
  31. u32 dr; /* 0x20 */
  32. u32 psmkr; /* 0x24 */
  33. u32 psmar; /* 0x28 */
  34. u32 pir; /* 0x2C */
  35. u32 lptr; /* 0x30 */
  36. };
  37. /*
  38. * QUADSPI control register
  39. */
  40. #define STM32_QSPI_CR_EN BIT(0)
  41. #define STM32_QSPI_CR_ABORT BIT(1)
  42. #define STM32_QSPI_CR_DMAEN BIT(2)
  43. #define STM32_QSPI_CR_TCEN BIT(3)
  44. #define STM32_QSPI_CR_SSHIFT BIT(4)
  45. #define STM32_QSPI_CR_DFM BIT(6)
  46. #define STM32_QSPI_CR_FSEL BIT(7)
  47. #define STM32_QSPI_CR_FTHRES_SHIFT 8
  48. #define STM32_QSPI_CR_TEIE BIT(16)
  49. #define STM32_QSPI_CR_TCIE BIT(17)
  50. #define STM32_QSPI_CR_FTIE BIT(18)
  51. #define STM32_QSPI_CR_SMIE BIT(19)
  52. #define STM32_QSPI_CR_TOIE BIT(20)
  53. #define STM32_QSPI_CR_APMS BIT(22)
  54. #define STM32_QSPI_CR_PMM BIT(23)
  55. #define STM32_QSPI_CR_PRESCALER_MASK GENMASK(7, 0)
  56. #define STM32_QSPI_CR_PRESCALER_SHIFT 24
  57. /*
  58. * QUADSPI device configuration register
  59. */
  60. #define STM32_QSPI_DCR_CKMODE BIT(0)
  61. #define STM32_QSPI_DCR_CSHT_MASK GENMASK(2, 0)
  62. #define STM32_QSPI_DCR_CSHT_SHIFT 8
  63. #define STM32_QSPI_DCR_FSIZE_MASK GENMASK(4, 0)
  64. #define STM32_QSPI_DCR_FSIZE_SHIFT 16
  65. /*
  66. * QUADSPI status register
  67. */
  68. #define STM32_QSPI_SR_TEF BIT(0)
  69. #define STM32_QSPI_SR_TCF BIT(1)
  70. #define STM32_QSPI_SR_FTF BIT(2)
  71. #define STM32_QSPI_SR_SMF BIT(3)
  72. #define STM32_QSPI_SR_TOF BIT(4)
  73. #define STM32_QSPI_SR_BUSY BIT(5)
  74. /*
  75. * QUADSPI flag clear register
  76. */
  77. #define STM32_QSPI_FCR_CTEF BIT(0)
  78. #define STM32_QSPI_FCR_CTCF BIT(1)
  79. #define STM32_QSPI_FCR_CSMF BIT(3)
  80. #define STM32_QSPI_FCR_CTOF BIT(4)
  81. /*
  82. * QUADSPI communication configuration register
  83. */
  84. #define STM32_QSPI_CCR_DDRM BIT(31)
  85. #define STM32_QSPI_CCR_DHHC BIT(30)
  86. #define STM32_QSPI_CCR_SIOO BIT(28)
  87. #define STM32_QSPI_CCR_FMODE_SHIFT 26
  88. #define STM32_QSPI_CCR_DMODE_SHIFT 24
  89. #define STM32_QSPI_CCR_DCYC_SHIFT 18
  90. #define STM32_QSPI_CCR_ABSIZE_SHIFT 16
  91. #define STM32_QSPI_CCR_ABMODE_SHIFT 14
  92. #define STM32_QSPI_CCR_ADSIZE_SHIFT 12
  93. #define STM32_QSPI_CCR_ADMODE_SHIFT 10
  94. #define STM32_QSPI_CCR_IMODE_SHIFT 8
  95. #define STM32_QSPI_CCR_IND_WRITE 0
  96. #define STM32_QSPI_CCR_IND_READ 1
  97. #define STM32_QSPI_CCR_MEM_MAP 3
  98. #define STM32_QSPI_MAX_MMAP_SZ SZ_256M
  99. #define STM32_QSPI_MAX_CHIP 2
  100. #define STM32_QSPI_FIFO_TIMEOUT_US 30000
  101. #define STM32_QSPI_CMD_TIMEOUT_US 1000000
  102. #define STM32_BUSY_TIMEOUT_US 100000
  103. #define STM32_ABT_TIMEOUT_US 100000
  104. struct stm32_qspi_flash {
  105. u32 cr;
  106. u32 dcr;
  107. bool initialized;
  108. };
  109. struct stm32_qspi_priv {
  110. struct stm32_qspi_regs *regs;
  111. struct stm32_qspi_flash flash[STM32_QSPI_MAX_CHIP];
  112. void __iomem *mm_base;
  113. resource_size_t mm_size;
  114. ulong clock_rate;
  115. int cs_used;
  116. };
  117. static int _stm32_qspi_wait_for_not_busy(struct stm32_qspi_priv *priv)
  118. {
  119. u32 sr;
  120. int ret;
  121. ret = readl_poll_timeout(&priv->regs->sr, sr,
  122. !(sr & STM32_QSPI_SR_BUSY),
  123. STM32_BUSY_TIMEOUT_US);
  124. if (ret)
  125. pr_err("busy timeout (stat:%#x)\n", sr);
  126. return ret;
  127. }
  128. static int _stm32_qspi_wait_cmd(struct stm32_qspi_priv *priv,
  129. const struct spi_mem_op *op)
  130. {
  131. u32 sr;
  132. int ret;
  133. if (!op->data.nbytes)
  134. return _stm32_qspi_wait_for_not_busy(priv);
  135. ret = readl_poll_timeout(&priv->regs->sr, sr,
  136. sr & STM32_QSPI_SR_TCF,
  137. STM32_QSPI_CMD_TIMEOUT_US);
  138. if (ret) {
  139. pr_err("cmd timeout (stat:%#x)\n", sr);
  140. } else if (readl(&priv->regs->sr) & STM32_QSPI_SR_TEF) {
  141. pr_err("transfer error (stat:%#x)\n", sr);
  142. ret = -EIO;
  143. }
  144. /* clear flags */
  145. writel(STM32_QSPI_FCR_CTCF | STM32_QSPI_FCR_CTEF, &priv->regs->fcr);
  146. return ret;
  147. }
  148. static void _stm32_qspi_read_fifo(u8 *val, void __iomem *addr)
  149. {
  150. *val = readb(addr);
  151. }
  152. static void _stm32_qspi_write_fifo(u8 *val, void __iomem *addr)
  153. {
  154. writeb(*val, addr);
  155. }
  156. static int _stm32_qspi_poll(struct stm32_qspi_priv *priv,
  157. const struct spi_mem_op *op)
  158. {
  159. void (*fifo)(u8 *val, void __iomem *addr);
  160. u32 len = op->data.nbytes, sr;
  161. u8 *buf;
  162. int ret;
  163. if (op->data.dir == SPI_MEM_DATA_IN) {
  164. fifo = _stm32_qspi_read_fifo;
  165. buf = op->data.buf.in;
  166. } else {
  167. fifo = _stm32_qspi_write_fifo;
  168. buf = (u8 *)op->data.buf.out;
  169. }
  170. while (len--) {
  171. ret = readl_poll_timeout(&priv->regs->sr, sr,
  172. sr & STM32_QSPI_SR_FTF,
  173. STM32_QSPI_FIFO_TIMEOUT_US);
  174. if (ret) {
  175. pr_err("fifo timeout (len:%d stat:%#x)\n", len, sr);
  176. return ret;
  177. }
  178. fifo(buf++, &priv->regs->dr);
  179. }
  180. return 0;
  181. }
  182. static int stm32_qspi_mm(struct stm32_qspi_priv *priv,
  183. const struct spi_mem_op *op)
  184. {
  185. memcpy_fromio(op->data.buf.in, priv->mm_base + op->addr.val,
  186. op->data.nbytes);
  187. return 0;
  188. }
  189. static int _stm32_qspi_tx(struct stm32_qspi_priv *priv,
  190. const struct spi_mem_op *op,
  191. u8 mode)
  192. {
  193. if (!op->data.nbytes)
  194. return 0;
  195. if (mode == STM32_QSPI_CCR_MEM_MAP)
  196. return stm32_qspi_mm(priv, op);
  197. return _stm32_qspi_poll(priv, op);
  198. }
  199. static int _stm32_qspi_get_mode(u8 buswidth)
  200. {
  201. if (buswidth == 4)
  202. return 3;
  203. return buswidth;
  204. }
  205. static int stm32_qspi_exec_op(struct spi_slave *slave,
  206. const struct spi_mem_op *op)
  207. {
  208. struct stm32_qspi_priv *priv = dev_get_priv(slave->dev->parent);
  209. u32 cr, ccr, addr_max;
  210. u8 mode = STM32_QSPI_CCR_IND_WRITE;
  211. int timeout, ret;
  212. debug("%s: cmd:%#x mode:%d.%d.%d.%d addr:%#llx len:%#x\n",
  213. __func__, op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
  214. op->dummy.buswidth, op->data.buswidth,
  215. op->addr.val, op->data.nbytes);
  216. ret = _stm32_qspi_wait_for_not_busy(priv);
  217. if (ret)
  218. return ret;
  219. addr_max = op->addr.val + op->data.nbytes + 1;
  220. if (op->data.dir == SPI_MEM_DATA_IN && op->data.nbytes) {
  221. if (addr_max < priv->mm_size && op->addr.buswidth)
  222. mode = STM32_QSPI_CCR_MEM_MAP;
  223. else
  224. mode = STM32_QSPI_CCR_IND_READ;
  225. }
  226. if (op->data.nbytes)
  227. writel(op->data.nbytes - 1, &priv->regs->dlr);
  228. ccr = (mode << STM32_QSPI_CCR_FMODE_SHIFT);
  229. ccr |= op->cmd.opcode;
  230. ccr |= (_stm32_qspi_get_mode(op->cmd.buswidth)
  231. << STM32_QSPI_CCR_IMODE_SHIFT);
  232. if (op->addr.nbytes) {
  233. ccr |= ((op->addr.nbytes - 1) << STM32_QSPI_CCR_ADSIZE_SHIFT);
  234. ccr |= (_stm32_qspi_get_mode(op->addr.buswidth)
  235. << STM32_QSPI_CCR_ADMODE_SHIFT);
  236. }
  237. if (op->dummy.buswidth && op->dummy.nbytes)
  238. ccr |= (op->dummy.nbytes * 8 / op->dummy.buswidth
  239. << STM32_QSPI_CCR_DCYC_SHIFT);
  240. if (op->data.nbytes)
  241. ccr |= (_stm32_qspi_get_mode(op->data.buswidth)
  242. << STM32_QSPI_CCR_DMODE_SHIFT);
  243. writel(ccr, &priv->regs->ccr);
  244. if (op->addr.nbytes && mode != STM32_QSPI_CCR_MEM_MAP)
  245. writel(op->addr.val, &priv->regs->ar);
  246. ret = _stm32_qspi_tx(priv, op, mode);
  247. /*
  248. * Abort in:
  249. * -error case
  250. * -read memory map: prefetching must be stopped if we read the last
  251. * byte of device (device size - fifo size). like device size is not
  252. * knows, the prefetching is always stop.
  253. */
  254. if (ret || mode == STM32_QSPI_CCR_MEM_MAP)
  255. goto abort;
  256. /* Wait end of tx in indirect mode */
  257. ret = _stm32_qspi_wait_cmd(priv, op);
  258. if (ret)
  259. goto abort;
  260. return 0;
  261. abort:
  262. setbits_le32(&priv->regs->cr, STM32_QSPI_CR_ABORT);
  263. /* Wait clear of abort bit by hw */
  264. timeout = readl_poll_timeout(&priv->regs->cr, cr,
  265. !(cr & STM32_QSPI_CR_ABORT),
  266. STM32_ABT_TIMEOUT_US);
  267. writel(STM32_QSPI_FCR_CTCF, &priv->regs->fcr);
  268. if (ret || timeout)
  269. pr_err("%s ret:%d abort timeout:%d\n", __func__, ret, timeout);
  270. return ret;
  271. }
  272. static int stm32_qspi_probe(struct udevice *bus)
  273. {
  274. struct stm32_qspi_priv *priv = dev_get_priv(bus);
  275. struct resource res;
  276. struct clk clk;
  277. struct reset_ctl reset_ctl;
  278. int ret;
  279. ret = dev_read_resource_byname(bus, "qspi", &res);
  280. if (ret) {
  281. dev_err(bus, "can't get regs base addresses(ret = %d)!\n", ret);
  282. return ret;
  283. }
  284. priv->regs = (struct stm32_qspi_regs *)res.start;
  285. ret = dev_read_resource_byname(bus, "qspi_mm", &res);
  286. if (ret) {
  287. dev_err(bus, "can't get mmap base address(ret = %d)!\n", ret);
  288. return ret;
  289. }
  290. priv->mm_base = (void __iomem *)res.start;
  291. priv->mm_size = resource_size(&res);
  292. if (priv->mm_size > STM32_QSPI_MAX_MMAP_SZ)
  293. return -EINVAL;
  294. debug("%s: regs=<0x%p> mapped=<0x%p> mapped_size=<0x%lx>\n",
  295. __func__, priv->regs, priv->mm_base, priv->mm_size);
  296. ret = clk_get_by_index(bus, 0, &clk);
  297. if (ret < 0)
  298. return ret;
  299. ret = clk_enable(&clk);
  300. if (ret) {
  301. dev_err(bus, "failed to enable clock\n");
  302. return ret;
  303. }
  304. priv->clock_rate = clk_get_rate(&clk);
  305. if (!priv->clock_rate) {
  306. clk_disable(&clk);
  307. return -EINVAL;
  308. }
  309. ret = reset_get_by_index(bus, 0, &reset_ctl);
  310. if (ret) {
  311. if (ret != -ENOENT) {
  312. dev_err(bus, "failed to get reset\n");
  313. clk_disable(&clk);
  314. return ret;
  315. }
  316. } else {
  317. /* Reset QSPI controller */
  318. reset_assert(&reset_ctl);
  319. udelay(2);
  320. reset_deassert(&reset_ctl);
  321. }
  322. priv->cs_used = -1;
  323. setbits_le32(&priv->regs->cr, STM32_QSPI_CR_SSHIFT);
  324. /* Set dcr fsize to max address */
  325. setbits_le32(&priv->regs->dcr,
  326. STM32_QSPI_DCR_FSIZE_MASK << STM32_QSPI_DCR_FSIZE_SHIFT);
  327. return 0;
  328. }
  329. static int stm32_qspi_claim_bus(struct udevice *dev)
  330. {
  331. struct stm32_qspi_priv *priv = dev_get_priv(dev->parent);
  332. struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
  333. int slave_cs = slave_plat->cs;
  334. if (slave_cs >= STM32_QSPI_MAX_CHIP)
  335. return -ENODEV;
  336. if (priv->cs_used != slave_cs) {
  337. struct stm32_qspi_flash *flash = &priv->flash[slave_cs];
  338. priv->cs_used = slave_cs;
  339. if (flash->initialized) {
  340. /* Set the configuration: speed + cs */
  341. writel(flash->cr, &priv->regs->cr);
  342. writel(flash->dcr, &priv->regs->dcr);
  343. } else {
  344. /* Set chip select */
  345. clrsetbits_le32(&priv->regs->cr, STM32_QSPI_CR_FSEL,
  346. priv->cs_used ? STM32_QSPI_CR_FSEL : 0);
  347. /* Save the configuration: speed + cs */
  348. flash->cr = readl(&priv->regs->cr);
  349. flash->dcr = readl(&priv->regs->dcr);
  350. flash->initialized = true;
  351. }
  352. }
  353. setbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN);
  354. return 0;
  355. }
  356. static int stm32_qspi_release_bus(struct udevice *dev)
  357. {
  358. struct stm32_qspi_priv *priv = dev_get_priv(dev->parent);
  359. clrbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN);
  360. return 0;
  361. }
  362. static int stm32_qspi_set_speed(struct udevice *bus, uint speed)
  363. {
  364. struct stm32_qspi_priv *priv = dev_get_priv(bus);
  365. u32 qspi_clk = priv->clock_rate;
  366. u32 prescaler = 255;
  367. u32 csht;
  368. int ret;
  369. if (speed > 0) {
  370. prescaler = 0;
  371. if (qspi_clk) {
  372. prescaler = DIV_ROUND_UP(qspi_clk, speed) - 1;
  373. if (prescaler > 255)
  374. prescaler = 255;
  375. }
  376. }
  377. csht = DIV_ROUND_UP((5 * qspi_clk) / (prescaler + 1), 100000000);
  378. csht = (csht - 1) & STM32_QSPI_DCR_CSHT_MASK;
  379. ret = _stm32_qspi_wait_for_not_busy(priv);
  380. if (ret)
  381. return ret;
  382. clrsetbits_le32(&priv->regs->cr,
  383. STM32_QSPI_CR_PRESCALER_MASK <<
  384. STM32_QSPI_CR_PRESCALER_SHIFT,
  385. prescaler << STM32_QSPI_CR_PRESCALER_SHIFT);
  386. clrsetbits_le32(&priv->regs->dcr,
  387. STM32_QSPI_DCR_CSHT_MASK << STM32_QSPI_DCR_CSHT_SHIFT,
  388. csht << STM32_QSPI_DCR_CSHT_SHIFT);
  389. debug("%s: regs=%p, speed=%d\n", __func__, priv->regs,
  390. (qspi_clk / (prescaler + 1)));
  391. return 0;
  392. }
  393. static int stm32_qspi_set_mode(struct udevice *bus, uint mode)
  394. {
  395. struct stm32_qspi_priv *priv = dev_get_priv(bus);
  396. int ret;
  397. ret = _stm32_qspi_wait_for_not_busy(priv);
  398. if (ret)
  399. return ret;
  400. if ((mode & SPI_CPHA) && (mode & SPI_CPOL))
  401. setbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CKMODE);
  402. else if (!(mode & SPI_CPHA) && !(mode & SPI_CPOL))
  403. clrbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CKMODE);
  404. else
  405. return -ENODEV;
  406. if (mode & SPI_CS_HIGH)
  407. return -ENODEV;
  408. debug("%s: regs=%p, mode=%d rx: ", __func__, priv->regs, mode);
  409. if (mode & SPI_RX_QUAD)
  410. debug("quad, tx: ");
  411. else if (mode & SPI_RX_DUAL)
  412. debug("dual, tx: ");
  413. else
  414. debug("single, tx: ");
  415. if (mode & SPI_TX_QUAD)
  416. debug("quad\n");
  417. else if (mode & SPI_TX_DUAL)
  418. debug("dual\n");
  419. else
  420. debug("single\n");
  421. return 0;
  422. }
  423. static const struct spi_controller_mem_ops stm32_qspi_mem_ops = {
  424. .exec_op = stm32_qspi_exec_op,
  425. };
  426. static const struct dm_spi_ops stm32_qspi_ops = {
  427. .claim_bus = stm32_qspi_claim_bus,
  428. .release_bus = stm32_qspi_release_bus,
  429. .set_speed = stm32_qspi_set_speed,
  430. .set_mode = stm32_qspi_set_mode,
  431. .mem_ops = &stm32_qspi_mem_ops,
  432. };
  433. static const struct udevice_id stm32_qspi_ids[] = {
  434. { .compatible = "st,stm32f469-qspi" },
  435. { }
  436. };
  437. U_BOOT_DRIVER(stm32_qspi) = {
  438. .name = "stm32_qspi",
  439. .id = UCLASS_SPI,
  440. .of_match = stm32_qspi_ids,
  441. .ops = &stm32_qspi_ops,
  442. .priv_auto_alloc_size = sizeof(struct stm32_qspi_priv),
  443. .probe = stm32_qspi_probe,
  444. };