mpc8xxx_spi.c 6.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2006 Ben Warren, Qstreams Networks Inc.
  4. * With help from the common/soft_spi and arch/powerpc/cpu/mpc8260 drivers
  5. */
  6. #include <common.h>
  7. #include <clk.h>
  8. #include <dm.h>
  9. #include <errno.h>
  10. #include <log.h>
  11. #include <malloc.h>
  12. #include <spi.h>
  13. #include <asm/mpc8xxx_spi.h>
  14. #include <asm-generic/gpio.h>
  15. #include <dm/device_compat.h>
  16. #include <linux/bitops.h>
  17. #include <linux/delay.h>
  18. enum {
  19. SPI_EV_NE = BIT(31 - 22), /* Receiver Not Empty */
  20. SPI_EV_NF = BIT(31 - 23), /* Transmitter Not Full */
  21. };
  22. enum {
  23. SPI_MODE_LOOP = BIT(31 - 1), /* Loopback mode */
  24. SPI_MODE_CI = BIT(31 - 2), /* Clock invert */
  25. SPI_MODE_CP = BIT(31 - 3), /* Clock phase */
  26. SPI_MODE_DIV16 = BIT(31 - 4), /* Divide clock source by 16 */
  27. SPI_MODE_REV = BIT(31 - 5), /* Reverse mode - MSB first */
  28. SPI_MODE_MS = BIT(31 - 6), /* Always master */
  29. SPI_MODE_EN = BIT(31 - 7), /* Enable interface */
  30. SPI_MODE_LEN_MASK = 0xf00000,
  31. SPI_MODE_LEN_SHIFT = 20,
  32. SPI_MODE_PM_SHIFT = 16,
  33. SPI_MODE_PM_MASK = 0xf0000,
  34. SPI_COM_LST = BIT(31 - 9),
  35. };
  36. struct mpc8xxx_priv {
  37. spi8xxx_t *spi;
  38. struct gpio_desc gpios[16];
  39. int cs_count;
  40. ulong clk_rate;
  41. };
  42. #define SPI_TIMEOUT 1000
  43. static int mpc8xxx_spi_ofdata_to_platdata(struct udevice *dev)
  44. {
  45. struct mpc8xxx_priv *priv = dev_get_priv(dev);
  46. struct clk clk;
  47. int ret;
  48. priv->spi = (spi8xxx_t *)dev_read_addr(dev);
  49. ret = gpio_request_list_by_name(dev, "gpios", priv->gpios,
  50. ARRAY_SIZE(priv->gpios), GPIOD_IS_OUT | GPIOD_ACTIVE_LOW);
  51. if (ret < 0)
  52. return -EINVAL;
  53. priv->cs_count = ret;
  54. ret = clk_get_by_index(dev, 0, &clk);
  55. if (ret) {
  56. dev_err(dev, "%s: clock not defined\n", __func__);
  57. return ret;
  58. }
  59. priv->clk_rate = clk_get_rate(&clk);
  60. if (!priv->clk_rate) {
  61. dev_err(dev, "%s: failed to get clock rate\n", __func__);
  62. return -EINVAL;
  63. }
  64. return 0;
  65. }
  66. static int mpc8xxx_spi_probe(struct udevice *dev)
  67. {
  68. struct mpc8xxx_priv *priv = dev_get_priv(dev);
  69. spi8xxx_t *spi = priv->spi;
  70. /*
  71. * SPI pins on the MPC83xx are not muxed, so all we do is initialize
  72. * some registers
  73. */
  74. out_be32(&priv->spi->mode, SPI_MODE_REV | SPI_MODE_MS);
  75. /* set len to 8 bits */
  76. setbits_be32(&spi->mode, (8 - 1) << SPI_MODE_LEN_SHIFT);
  77. setbits_be32(&spi->mode, SPI_MODE_EN);
  78. /* Clear all SPI events */
  79. setbits_be32(&priv->spi->event, 0xffffffff);
  80. /* Mask all SPI interrupts */
  81. clrbits_be32(&priv->spi->mask, 0xffffffff);
  82. /* LST bit doesn't do anything, so disregard */
  83. out_be32(&priv->spi->com, 0);
  84. return 0;
  85. }
  86. static void mpc8xxx_spi_cs_activate(struct udevice *dev)
  87. {
  88. struct mpc8xxx_priv *priv = dev_get_priv(dev->parent);
  89. struct dm_spi_slave_platdata *platdata = dev_get_parent_platdata(dev);
  90. dm_gpio_set_value(&priv->gpios[platdata->cs], 1);
  91. }
  92. static void mpc8xxx_spi_cs_deactivate(struct udevice *dev)
  93. {
  94. struct mpc8xxx_priv *priv = dev_get_priv(dev->parent);
  95. struct dm_spi_slave_platdata *platdata = dev_get_parent_platdata(dev);
  96. dm_gpio_set_value(&priv->gpios[platdata->cs], 0);
  97. }
  98. static int mpc8xxx_spi_xfer(struct udevice *dev, uint bitlen,
  99. const void *dout, void *din, ulong flags)
  100. {
  101. struct udevice *bus = dev->parent;
  102. struct mpc8xxx_priv *priv = dev_get_priv(bus);
  103. spi8xxx_t *spi = priv->spi;
  104. struct dm_spi_slave_platdata *platdata = dev_get_parent_platdata(dev);
  105. u32 tmpdin = 0, tmpdout = 0, n;
  106. const u8 *cout = dout;
  107. u8 *cin = din;
  108. debug("%s: slave %s:%u dout %08X din %08X bitlen %u\n", __func__,
  109. bus->name, platdata->cs, (uint)dout, (uint)din, bitlen);
  110. if (platdata->cs >= priv->cs_count) {
  111. dev_err(dev, "chip select index %d too large (cs_count=%d)\n",
  112. platdata->cs, priv->cs_count);
  113. return -EINVAL;
  114. }
  115. if (bitlen % 8) {
  116. printf("*** spi_xfer: bitlen must be multiple of 8\n");
  117. return -ENOTSUPP;
  118. }
  119. if (flags & SPI_XFER_BEGIN)
  120. mpc8xxx_spi_cs_activate(dev);
  121. /* Clear all SPI events */
  122. setbits_be32(&spi->event, 0xffffffff);
  123. n = bitlen / 8;
  124. /* Handle data in 8-bit chunks */
  125. while (n--) {
  126. ulong start;
  127. if (cout)
  128. tmpdout = *cout++;
  129. /* Write the data out */
  130. out_be32(&spi->tx, tmpdout);
  131. debug("*** %s: ... %08x written\n", __func__, tmpdout);
  132. /*
  133. * Wait for SPI transmit to get out
  134. * or time out (1 second = 1000 ms)
  135. * The NE event must be read and cleared first
  136. */
  137. start = get_timer(0);
  138. do {
  139. u32 event = in_be32(&spi->event);
  140. bool have_ne = event & SPI_EV_NE;
  141. bool have_nf = event & SPI_EV_NF;
  142. if (!have_ne)
  143. continue;
  144. tmpdin = in_be32(&spi->rx);
  145. setbits_be32(&spi->event, SPI_EV_NE);
  146. if (cin)
  147. *cin++ = tmpdin;
  148. /*
  149. * Only bail when we've had both NE and NF events.
  150. * This will cause timeouts on RO devices, so maybe
  151. * in the future put an arbitrary delay after writing
  152. * the device. Arbitrary delays suck, though...
  153. */
  154. if (have_nf)
  155. break;
  156. mdelay(1);
  157. } while (get_timer(start) < SPI_TIMEOUT);
  158. if (get_timer(start) >= SPI_TIMEOUT) {
  159. debug("*** %s: Time out during SPI transfer\n",
  160. __func__);
  161. return -ETIMEDOUT;
  162. }
  163. debug("*** %s: transfer ended. Value=%08x\n", __func__, tmpdin);
  164. }
  165. if (flags & SPI_XFER_END)
  166. mpc8xxx_spi_cs_deactivate(dev);
  167. return 0;
  168. }
  169. static int mpc8xxx_spi_set_speed(struct udevice *dev, uint speed)
  170. {
  171. struct mpc8xxx_priv *priv = dev_get_priv(dev);
  172. spi8xxx_t *spi = priv->spi;
  173. u32 bits, mask, div16, pm;
  174. u32 mode;
  175. ulong clk;
  176. clk = priv->clk_rate;
  177. if (clk / 64 > speed) {
  178. div16 = SPI_MODE_DIV16;
  179. clk /= 16;
  180. } else {
  181. div16 = 0;
  182. }
  183. pm = (clk - 1)/(4*speed) + 1;
  184. if (pm > 16) {
  185. dev_err(dev, "requested speed %u too small\n", speed);
  186. return -EINVAL;
  187. }
  188. pm--;
  189. bits = div16 | (pm << SPI_MODE_PM_SHIFT);
  190. mask = SPI_MODE_DIV16 | SPI_MODE_PM_MASK;
  191. mode = in_be32(&spi->mode);
  192. if ((mode & mask) != bits) {
  193. /* Must clear mode[EN] while changing speed. */
  194. mode &= ~(mask | SPI_MODE_EN);
  195. out_be32(&spi->mode, mode);
  196. mode |= bits;
  197. out_be32(&spi->mode, mode);
  198. mode |= SPI_MODE_EN;
  199. out_be32(&spi->mode, mode);
  200. }
  201. debug("requested speed %u, set speed to %lu/(%s4*%u) == %lu\n",
  202. speed, priv->clk_rate, div16 ? "16*" : "", pm + 1,
  203. clk/(4*(pm + 1)));
  204. return 0;
  205. }
  206. static int mpc8xxx_spi_set_mode(struct udevice *dev, uint mode)
  207. {
  208. /* TODO(mario.six@gdsys.cc): Using SPI_CPHA (for clock phase) and
  209. * SPI_CPOL (for clock polarity) should work
  210. */
  211. return 0;
  212. }
  213. static const struct dm_spi_ops mpc8xxx_spi_ops = {
  214. .xfer = mpc8xxx_spi_xfer,
  215. .set_speed = mpc8xxx_spi_set_speed,
  216. .set_mode = mpc8xxx_spi_set_mode,
  217. /*
  218. * cs_info is not needed, since we require all chip selects to be
  219. * in the device tree explicitly
  220. */
  221. };
  222. static const struct udevice_id mpc8xxx_spi_ids[] = {
  223. { .compatible = "fsl,spi" },
  224. { }
  225. };
  226. U_BOOT_DRIVER(mpc8xxx_spi) = {
  227. .name = "mpc8xxx_spi",
  228. .id = UCLASS_SPI,
  229. .of_match = mpc8xxx_spi_ids,
  230. .ops = &mpc8xxx_spi_ops,
  231. .ofdata_to_platdata = mpc8xxx_spi_ofdata_to_platdata,
  232. .probe = mpc8xxx_spi_probe,
  233. .priv_auto_alloc_size = sizeof(struct mpc8xxx_priv),
  234. };