fsl_qspi.c 24 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Freescale QuadSPI driver.
  4. *
  5. * Copyright (C) 2013 Freescale Semiconductor, Inc.
  6. * Copyright (C) 2018 Bootlin
  7. * Copyright (C) 2018 exceet electronics GmbH
  8. * Copyright (C) 2018 Kontron Electronics GmbH
  9. * Copyright 2019-2020 NXP
  10. *
  11. * This driver is a ported version of Linux Freescale QSPI driver taken from
  12. * v5.5-rc1 tag having following information.
  13. *
  14. * Transition to SPI MEM interface:
  15. * Authors:
  16. * Boris Brezillon <bbrezillon@kernel.org>
  17. * Frieder Schrempf <frieder.schrempf@kontron.de>
  18. * Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
  19. * Suresh Gupta <suresh.gupta@nxp.com>
  20. *
  21. * Based on the original fsl-quadspi.c spi-nor driver.
  22. * Transition to spi-mem in spi-fsl-qspi.c
  23. */
  24. #include <common.h>
  25. #include <log.h>
  26. #include <asm/io.h>
  27. #include <linux/bitops.h>
  28. #include <linux/delay.h>
  29. #include <linux/libfdt.h>
  30. #include <linux/sizes.h>
  31. #include <linux/iopoll.h>
  32. #include <dm.h>
  33. #include <linux/iopoll.h>
  34. #include <linux/sizes.h>
  35. #include <linux/err.h>
  36. #include <spi.h>
  37. #include <spi-mem.h>
  38. DECLARE_GLOBAL_DATA_PTR;
  39. /*
  40. * The driver only uses one single LUT entry, that is updated on
  41. * each call of exec_op(). Index 0 is preset at boot with a basic
  42. * read operation, so let's use the last entry (15).
  43. */
  44. #define SEQID_LUT 15
  45. #define SEQID_LUT_AHB 14
  46. /* Registers used by the driver */
  47. #define QUADSPI_MCR 0x00
  48. #define QUADSPI_MCR_RESERVED_MASK GENMASK(19, 16)
  49. #define QUADSPI_MCR_MDIS_MASK BIT(14)
  50. #define QUADSPI_MCR_CLR_TXF_MASK BIT(11)
  51. #define QUADSPI_MCR_CLR_RXF_MASK BIT(10)
  52. #define QUADSPI_MCR_DDR_EN_MASK BIT(7)
  53. #define QUADSPI_MCR_END_CFG_MASK GENMASK(3, 2)
  54. #define QUADSPI_MCR_SWRSTHD_MASK BIT(1)
  55. #define QUADSPI_MCR_SWRSTSD_MASK BIT(0)
  56. #define QUADSPI_IPCR 0x08
  57. #define QUADSPI_IPCR_SEQID(x) ((x) << 24)
  58. #define QUADSPI_FLSHCR 0x0c
  59. #define QUADSPI_FLSHCR_TCSS_MASK GENMASK(3, 0)
  60. #define QUADSPI_FLSHCR_TCSH_MASK GENMASK(11, 8)
  61. #define QUADSPI_FLSHCR_TDH_MASK GENMASK(17, 16)
  62. #define QUADSPI_BUF3CR 0x1c
  63. #define QUADSPI_BUF3CR_ALLMST_MASK BIT(31)
  64. #define QUADSPI_BUF3CR_ADATSZ(x) ((x) << 8)
  65. #define QUADSPI_BUF3CR_ADATSZ_MASK GENMASK(15, 8)
  66. #define QUADSPI_BFGENCR 0x20
  67. #define QUADSPI_BFGENCR_SEQID(x) ((x) << 12)
  68. #define QUADSPI_BUF0IND 0x30
  69. #define QUADSPI_BUF1IND 0x34
  70. #define QUADSPI_BUF2IND 0x38
  71. #define QUADSPI_SFAR 0x100
  72. #define QUADSPI_SMPR 0x108
  73. #define QUADSPI_SMPR_DDRSMP_MASK GENMASK(18, 16)
  74. #define QUADSPI_SMPR_FSDLY_MASK BIT(6)
  75. #define QUADSPI_SMPR_FSPHS_MASK BIT(5)
  76. #define QUADSPI_SMPR_HSENA_MASK BIT(0)
  77. #define QUADSPI_RBCT 0x110
  78. #define QUADSPI_RBCT_WMRK_MASK GENMASK(4, 0)
  79. #define QUADSPI_RBCT_RXBRD_USEIPS BIT(8)
  80. #define QUADSPI_TBDR 0x154
  81. #define QUADSPI_SR 0x15c
  82. #define QUADSPI_SR_IP_ACC_MASK BIT(1)
  83. #define QUADSPI_SR_AHB_ACC_MASK BIT(2)
  84. #define QUADSPI_FR 0x160
  85. #define QUADSPI_FR_TFF_MASK BIT(0)
  86. #define QUADSPI_RSER 0x164
  87. #define QUADSPI_RSER_TFIE BIT(0)
  88. #define QUADSPI_SPTRCLR 0x16c
  89. #define QUADSPI_SPTRCLR_IPPTRC BIT(8)
  90. #define QUADSPI_SPTRCLR_BFPTRC BIT(0)
  91. #define QUADSPI_SFA1AD 0x180
  92. #define QUADSPI_SFA2AD 0x184
  93. #define QUADSPI_SFB1AD 0x188
  94. #define QUADSPI_SFB2AD 0x18c
  95. #define QUADSPI_RBDR(x) (0x200 + ((x) * 4))
  96. #define QUADSPI_LUTKEY 0x300
  97. #define QUADSPI_LUTKEY_VALUE 0x5AF05AF0
  98. #define QUADSPI_LCKCR 0x304
  99. #define QUADSPI_LCKER_LOCK BIT(0)
  100. #define QUADSPI_LCKER_UNLOCK BIT(1)
  101. #define QUADSPI_LUT_BASE 0x310
  102. #define QUADSPI_LUT_OFFSET (SEQID_LUT * 4 * 4)
  103. #define QUADSPI_LUT_REG(idx) \
  104. (QUADSPI_LUT_BASE + QUADSPI_LUT_OFFSET + (idx) * 4)
  105. #define QUADSPI_AHB_LUT_OFFSET (SEQID_LUT_AHB * 4 * 4)
  106. #define QUADSPI_AHB_LUT_REG(idx) \
  107. (QUADSPI_LUT_BASE + QUADSPI_AHB_LUT_OFFSET + (idx) * 4)
  108. /* Instruction set for the LUT register */
  109. #define LUT_STOP 0
  110. #define LUT_CMD 1
  111. #define LUT_ADDR 2
  112. #define LUT_DUMMY 3
  113. #define LUT_MODE 4
  114. #define LUT_MODE2 5
  115. #define LUT_MODE4 6
  116. #define LUT_FSL_READ 7
  117. #define LUT_FSL_WRITE 8
  118. #define LUT_JMP_ON_CS 9
  119. #define LUT_ADDR_DDR 10
  120. #define LUT_MODE_DDR 11
  121. #define LUT_MODE2_DDR 12
  122. #define LUT_MODE4_DDR 13
  123. #define LUT_FSL_READ_DDR 14
  124. #define LUT_FSL_WRITE_DDR 15
  125. #define LUT_DATA_LEARN 16
  126. /*
  127. * The PAD definitions for LUT register.
  128. *
  129. * The pad stands for the number of IO lines [0:3].
  130. * For example, the quad read needs four IO lines,
  131. * so you should use LUT_PAD(4).
  132. */
  133. #define LUT_PAD(x) (fls(x) - 1)
  134. /*
  135. * Macro for constructing the LUT entries with the following
  136. * register layout:
  137. *
  138. * ---------------------------------------------------
  139. * | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 |
  140. * ---------------------------------------------------
  141. */
  142. #define LUT_DEF(idx, ins, pad, opr) \
  143. ((((ins) << 10) | ((pad) << 8) | (opr)) << (((idx) % 2) * 16))
  144. /* Controller needs driver to swap endianness */
  145. #define QUADSPI_QUIRK_SWAP_ENDIAN BIT(0)
  146. /* Controller needs 4x internal clock */
  147. #define QUADSPI_QUIRK_4X_INT_CLK BIT(1)
  148. /*
  149. * TKT253890, the controller needs the driver to fill the txfifo with
  150. * 16 bytes at least to trigger a data transfer, even though the extra
  151. * data won't be transferred.
  152. */
  153. #define QUADSPI_QUIRK_TKT253890 BIT(2)
  154. /* TKT245618, the controller cannot wake up from wait mode */
  155. #define QUADSPI_QUIRK_TKT245618 BIT(3)
  156. /*
  157. * Controller adds QSPI_AMBA_BASE (base address of the mapped memory)
  158. * internally. No need to add it when setting SFXXAD and SFAR registers
  159. */
  160. #define QUADSPI_QUIRK_BASE_INTERNAL BIT(4)
  161. /*
  162. * Controller uses TDH bits in register QUADSPI_FLSHCR.
  163. * They need to be set in accordance with the DDR/SDR mode.
  164. */
  165. #define QUADSPI_QUIRK_USE_TDH_SETTING BIT(5)
  166. /*
  167. * Controller only has Two CS on flash A, no flash B port
  168. */
  169. #define QUADSPI_QUIRK_SINGLE_BUS BIT(6)
  170. struct fsl_qspi_devtype_data {
  171. unsigned int rxfifo;
  172. unsigned int txfifo;
  173. unsigned int ahb_buf_size;
  174. unsigned int quirks;
  175. bool little_endian;
  176. };
  177. static const struct fsl_qspi_devtype_data vybrid_data = {
  178. .rxfifo = SZ_128,
  179. .txfifo = SZ_64,
  180. .ahb_buf_size = SZ_1K,
  181. .quirks = QUADSPI_QUIRK_SWAP_ENDIAN,
  182. .little_endian = true,
  183. };
  184. static const struct fsl_qspi_devtype_data imx6sx_data = {
  185. .rxfifo = SZ_128,
  186. .txfifo = SZ_512,
  187. .ahb_buf_size = SZ_1K,
  188. .quirks = QUADSPI_QUIRK_4X_INT_CLK | QUADSPI_QUIRK_TKT245618,
  189. .little_endian = true,
  190. };
  191. static const struct fsl_qspi_devtype_data imx7d_data = {
  192. .rxfifo = SZ_128,
  193. .txfifo = SZ_512,
  194. .ahb_buf_size = SZ_1K,
  195. .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK |
  196. QUADSPI_QUIRK_USE_TDH_SETTING,
  197. .little_endian = true,
  198. };
  199. static const struct fsl_qspi_devtype_data imx6ul_data = {
  200. .rxfifo = SZ_128,
  201. .txfifo = SZ_512,
  202. .ahb_buf_size = SZ_1K,
  203. .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK |
  204. QUADSPI_QUIRK_USE_TDH_SETTING,
  205. .little_endian = true,
  206. };
  207. static const struct fsl_qspi_devtype_data imx7ulp_data = {
  208. .rxfifo = SZ_64,
  209. .txfifo = SZ_64,
  210. .ahb_buf_size = SZ_128,
  211. .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK |
  212. QUADSPI_QUIRK_USE_TDH_SETTING | QUADSPI_QUIRK_SINGLE_BUS,
  213. .little_endian = true,
  214. };
  215. static const struct fsl_qspi_devtype_data ls1021a_data = {
  216. .rxfifo = SZ_128,
  217. .txfifo = SZ_64,
  218. .ahb_buf_size = SZ_1K,
  219. .quirks = 0,
  220. .little_endian = false,
  221. };
  222. static const struct fsl_qspi_devtype_data ls1088a_data = {
  223. .rxfifo = SZ_128,
  224. .txfifo = SZ_128,
  225. .ahb_buf_size = SZ_1K,
  226. .quirks = QUADSPI_QUIRK_TKT253890,
  227. .little_endian = true,
  228. };
  229. static const struct fsl_qspi_devtype_data ls2080a_data = {
  230. .rxfifo = SZ_128,
  231. .txfifo = SZ_64,
  232. .ahb_buf_size = SZ_1K,
  233. .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_BASE_INTERNAL,
  234. .little_endian = true,
  235. };
  236. struct fsl_qspi {
  237. struct udevice *dev;
  238. void __iomem *iobase;
  239. void __iomem *ahb_addr;
  240. u32 memmap_phy;
  241. u32 memmap_size;
  242. const struct fsl_qspi_devtype_data *devtype_data;
  243. int selected;
  244. };
  245. static inline int needs_swap_endian(struct fsl_qspi *q)
  246. {
  247. return q->devtype_data->quirks & QUADSPI_QUIRK_SWAP_ENDIAN;
  248. }
  249. static inline int needs_4x_clock(struct fsl_qspi *q)
  250. {
  251. return q->devtype_data->quirks & QUADSPI_QUIRK_4X_INT_CLK;
  252. }
  253. static inline int needs_fill_txfifo(struct fsl_qspi *q)
  254. {
  255. return q->devtype_data->quirks & QUADSPI_QUIRK_TKT253890;
  256. }
  257. static inline int needs_wakeup_wait_mode(struct fsl_qspi *q)
  258. {
  259. return q->devtype_data->quirks & QUADSPI_QUIRK_TKT245618;
  260. }
  261. static inline int needs_amba_base_offset(struct fsl_qspi *q)
  262. {
  263. return !(q->devtype_data->quirks & QUADSPI_QUIRK_BASE_INTERNAL);
  264. }
  265. static inline int needs_tdh_setting(struct fsl_qspi *q)
  266. {
  267. return q->devtype_data->quirks & QUADSPI_QUIRK_USE_TDH_SETTING;
  268. }
  269. static inline int needs_single_bus(struct fsl_qspi *q)
  270. {
  271. return q->devtype_data->quirks & QUADSPI_QUIRK_SINGLE_BUS;
  272. }
  273. /*
  274. * An IC bug makes it necessary to rearrange the 32-bit data.
  275. * Later chips, such as IMX6SLX, have fixed this bug.
  276. */
  277. static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi *q, u32 a)
  278. {
  279. return needs_swap_endian(q) ? __swab32(a) : a;
  280. }
  281. /*
  282. * R/W functions for big- or little-endian registers:
  283. * The QSPI controller's endianness is independent of
  284. * the CPU core's endianness. So far, although the CPU
  285. * core is little-endian the QSPI controller can use
  286. * big-endian or little-endian.
  287. */
  288. static void qspi_writel(struct fsl_qspi *q, u32 val, void __iomem *addr)
  289. {
  290. if (q->devtype_data->little_endian)
  291. out_le32(addr, val);
  292. else
  293. out_be32(addr, val);
  294. }
  295. static u32 qspi_readl(struct fsl_qspi *q, void __iomem *addr)
  296. {
  297. if (q->devtype_data->little_endian)
  298. return in_le32(addr);
  299. return in_be32(addr);
  300. }
  301. static int fsl_qspi_check_buswidth(struct fsl_qspi *q, u8 width)
  302. {
  303. switch (width) {
  304. case 1:
  305. case 2:
  306. case 4:
  307. return 0;
  308. }
  309. return -ENOTSUPP;
  310. }
  311. static bool fsl_qspi_supports_op(struct spi_slave *slave,
  312. const struct spi_mem_op *op)
  313. {
  314. struct fsl_qspi *q = dev_get_priv(slave->dev->parent);
  315. int ret;
  316. ret = fsl_qspi_check_buswidth(q, op->cmd.buswidth);
  317. if (op->addr.nbytes)
  318. ret |= fsl_qspi_check_buswidth(q, op->addr.buswidth);
  319. if (op->dummy.nbytes)
  320. ret |= fsl_qspi_check_buswidth(q, op->dummy.buswidth);
  321. if (op->data.nbytes)
  322. ret |= fsl_qspi_check_buswidth(q, op->data.buswidth);
  323. if (ret)
  324. return false;
  325. /*
  326. * The number of instructions needed for the op, needs
  327. * to fit into a single LUT entry.
  328. */
  329. if (op->addr.nbytes +
  330. (op->dummy.nbytes ? 1 : 0) +
  331. (op->data.nbytes ? 1 : 0) > 6)
  332. return false;
  333. /* Max 64 dummy clock cycles supported */
  334. if (op->dummy.nbytes &&
  335. (op->dummy.nbytes * 8 / op->dummy.buswidth > 64))
  336. return false;
  337. /* Max data length, check controller limits and alignment */
  338. if (op->data.dir == SPI_MEM_DATA_IN &&
  339. (op->data.nbytes > q->devtype_data->ahb_buf_size ||
  340. (op->data.nbytes > q->devtype_data->rxfifo - 4 &&
  341. !IS_ALIGNED(op->data.nbytes, 8))))
  342. return false;
  343. if (op->data.dir == SPI_MEM_DATA_OUT &&
  344. op->data.nbytes > q->devtype_data->txfifo)
  345. return false;
  346. return true;
  347. }
  348. static void fsl_qspi_prepare_lut(struct fsl_qspi *q,
  349. const struct spi_mem_op *op)
  350. {
  351. void __iomem *base = q->iobase;
  352. u32 lutval[4] = {};
  353. int lutidx = 1, i;
  354. lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth),
  355. op->cmd.opcode);
  356. if (IS_ENABLED(CONFIG_FSL_QSPI_AHB_FULL_MAP)) {
  357. if (op->addr.nbytes) {
  358. lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_ADDR,
  359. LUT_PAD(op->addr.buswidth),
  360. (op->addr.nbytes == 4) ? 0x20 : 0x18);
  361. lutidx++;
  362. }
  363. } else {
  364. /*
  365. * For some unknown reason, using LUT_ADDR doesn't work in some
  366. * cases (at least with only one byte long addresses), so
  367. * let's use LUT_MODE to write the address bytes one by one
  368. */
  369. for (i = 0; i < op->addr.nbytes; i++) {
  370. u8 addrbyte = op->addr.val >> (8 * (op->addr.nbytes - i - 1));
  371. lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_MODE,
  372. LUT_PAD(op->addr.buswidth),
  373. addrbyte);
  374. lutidx++;
  375. }
  376. }
  377. if (op->dummy.nbytes) {
  378. lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_DUMMY,
  379. LUT_PAD(op->dummy.buswidth),
  380. op->dummy.nbytes * 8 /
  381. op->dummy.buswidth);
  382. lutidx++;
  383. }
  384. if (op->data.nbytes) {
  385. lutval[lutidx / 2] |= LUT_DEF(lutidx,
  386. op->data.dir == SPI_MEM_DATA_IN ?
  387. LUT_FSL_READ : LUT_FSL_WRITE,
  388. LUT_PAD(op->data.buswidth),
  389. 0);
  390. lutidx++;
  391. }
  392. lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_STOP, 0, 0);
  393. /* unlock LUT */
  394. qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
  395. qspi_writel(q, QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
  396. dev_dbg(q->dev, "CMD[%x] lutval[0:%x \t 1:%x \t 2:%x \t 3:%x]\n",
  397. op->cmd.opcode, lutval[0], lutval[1], lutval[2], lutval[3]);
  398. /* fill LUT */
  399. for (i = 0; i < ARRAY_SIZE(lutval); i++)
  400. qspi_writel(q, lutval[i], base + QUADSPI_LUT_REG(i));
  401. if (IS_ENABLED(CONFIG_FSL_QSPI_AHB_FULL_MAP)) {
  402. if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN &&
  403. op->addr.nbytes) {
  404. for (i = 0; i < ARRAY_SIZE(lutval); i++)
  405. qspi_writel(q, lutval[i], base + QUADSPI_AHB_LUT_REG(i));
  406. }
  407. }
  408. /* lock LUT */
  409. qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
  410. qspi_writel(q, QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);
  411. }
  412. /*
  413. * If we have changed the content of the flash by writing or erasing, or if we
  414. * read from flash with a different offset into the page buffer, we need to
  415. * invalidate the AHB buffer. If we do not do so, we may read out the wrong
  416. * data. The spec tells us reset the AHB domain and Serial Flash domain at
  417. * the same time.
  418. */
  419. static void fsl_qspi_invalidate(struct fsl_qspi *q)
  420. {
  421. u32 reg;
  422. reg = qspi_readl(q, q->iobase + QUADSPI_MCR);
  423. reg |= QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK;
  424. qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
  425. /*
  426. * The minimum delay : 1 AHB + 2 SFCK clocks.
  427. * Delay 1 us is enough.
  428. */
  429. udelay(1);
  430. reg &= ~(QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK);
  431. qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
  432. }
  433. static void fsl_qspi_select_mem(struct fsl_qspi *q, struct spi_slave *slave)
  434. {
  435. struct dm_spi_slave_platdata *plat =
  436. dev_get_parent_platdata(slave->dev);
  437. if (q->selected == plat->cs)
  438. return;
  439. q->selected = plat->cs;
  440. fsl_qspi_invalidate(q);
  441. }
  442. static u32 fsl_qspi_memsize_per_cs(struct fsl_qspi *q)
  443. {
  444. if (IS_ENABLED(CONFIG_FSL_QSPI_AHB_FULL_MAP)) {
  445. if (needs_single_bus(q))
  446. return q->memmap_size / 2;
  447. else
  448. return q->memmap_size / 4;
  449. } else {
  450. return ALIGN(q->devtype_data->ahb_buf_size, 0x400);
  451. }
  452. }
  453. static void fsl_qspi_read_ahb(struct fsl_qspi *q, const struct spi_mem_op *op)
  454. {
  455. void __iomem *ahb_read_addr = q->ahb_addr;
  456. if (IS_ENABLED(CONFIG_FSL_QSPI_AHB_FULL_MAP)) {
  457. if (op->addr.nbytes)
  458. ahb_read_addr += op->addr.val;
  459. }
  460. memcpy_fromio(op->data.buf.in,
  461. ahb_read_addr + q->selected * fsl_qspi_memsize_per_cs(q),
  462. op->data.nbytes);
  463. }
  464. static void fsl_qspi_fill_txfifo(struct fsl_qspi *q,
  465. const struct spi_mem_op *op)
  466. {
  467. void __iomem *base = q->iobase;
  468. int i;
  469. u32 val;
  470. for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 4); i += 4) {
  471. memcpy(&val, op->data.buf.out + i, 4);
  472. val = fsl_qspi_endian_xchg(q, val);
  473. qspi_writel(q, val, base + QUADSPI_TBDR);
  474. }
  475. if (i < op->data.nbytes) {
  476. memcpy(&val, op->data.buf.out + i, op->data.nbytes - i);
  477. val = fsl_qspi_endian_xchg(q, val);
  478. qspi_writel(q, val, base + QUADSPI_TBDR);
  479. }
  480. if (needs_fill_txfifo(q)) {
  481. for (i = op->data.nbytes; i < 16; i += 4)
  482. qspi_writel(q, 0, base + QUADSPI_TBDR);
  483. }
  484. }
  485. static void fsl_qspi_read_rxfifo(struct fsl_qspi *q,
  486. const struct spi_mem_op *op)
  487. {
  488. void __iomem *base = q->iobase;
  489. int i;
  490. u8 *buf = op->data.buf.in;
  491. u32 val;
  492. for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 4); i += 4) {
  493. val = qspi_readl(q, base + QUADSPI_RBDR(i / 4));
  494. val = fsl_qspi_endian_xchg(q, val);
  495. memcpy(buf + i, &val, 4);
  496. }
  497. if (i < op->data.nbytes) {
  498. val = qspi_readl(q, base + QUADSPI_RBDR(i / 4));
  499. val = fsl_qspi_endian_xchg(q, val);
  500. memcpy(buf + i, &val, op->data.nbytes - i);
  501. }
  502. }
  503. static int fsl_qspi_readl_poll_tout(struct fsl_qspi *q, void __iomem *base,
  504. u32 mask, u32 delay_us, u32 timeout_us)
  505. {
  506. u32 reg;
  507. if (!q->devtype_data->little_endian)
  508. mask = (u32)cpu_to_be32(mask);
  509. return readl_poll_timeout(base, reg, !(reg & mask), timeout_us);
  510. }
  511. static int fsl_qspi_do_op(struct fsl_qspi *q, const struct spi_mem_op *op)
  512. {
  513. void __iomem *base = q->iobase;
  514. int err = 0;
  515. /*
  516. * Always start the sequence at the same index since we update
  517. * the LUT at each exec_op() call. And also specify the DATA
  518. * length, since it's has not been specified in the LUT.
  519. */
  520. qspi_writel(q, op->data.nbytes | QUADSPI_IPCR_SEQID(SEQID_LUT),
  521. base + QUADSPI_IPCR);
  522. /* wait for the controller being ready */
  523. err = fsl_qspi_readl_poll_tout(q, base + QUADSPI_SR,
  524. (QUADSPI_SR_IP_ACC_MASK |
  525. QUADSPI_SR_AHB_ACC_MASK),
  526. 10, 1000);
  527. if (!err && op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN)
  528. fsl_qspi_read_rxfifo(q, op);
  529. return err;
  530. }
  531. static int fsl_qspi_exec_op(struct spi_slave *slave,
  532. const struct spi_mem_op *op)
  533. {
  534. struct fsl_qspi *q = dev_get_priv(slave->dev->parent);
  535. void __iomem *base = q->iobase;
  536. u32 addr_offset = 0;
  537. int err = 0;
  538. /* wait for the controller being ready */
  539. fsl_qspi_readl_poll_tout(q, base + QUADSPI_SR, (QUADSPI_SR_IP_ACC_MASK |
  540. QUADSPI_SR_AHB_ACC_MASK), 10, 1000);
  541. fsl_qspi_select_mem(q, slave);
  542. if (needs_amba_base_offset(q))
  543. addr_offset = q->memmap_phy;
  544. if (IS_ENABLED(CONFIG_FSL_QSPI_AHB_FULL_MAP)) {
  545. if (op->addr.nbytes)
  546. addr_offset += op->addr.val;
  547. }
  548. qspi_writel(q,
  549. q->selected * fsl_qspi_memsize_per_cs(q) + addr_offset,
  550. base + QUADSPI_SFAR);
  551. qspi_writel(q, qspi_readl(q, base + QUADSPI_MCR) |
  552. QUADSPI_MCR_CLR_RXF_MASK | QUADSPI_MCR_CLR_TXF_MASK,
  553. base + QUADSPI_MCR);
  554. qspi_writel(q, QUADSPI_SPTRCLR_BFPTRC | QUADSPI_SPTRCLR_IPPTRC,
  555. base + QUADSPI_SPTRCLR);
  556. fsl_qspi_prepare_lut(q, op);
  557. /*
  558. * If we have large chunks of data, we read them through the AHB bus
  559. * by accessing the mapped memory. In all other cases we use
  560. * IP commands to access the flash.
  561. */
  562. if (op->data.nbytes > (q->devtype_data->rxfifo - 4) &&
  563. op->data.dir == SPI_MEM_DATA_IN) {
  564. fsl_qspi_read_ahb(q, op);
  565. } else {
  566. qspi_writel(q, QUADSPI_RBCT_WMRK_MASK |
  567. QUADSPI_RBCT_RXBRD_USEIPS, base + QUADSPI_RBCT);
  568. if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT)
  569. fsl_qspi_fill_txfifo(q, op);
  570. err = fsl_qspi_do_op(q, op);
  571. }
  572. /* Invalidate the data in the AHB buffer. */
  573. fsl_qspi_invalidate(q);
  574. return err;
  575. }
  576. static int fsl_qspi_adjust_op_size(struct spi_slave *slave,
  577. struct spi_mem_op *op)
  578. {
  579. struct fsl_qspi *q = dev_get_priv(slave->dev->parent);
  580. if (op->data.dir == SPI_MEM_DATA_OUT) {
  581. if (op->data.nbytes > q->devtype_data->txfifo)
  582. op->data.nbytes = q->devtype_data->txfifo;
  583. } else {
  584. if (op->data.nbytes > q->devtype_data->ahb_buf_size)
  585. op->data.nbytes = q->devtype_data->ahb_buf_size;
  586. else if (op->data.nbytes > (q->devtype_data->rxfifo - 4))
  587. op->data.nbytes = ALIGN_DOWN(op->data.nbytes, 8);
  588. }
  589. return 0;
  590. }
  591. static int fsl_qspi_default_setup(struct fsl_qspi *q)
  592. {
  593. void __iomem *base = q->iobase;
  594. u32 reg, addr_offset = 0, memsize_cs;
  595. /* Reset the module */
  596. qspi_writel(q, QUADSPI_MCR_SWRSTSD_MASK | QUADSPI_MCR_SWRSTHD_MASK,
  597. base + QUADSPI_MCR);
  598. udelay(1);
  599. /* Disable the module */
  600. qspi_writel(q, QUADSPI_MCR_MDIS_MASK | QUADSPI_MCR_RESERVED_MASK,
  601. base + QUADSPI_MCR);
  602. /*
  603. * Previous boot stages (BootROM, bootloader) might have used DDR
  604. * mode and did not clear the TDH bits. As we currently use SDR mode
  605. * only, clear the TDH bits if necessary.
  606. */
  607. if (needs_tdh_setting(q))
  608. qspi_writel(q, qspi_readl(q, base + QUADSPI_FLSHCR) &
  609. ~QUADSPI_FLSHCR_TDH_MASK,
  610. base + QUADSPI_FLSHCR);
  611. reg = qspi_readl(q, base + QUADSPI_SMPR);
  612. qspi_writel(q, reg & ~(QUADSPI_SMPR_FSDLY_MASK
  613. | QUADSPI_SMPR_FSPHS_MASK
  614. | QUADSPI_SMPR_HSENA_MASK
  615. | QUADSPI_SMPR_DDRSMP_MASK), base + QUADSPI_SMPR);
  616. /* We only use the buffer3 for AHB read */
  617. qspi_writel(q, 0, base + QUADSPI_BUF0IND);
  618. qspi_writel(q, 0, base + QUADSPI_BUF1IND);
  619. qspi_writel(q, 0, base + QUADSPI_BUF2IND);
  620. if (IS_ENABLED(CONFIG_FSL_QSPI_AHB_FULL_MAP))
  621. qspi_writel(q, QUADSPI_BFGENCR_SEQID(SEQID_LUT_AHB),
  622. q->iobase + QUADSPI_BFGENCR);
  623. else
  624. qspi_writel(q, QUADSPI_BFGENCR_SEQID(SEQID_LUT),
  625. q->iobase + QUADSPI_BFGENCR);
  626. qspi_writel(q, QUADSPI_RBCT_WMRK_MASK, base + QUADSPI_RBCT);
  627. qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK |
  628. QUADSPI_BUF3CR_ADATSZ(q->devtype_data->ahb_buf_size / 8),
  629. base + QUADSPI_BUF3CR);
  630. if (needs_amba_base_offset(q))
  631. addr_offset = q->memmap_phy;
  632. /*
  633. * In HW there can be a maximum of four chips on two buses with
  634. * two chip selects on each bus. We use four chip selects in SW
  635. * to differentiate between the four chips.
  636. * We use ahb_buf_size for each chip and set SFA1AD, SFA2AD, SFB1AD,
  637. * SFB2AD accordingly.
  638. */
  639. memsize_cs = fsl_qspi_memsize_per_cs(q);
  640. qspi_writel(q, memsize_cs + addr_offset,
  641. base + QUADSPI_SFA1AD);
  642. qspi_writel(q, memsize_cs * 2 + addr_offset,
  643. base + QUADSPI_SFA2AD);
  644. if (!needs_single_bus(q)) {
  645. qspi_writel(q, memsize_cs * 3 + addr_offset,
  646. base + QUADSPI_SFB1AD);
  647. qspi_writel(q, memsize_cs * 4 + addr_offset,
  648. base + QUADSPI_SFB2AD);
  649. }
  650. q->selected = -1;
  651. /* Enable the module */
  652. qspi_writel(q, QUADSPI_MCR_RESERVED_MASK | QUADSPI_MCR_END_CFG_MASK,
  653. base + QUADSPI_MCR);
  654. return 0;
  655. }
  656. static const struct spi_controller_mem_ops fsl_qspi_mem_ops = {
  657. .adjust_op_size = fsl_qspi_adjust_op_size,
  658. .supports_op = fsl_qspi_supports_op,
  659. .exec_op = fsl_qspi_exec_op,
  660. };
  661. static int fsl_qspi_probe(struct udevice *bus)
  662. {
  663. struct dm_spi_bus *dm_bus = bus->uclass_priv;
  664. struct fsl_qspi *q = dev_get_priv(bus);
  665. const void *blob = gd->fdt_blob;
  666. int node = dev_of_offset(bus);
  667. struct fdt_resource res;
  668. int ret;
  669. q->dev = bus;
  670. q->devtype_data = (struct fsl_qspi_devtype_data *)
  671. dev_get_driver_data(bus);
  672. /* find the resources */
  673. ret = fdt_get_named_resource(blob, node, "reg", "reg-names", "QuadSPI",
  674. &res);
  675. if (ret) {
  676. dev_err(bus, "Can't get regs base addresses(ret = %d)!\n", ret);
  677. return -ENOMEM;
  678. }
  679. q->iobase = map_physmem(res.start, res.end - res.start, MAP_NOCACHE);
  680. ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
  681. "QuadSPI-memory", &res);
  682. if (ret) {
  683. dev_err(bus, "Can't get AMBA base addresses(ret = %d)!\n", ret);
  684. return -ENOMEM;
  685. }
  686. q->ahb_addr = map_physmem(res.start, res.end - res.start, MAP_NOCACHE);
  687. q->memmap_phy = res.start;
  688. q->memmap_size = res.end - res.start;
  689. dm_bus->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
  690. 66000000);
  691. fsl_qspi_default_setup(q);
  692. return 0;
  693. }
  694. static int fsl_qspi_xfer(struct udevice *dev, unsigned int bitlen,
  695. const void *dout, void *din, unsigned long flags)
  696. {
  697. return 0;
  698. }
  699. static int fsl_qspi_claim_bus(struct udevice *dev)
  700. {
  701. return 0;
  702. }
  703. static int fsl_qspi_release_bus(struct udevice *dev)
  704. {
  705. return 0;
  706. }
  707. static int fsl_qspi_set_speed(struct udevice *bus, uint speed)
  708. {
  709. return 0;
  710. }
  711. static int fsl_qspi_set_mode(struct udevice *bus, uint mode)
  712. {
  713. return 0;
  714. }
  715. static const struct dm_spi_ops fsl_qspi_ops = {
  716. .claim_bus = fsl_qspi_claim_bus,
  717. .release_bus = fsl_qspi_release_bus,
  718. .xfer = fsl_qspi_xfer,
  719. .set_speed = fsl_qspi_set_speed,
  720. .set_mode = fsl_qspi_set_mode,
  721. .mem_ops = &fsl_qspi_mem_ops,
  722. };
  723. static const struct udevice_id fsl_qspi_ids[] = {
  724. { .compatible = "fsl,vf610-qspi", .data = (ulong)&vybrid_data, },
  725. { .compatible = "fsl,imx6sx-qspi", .data = (ulong)&imx6sx_data, },
  726. { .compatible = "fsl,imx6ul-qspi", .data = (ulong)&imx6ul_data, },
  727. { .compatible = "fsl,imx7d-qspi", .data = (ulong)&imx7d_data, },
  728. { .compatible = "fsl,imx7ulp-qspi", .data = (ulong)&imx7ulp_data, },
  729. { .compatible = "fsl,ls1021a-qspi", .data = (ulong)&ls1021a_data, },
  730. { .compatible = "fsl,ls1088a-qspi", .data = (ulong)&ls1088a_data, },
  731. { .compatible = "fsl,ls2080a-qspi", .data = (ulong)&ls2080a_data, },
  732. { }
  733. };
  734. U_BOOT_DRIVER(fsl_qspi) = {
  735. .name = "fsl_qspi",
  736. .id = UCLASS_SPI,
  737. .of_match = fsl_qspi_ids,
  738. .ops = &fsl_qspi_ops,
  739. .priv_auto_alloc_size = sizeof(struct fsl_qspi),
  740. .probe = fsl_qspi_probe,
  741. };