cadence_qspi.c 9.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2012
  4. * Altera Corporation <www.altera.com>
  5. */
  6. #include <common.h>
  7. #include <clk.h>
  8. #include <log.h>
  9. #include <asm-generic/io.h>
  10. #include <dm.h>
  11. #include <fdtdec.h>
  12. #include <malloc.h>
  13. #include <reset.h>
  14. #include <spi.h>
  15. #include <spi-mem.h>
  16. #include <dm/device_compat.h>
  17. #include <linux/err.h>
  18. #include <linux/errno.h>
  19. #include <linux/sizes.h>
  20. #include "cadence_qspi.h"
  21. #define CQSPI_STIG_READ 0
  22. #define CQSPI_STIG_WRITE 1
  23. #define CQSPI_READ 2
  24. #define CQSPI_WRITE 3
  25. static int cadence_spi_write_speed(struct udevice *bus, uint hz)
  26. {
  27. struct cadence_spi_platdata *plat = bus->platdata;
  28. struct cadence_spi_priv *priv = dev_get_priv(bus);
  29. cadence_qspi_apb_config_baudrate_div(priv->regbase,
  30. plat->ref_clk_hz, hz);
  31. /* Reconfigure delay timing if speed is changed. */
  32. cadence_qspi_apb_delay(priv->regbase, plat->ref_clk_hz, hz,
  33. plat->tshsl_ns, plat->tsd2d_ns,
  34. plat->tchsh_ns, plat->tslch_ns);
  35. return 0;
  36. }
  37. static int cadence_spi_read_id(void *reg_base, u8 len, u8 *idcode)
  38. {
  39. struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(0x9F, 1),
  40. SPI_MEM_OP_NO_ADDR,
  41. SPI_MEM_OP_NO_DUMMY,
  42. SPI_MEM_OP_DATA_IN(len, idcode, 1));
  43. return cadence_qspi_apb_command_read(reg_base, &op);
  44. }
  45. /* Calibration sequence to determine the read data capture delay register */
  46. static int spi_calibration(struct udevice *bus, uint hz)
  47. {
  48. struct cadence_spi_priv *priv = dev_get_priv(bus);
  49. void *base = priv->regbase;
  50. unsigned int idcode = 0, temp = 0;
  51. int err = 0, i, range_lo = -1, range_hi = -1;
  52. /* start with slowest clock (1 MHz) */
  53. cadence_spi_write_speed(bus, 1000000);
  54. /* configure the read data capture delay register to 0 */
  55. cadence_qspi_apb_readdata_capture(base, 1, 0);
  56. /* Enable QSPI */
  57. cadence_qspi_apb_controller_enable(base);
  58. /* read the ID which will be our golden value */
  59. err = cadence_spi_read_id(base, 3, (u8 *)&idcode);
  60. if (err) {
  61. puts("SF: Calibration failed (read)\n");
  62. return err;
  63. }
  64. /* use back the intended clock and find low range */
  65. cadence_spi_write_speed(bus, hz);
  66. for (i = 0; i < CQSPI_READ_CAPTURE_MAX_DELAY; i++) {
  67. /* Disable QSPI */
  68. cadence_qspi_apb_controller_disable(base);
  69. /* reconfigure the read data capture delay register */
  70. cadence_qspi_apb_readdata_capture(base, 1, i);
  71. /* Enable back QSPI */
  72. cadence_qspi_apb_controller_enable(base);
  73. /* issue a RDID to get the ID value */
  74. err = cadence_spi_read_id(base, 3, (u8 *)&temp);
  75. if (err) {
  76. puts("SF: Calibration failed (read)\n");
  77. return err;
  78. }
  79. /* search for range lo */
  80. if (range_lo == -1 && temp == idcode) {
  81. range_lo = i;
  82. continue;
  83. }
  84. /* search for range hi */
  85. if (range_lo != -1 && temp != idcode) {
  86. range_hi = i - 1;
  87. break;
  88. }
  89. range_hi = i;
  90. }
  91. if (range_lo == -1) {
  92. puts("SF: Calibration failed (low range)\n");
  93. return err;
  94. }
  95. /* Disable QSPI for subsequent initialization */
  96. cadence_qspi_apb_controller_disable(base);
  97. /* configure the final value for read data capture delay register */
  98. cadence_qspi_apb_readdata_capture(base, 1, (range_hi + range_lo) / 2);
  99. debug("SF: Read data capture delay calibrated to %i (%i - %i)\n",
  100. (range_hi + range_lo) / 2, range_lo, range_hi);
  101. /* just to ensure we do once only when speed or chip select change */
  102. priv->qspi_calibrated_hz = hz;
  103. priv->qspi_calibrated_cs = spi_chip_select(bus);
  104. return 0;
  105. }
  106. static int cadence_spi_set_speed(struct udevice *bus, uint hz)
  107. {
  108. struct cadence_spi_platdata *plat = bus->platdata;
  109. struct cadence_spi_priv *priv = dev_get_priv(bus);
  110. int err;
  111. if (hz > plat->max_hz)
  112. hz = plat->max_hz;
  113. /* Disable QSPI */
  114. cadence_qspi_apb_controller_disable(priv->regbase);
  115. /*
  116. * Calibration required for different current SCLK speed, requested
  117. * SCLK speed or chip select
  118. */
  119. if (priv->previous_hz != hz ||
  120. priv->qspi_calibrated_hz != hz ||
  121. priv->qspi_calibrated_cs != spi_chip_select(bus)) {
  122. err = spi_calibration(bus, hz);
  123. if (err)
  124. return err;
  125. /* prevent calibration run when same as previous request */
  126. priv->previous_hz = hz;
  127. }
  128. /* Enable QSPI */
  129. cadence_qspi_apb_controller_enable(priv->regbase);
  130. debug("%s: speed=%d\n", __func__, hz);
  131. return 0;
  132. }
  133. static int cadence_spi_probe(struct udevice *bus)
  134. {
  135. struct cadence_spi_platdata *plat = bus->platdata;
  136. struct cadence_spi_priv *priv = dev_get_priv(bus);
  137. struct clk clk;
  138. int ret;
  139. priv->regbase = plat->regbase;
  140. priv->ahbbase = plat->ahbbase;
  141. if (plat->ref_clk_hz == 0) {
  142. ret = clk_get_by_index(bus, 0, &clk);
  143. if (ret) {
  144. #ifdef CONFIG_CQSPI_REF_CLK
  145. plat->ref_clk_hz = CONFIG_CQSPI_REF_CLK;
  146. #else
  147. return ret;
  148. #endif
  149. } else {
  150. plat->ref_clk_hz = clk_get_rate(&clk);
  151. clk_free(&clk);
  152. if (IS_ERR_VALUE(plat->ref_clk_hz))
  153. return plat->ref_clk_hz;
  154. }
  155. }
  156. ret = reset_get_bulk(bus, &priv->resets);
  157. if (ret)
  158. dev_warn(bus, "Can't get reset: %d\n", ret);
  159. else
  160. reset_deassert_bulk(&priv->resets);
  161. if (!priv->qspi_is_init) {
  162. cadence_qspi_apb_controller_init(plat);
  163. priv->qspi_is_init = 1;
  164. }
  165. return 0;
  166. }
  167. static int cadence_spi_remove(struct udevice *dev)
  168. {
  169. struct cadence_spi_priv *priv = dev_get_priv(dev);
  170. return reset_release_bulk(&priv->resets);
  171. }
  172. static int cadence_spi_set_mode(struct udevice *bus, uint mode)
  173. {
  174. struct cadence_spi_platdata *plat = bus->platdata;
  175. struct cadence_spi_priv *priv = dev_get_priv(bus);
  176. /* Disable QSPI */
  177. cadence_qspi_apb_controller_disable(priv->regbase);
  178. /* Set SPI mode */
  179. cadence_qspi_apb_set_clk_mode(priv->regbase, mode);
  180. /* Enable Direct Access Controller */
  181. if (plat->use_dac_mode)
  182. cadence_qspi_apb_dac_mode_enable(priv->regbase);
  183. /* Enable QSPI */
  184. cadence_qspi_apb_controller_enable(priv->regbase);
  185. return 0;
  186. }
  187. static int cadence_spi_mem_exec_op(struct spi_slave *spi,
  188. const struct spi_mem_op *op)
  189. {
  190. struct udevice *bus = spi->dev->parent;
  191. struct cadence_spi_platdata *plat = bus->platdata;
  192. struct cadence_spi_priv *priv = dev_get_priv(bus);
  193. void *base = priv->regbase;
  194. int err = 0;
  195. u32 mode;
  196. /* Set Chip select */
  197. cadence_qspi_apb_chipselect(base, spi_chip_select(spi->dev),
  198. plat->is_decoded_cs);
  199. if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) {
  200. if (!op->addr.nbytes)
  201. mode = CQSPI_STIG_READ;
  202. else
  203. mode = CQSPI_READ;
  204. } else {
  205. if (!op->addr.nbytes || !op->data.buf.out)
  206. mode = CQSPI_STIG_WRITE;
  207. else
  208. mode = CQSPI_WRITE;
  209. }
  210. switch (mode) {
  211. case CQSPI_STIG_READ:
  212. err = cadence_qspi_apb_command_read(base, op);
  213. break;
  214. case CQSPI_STIG_WRITE:
  215. err = cadence_qspi_apb_command_write(base, op);
  216. break;
  217. case CQSPI_READ:
  218. err = cadence_qspi_apb_read_setup(plat, op);
  219. if (!err)
  220. err = cadence_qspi_apb_read_execute(plat, op);
  221. break;
  222. case CQSPI_WRITE:
  223. err = cadence_qspi_apb_write_setup(plat, op);
  224. if (!err)
  225. err = cadence_qspi_apb_write_execute(plat, op);
  226. break;
  227. default:
  228. err = -1;
  229. break;
  230. }
  231. return err;
  232. }
  233. static int cadence_spi_ofdata_to_platdata(struct udevice *bus)
  234. {
  235. struct cadence_spi_platdata *plat = bus->platdata;
  236. ofnode subnode;
  237. plat->regbase = (void *)devfdt_get_addr_index(bus, 0);
  238. plat->ahbbase = (void *)devfdt_get_addr_size_index(bus, 1,
  239. &plat->ahbsize);
  240. plat->is_decoded_cs = dev_read_bool(bus, "cdns,is-decoded-cs");
  241. plat->fifo_depth = dev_read_u32_default(bus, "cdns,fifo-depth", 128);
  242. plat->fifo_width = dev_read_u32_default(bus, "cdns,fifo-width", 4);
  243. plat->trigger_address = dev_read_u32_default(bus,
  244. "cdns,trigger-address",
  245. 0);
  246. /* Use DAC mode only when MMIO window is at least 8M wide */
  247. if (plat->ahbsize >= SZ_8M)
  248. plat->use_dac_mode = true;
  249. /* All other paramters are embedded in the child node */
  250. subnode = dev_read_first_subnode(bus);
  251. if (!ofnode_valid(subnode)) {
  252. printf("Error: subnode with SPI flash config missing!\n");
  253. return -ENODEV;
  254. }
  255. /* Use 500 KHz as a suitable default */
  256. plat->max_hz = ofnode_read_u32_default(subnode, "spi-max-frequency",
  257. 500000);
  258. /* Read other parameters from DT */
  259. plat->page_size = ofnode_read_u32_default(subnode, "page-size", 256);
  260. plat->block_size = ofnode_read_u32_default(subnode, "block-size", 16);
  261. plat->tshsl_ns = ofnode_read_u32_default(subnode, "cdns,tshsl-ns",
  262. 200);
  263. plat->tsd2d_ns = ofnode_read_u32_default(subnode, "cdns,tsd2d-ns",
  264. 255);
  265. plat->tchsh_ns = ofnode_read_u32_default(subnode, "cdns,tchsh-ns", 20);
  266. plat->tslch_ns = ofnode_read_u32_default(subnode, "cdns,tslch-ns", 20);
  267. debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n",
  268. __func__, plat->regbase, plat->ahbbase, plat->max_hz,
  269. plat->page_size);
  270. return 0;
  271. }
  272. static const struct spi_controller_mem_ops cadence_spi_mem_ops = {
  273. .exec_op = cadence_spi_mem_exec_op,
  274. };
  275. static const struct dm_spi_ops cadence_spi_ops = {
  276. .set_speed = cadence_spi_set_speed,
  277. .set_mode = cadence_spi_set_mode,
  278. .mem_ops = &cadence_spi_mem_ops,
  279. /*
  280. * cs_info is not needed, since we require all chip selects to be
  281. * in the device tree explicitly
  282. */
  283. };
  284. static const struct udevice_id cadence_spi_ids[] = {
  285. { .compatible = "cdns,qspi-nor" },
  286. { .compatible = "ti,am654-ospi" },
  287. { }
  288. };
  289. U_BOOT_DRIVER(cadence_spi) = {
  290. .name = "cadence_spi",
  291. .id = UCLASS_SPI,
  292. .of_match = cadence_spi_ids,
  293. .ops = &cadence_spi_ops,
  294. .ofdata_to_platdata = cadence_spi_ofdata_to_platdata,
  295. .platdata_auto_alloc_size = sizeof(struct cadence_spi_platdata),
  296. .priv_auto_alloc_size = sizeof(struct cadence_spi_priv),
  297. .probe = cadence_spi_probe,
  298. .remove = cadence_spi_remove,
  299. .flags = DM_FLAG_OS_PREPARE,
  300. };