bcm63xx_hsspi.c 11 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
  4. *
  5. * Derived from linux/drivers/spi/spi-bcm63xx-hsspi.c:
  6. * Copyright (C) 2000-2010 Broadcom Corporation
  7. * Copyright (C) 2012-2013 Jonas Gorski <jogo@openwrt.org>
  8. */
  9. #include <common.h>
  10. #include <clk.h>
  11. #include <dm.h>
  12. #include <log.h>
  13. #include <malloc.h>
  14. #include <spi.h>
  15. #include <reset.h>
  16. #include <wait_bit.h>
  17. #include <asm/io.h>
  18. #include <linux/bitops.h>
  19. #define HSSPI_PP 0
  20. #define SPI_MAX_SYNC_CLOCK 30000000
  21. /* SPI Control register */
  22. #define SPI_CTL_REG 0x000
  23. #define SPI_CTL_CS_POL_SHIFT 0
  24. #define SPI_CTL_CS_POL_MASK (0xff << SPI_CTL_CS_POL_SHIFT)
  25. #define SPI_CTL_CLK_GATE_SHIFT 16
  26. #define SPI_CTL_CLK_GATE_MASK (1 << SPI_CTL_CLK_GATE_SHIFT)
  27. #define SPI_CTL_CLK_POL_SHIFT 17
  28. #define SPI_CTL_CLK_POL_MASK (1 << SPI_CTL_CLK_POL_SHIFT)
  29. /* SPI Interrupts registers */
  30. #define SPI_IR_STAT_REG 0x008
  31. #define SPI_IR_ST_MASK_REG 0x00c
  32. #define SPI_IR_MASK_REG 0x010
  33. #define SPI_IR_CLEAR_ALL 0xff001f1f
  34. /* SPI Ping-Pong Command registers */
  35. #define SPI_CMD_REG (0x080 + (0x40 * (HSSPI_PP)) + 0x00)
  36. #define SPI_CMD_OP_SHIFT 0
  37. #define SPI_CMD_OP_START (0x1 << SPI_CMD_OP_SHIFT)
  38. #define SPI_CMD_PFL_SHIFT 8
  39. #define SPI_CMD_PFL_MASK (0x7 << SPI_CMD_PFL_SHIFT)
  40. #define SPI_CMD_SLAVE_SHIFT 12
  41. #define SPI_CMD_SLAVE_MASK (0x7 << SPI_CMD_SLAVE_SHIFT)
  42. /* SPI Ping-Pong Status registers */
  43. #define SPI_STAT_REG (0x080 + (0x40 * (HSSPI_PP)) + 0x04)
  44. #define SPI_STAT_SRCBUSY_SHIFT 1
  45. #define SPI_STAT_SRCBUSY_MASK (1 << SPI_STAT_SRCBUSY_SHIFT)
  46. /* SPI Profile Clock registers */
  47. #define SPI_PFL_CLK_REG(x) (0x100 + (0x20 * (x)) + 0x00)
  48. #define SPI_PFL_CLK_FREQ_SHIFT 0
  49. #define SPI_PFL_CLK_FREQ_MASK (0x3fff << SPI_PFL_CLK_FREQ_SHIFT)
  50. #define SPI_PFL_CLK_RSTLOOP_SHIFT 15
  51. #define SPI_PFL_CLK_RSTLOOP_MASK (1 << SPI_PFL_CLK_RSTLOOP_SHIFT)
  52. /* SPI Profile Signal registers */
  53. #define SPI_PFL_SIG_REG(x) (0x100 + (0x20 * (x)) + 0x04)
  54. #define SPI_PFL_SIG_LATCHRIS_SHIFT 12
  55. #define SPI_PFL_SIG_LATCHRIS_MASK (1 << SPI_PFL_SIG_LATCHRIS_SHIFT)
  56. #define SPI_PFL_SIG_LAUNCHRIS_SHIFT 13
  57. #define SPI_PFL_SIG_LAUNCHRIS_MASK (1 << SPI_PFL_SIG_LAUNCHRIS_SHIFT)
  58. #define SPI_PFL_SIG_ASYNCIN_SHIFT 16
  59. #define SPI_PFL_SIG_ASYNCIN_MASK (1 << SPI_PFL_SIG_ASYNCIN_SHIFT)
  60. /* SPI Profile Mode registers */
  61. #define SPI_PFL_MODE_REG(x) (0x100 + (0x20 * (x)) + 0x08)
  62. #define SPI_PFL_MODE_FILL_SHIFT 0
  63. #define SPI_PFL_MODE_FILL_MASK (0xff << SPI_PFL_MODE_FILL_SHIFT)
  64. #define SPI_PFL_MODE_MDRDSZ_SHIFT 16
  65. #define SPI_PFL_MODE_MDRDSZ_MASK (1 << SPI_PFL_MODE_MDRDSZ_SHIFT)
  66. #define SPI_PFL_MODE_MDWRSZ_SHIFT 18
  67. #define SPI_PFL_MODE_MDWRSZ_MASK (1 << SPI_PFL_MODE_MDWRSZ_SHIFT)
  68. #define SPI_PFL_MODE_3WIRE_SHIFT 20
  69. #define SPI_PFL_MODE_3WIRE_MASK (1 << SPI_PFL_MODE_3WIRE_SHIFT)
  70. /* SPI Ping-Pong FIFO registers */
  71. #define HSSPI_FIFO_SIZE 0x200
  72. #define HSSPI_FIFO_BASE (0x200 + \
  73. (HSSPI_FIFO_SIZE * HSSPI_PP))
  74. /* SPI Ping-Pong FIFO OP register */
  75. #define HSSPI_FIFO_OP_SIZE 0x2
  76. #define HSSPI_FIFO_OP_REG (HSSPI_FIFO_BASE + 0x00)
  77. #define HSSPI_FIFO_OP_BYTES_SHIFT 0
  78. #define HSSPI_FIFO_OP_BYTES_MASK (0x3ff << HSSPI_FIFO_OP_BYTES_SHIFT)
  79. #define HSSPI_FIFO_OP_MBIT_SHIFT 11
  80. #define HSSPI_FIFO_OP_MBIT_MASK (1 << HSSPI_FIFO_OP_MBIT_SHIFT)
  81. #define HSSPI_FIFO_OP_CODE_SHIFT 13
  82. #define HSSPI_FIFO_OP_READ_WRITE (1 << HSSPI_FIFO_OP_CODE_SHIFT)
  83. #define HSSPI_FIFO_OP_CODE_W (2 << HSSPI_FIFO_OP_CODE_SHIFT)
  84. #define HSSPI_FIFO_OP_CODE_R (3 << HSSPI_FIFO_OP_CODE_SHIFT)
  85. struct bcm63xx_hsspi_priv {
  86. void __iomem *regs;
  87. ulong clk_rate;
  88. uint8_t num_cs;
  89. uint8_t cs_pols;
  90. uint speed;
  91. };
  92. static int bcm63xx_hsspi_cs_info(struct udevice *bus, uint cs,
  93. struct spi_cs_info *info)
  94. {
  95. struct bcm63xx_hsspi_priv *priv = dev_get_priv(bus);
  96. if (cs >= priv->num_cs) {
  97. printf("no cs %u\n", cs);
  98. return -EINVAL;
  99. }
  100. return 0;
  101. }
  102. static int bcm63xx_hsspi_set_mode(struct udevice *bus, uint mode)
  103. {
  104. struct bcm63xx_hsspi_priv *priv = dev_get_priv(bus);
  105. /* clock polarity */
  106. if (mode & SPI_CPOL)
  107. setbits_32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_POL_MASK);
  108. else
  109. clrbits_32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_POL_MASK);
  110. return 0;
  111. }
  112. static int bcm63xx_hsspi_set_speed(struct udevice *bus, uint speed)
  113. {
  114. struct bcm63xx_hsspi_priv *priv = dev_get_priv(bus);
  115. priv->speed = speed;
  116. return 0;
  117. }
  118. static void bcm63xx_hsspi_activate_cs(struct bcm63xx_hsspi_priv *priv,
  119. struct dm_spi_slave_platdata *plat)
  120. {
  121. uint32_t clr, set;
  122. /* profile clock */
  123. set = DIV_ROUND_UP(priv->clk_rate, priv->speed);
  124. set = DIV_ROUND_UP(2048, set);
  125. set &= SPI_PFL_CLK_FREQ_MASK;
  126. set |= SPI_PFL_CLK_RSTLOOP_MASK;
  127. writel(set, priv->regs + SPI_PFL_CLK_REG(plat->cs));
  128. /* profile signal */
  129. set = 0;
  130. clr = SPI_PFL_SIG_LAUNCHRIS_MASK |
  131. SPI_PFL_SIG_LATCHRIS_MASK |
  132. SPI_PFL_SIG_ASYNCIN_MASK;
  133. /* latch/launch config */
  134. if (plat->mode & SPI_CPHA)
  135. set |= SPI_PFL_SIG_LAUNCHRIS_MASK;
  136. else
  137. set |= SPI_PFL_SIG_LATCHRIS_MASK;
  138. /* async clk */
  139. if (priv->speed > SPI_MAX_SYNC_CLOCK)
  140. set |= SPI_PFL_SIG_ASYNCIN_MASK;
  141. clrsetbits_32(priv->regs + SPI_PFL_SIG_REG(plat->cs), clr, set);
  142. /* global control */
  143. set = 0;
  144. clr = 0;
  145. /* invert cs polarity */
  146. if (priv->cs_pols & BIT(plat->cs))
  147. clr |= BIT(plat->cs);
  148. else
  149. set |= BIT(plat->cs);
  150. /* invert dummy cs polarity */
  151. if (priv->cs_pols & BIT(!plat->cs))
  152. clr |= BIT(!plat->cs);
  153. else
  154. set |= BIT(!plat->cs);
  155. clrsetbits_32(priv->regs + SPI_CTL_REG, clr, set);
  156. }
  157. static void bcm63xx_hsspi_deactivate_cs(struct bcm63xx_hsspi_priv *priv)
  158. {
  159. /* restore cs polarities */
  160. clrsetbits_32(priv->regs + SPI_CTL_REG, SPI_CTL_CS_POL_MASK,
  161. priv->cs_pols);
  162. }
  163. /*
  164. * BCM63xx HSSPI driver doesn't allow keeping CS active between transfers
  165. * because they are controlled by HW.
  166. * However, it provides a mechanism to prepend write transfers prior to read
  167. * transfers (with a maximum prepend of 15 bytes), which is usually enough for
  168. * SPI-connected flashes since reading requires prepending a write transfer of
  169. * 5 bytes. On the other hand it also provides a way to invert each CS
  170. * polarity, not only between transfers like the older BCM63xx SPI driver, but
  171. * also the rest of the time.
  172. *
  173. * Instead of using the prepend mechanism, this implementation inverts the
  174. * polarity of both the desired CS and another dummy CS when the bus is
  175. * claimed. This way, the dummy CS is restored to its inactive value when
  176. * transfers are issued and the desired CS is preserved in its active value
  177. * all the time. This hack is also used in the upstream linux driver and
  178. * allows keeping CS active between trasnfers even if the HW doesn't give
  179. * this possibility.
  180. */
  181. static int bcm63xx_hsspi_xfer(struct udevice *dev, unsigned int bitlen,
  182. const void *dout, void *din, unsigned long flags)
  183. {
  184. struct bcm63xx_hsspi_priv *priv = dev_get_priv(dev->parent);
  185. struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev);
  186. size_t data_bytes = bitlen / 8;
  187. size_t step_size = HSSPI_FIFO_SIZE;
  188. uint16_t opcode = 0;
  189. uint32_t val;
  190. const uint8_t *tx = dout;
  191. uint8_t *rx = din;
  192. if (flags & SPI_XFER_BEGIN)
  193. bcm63xx_hsspi_activate_cs(priv, plat);
  194. /* fifo operation */
  195. if (tx && rx)
  196. opcode = HSSPI_FIFO_OP_READ_WRITE;
  197. else if (rx)
  198. opcode = HSSPI_FIFO_OP_CODE_R;
  199. else if (tx)
  200. opcode = HSSPI_FIFO_OP_CODE_W;
  201. if (opcode != HSSPI_FIFO_OP_CODE_R)
  202. step_size -= HSSPI_FIFO_OP_SIZE;
  203. /* dual mode */
  204. if ((opcode == HSSPI_FIFO_OP_CODE_R && plat->mode == SPI_RX_DUAL) ||
  205. (opcode == HSSPI_FIFO_OP_CODE_W && plat->mode == SPI_TX_DUAL))
  206. opcode |= HSSPI_FIFO_OP_MBIT_MASK;
  207. /* profile mode */
  208. val = SPI_PFL_MODE_FILL_MASK |
  209. SPI_PFL_MODE_MDRDSZ_MASK |
  210. SPI_PFL_MODE_MDWRSZ_MASK;
  211. if (plat->mode & SPI_3WIRE)
  212. val |= SPI_PFL_MODE_3WIRE_MASK;
  213. writel(val, priv->regs + SPI_PFL_MODE_REG(plat->cs));
  214. /* transfer loop */
  215. while (data_bytes > 0) {
  216. size_t curr_step = min(step_size, data_bytes);
  217. int ret;
  218. /* copy tx data */
  219. if (tx) {
  220. memcpy_toio(priv->regs + HSSPI_FIFO_BASE +
  221. HSSPI_FIFO_OP_SIZE, tx, curr_step);
  222. tx += curr_step;
  223. }
  224. /* set fifo operation */
  225. writew(cpu_to_be16(opcode | (curr_step & HSSPI_FIFO_OP_BYTES_MASK)),
  226. priv->regs + HSSPI_FIFO_OP_REG);
  227. /* issue the transfer */
  228. val = SPI_CMD_OP_START;
  229. val |= (plat->cs << SPI_CMD_PFL_SHIFT) &
  230. SPI_CMD_PFL_MASK;
  231. val |= (!plat->cs << SPI_CMD_SLAVE_SHIFT) &
  232. SPI_CMD_SLAVE_MASK;
  233. writel(val, priv->regs + SPI_CMD_REG);
  234. /* wait for completion */
  235. ret = wait_for_bit_32(priv->regs + SPI_STAT_REG,
  236. SPI_STAT_SRCBUSY_MASK, false,
  237. 1000, false);
  238. if (ret) {
  239. printf("interrupt timeout\n");
  240. return ret;
  241. }
  242. /* copy rx data */
  243. if (rx) {
  244. memcpy_fromio(rx, priv->regs + HSSPI_FIFO_BASE,
  245. curr_step);
  246. rx += curr_step;
  247. }
  248. data_bytes -= curr_step;
  249. }
  250. if (flags & SPI_XFER_END)
  251. bcm63xx_hsspi_deactivate_cs(priv);
  252. return 0;
  253. }
  254. static const struct dm_spi_ops bcm63xx_hsspi_ops = {
  255. .cs_info = bcm63xx_hsspi_cs_info,
  256. .set_mode = bcm63xx_hsspi_set_mode,
  257. .set_speed = bcm63xx_hsspi_set_speed,
  258. .xfer = bcm63xx_hsspi_xfer,
  259. };
  260. static const struct udevice_id bcm63xx_hsspi_ids[] = {
  261. { .compatible = "brcm,bcm6328-hsspi", },
  262. { /* sentinel */ }
  263. };
  264. static int bcm63xx_hsspi_child_pre_probe(struct udevice *dev)
  265. {
  266. struct bcm63xx_hsspi_priv *priv = dev_get_priv(dev->parent);
  267. struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev);
  268. /* check cs */
  269. if (plat->cs >= priv->num_cs) {
  270. printf("no cs %u\n", plat->cs);
  271. return -ENODEV;
  272. }
  273. /* cs polarity */
  274. if (plat->mode & SPI_CS_HIGH)
  275. priv->cs_pols |= BIT(plat->cs);
  276. else
  277. priv->cs_pols &= ~BIT(plat->cs);
  278. return 0;
  279. }
  280. static int bcm63xx_hsspi_probe(struct udevice *dev)
  281. {
  282. struct bcm63xx_hsspi_priv *priv = dev_get_priv(dev);
  283. struct reset_ctl rst_ctl;
  284. struct clk clk;
  285. int ret;
  286. priv->regs = dev_remap_addr(dev);
  287. if (!priv->regs)
  288. return -EINVAL;
  289. priv->num_cs = dev_read_u32_default(dev, "num-cs", 8);
  290. /* enable clock */
  291. ret = clk_get_by_name(dev, "hsspi", &clk);
  292. if (ret < 0)
  293. return ret;
  294. ret = clk_enable(&clk);
  295. if (ret < 0 && ret != -ENOSYS)
  296. return ret;
  297. ret = clk_free(&clk);
  298. if (ret < 0 && ret != -ENOSYS)
  299. return ret;
  300. /* get clock rate */
  301. ret = clk_get_by_name(dev, "pll", &clk);
  302. if (ret < 0 && ret != -ENOSYS)
  303. return ret;
  304. priv->clk_rate = clk_get_rate(&clk);
  305. ret = clk_free(&clk);
  306. if (ret < 0 && ret != -ENOSYS)
  307. return ret;
  308. /* perform reset */
  309. ret = reset_get_by_index(dev, 0, &rst_ctl);
  310. if (ret >= 0) {
  311. ret = reset_deassert(&rst_ctl);
  312. if (ret < 0)
  313. return ret;
  314. }
  315. ret = reset_free(&rst_ctl);
  316. if (ret < 0)
  317. return ret;
  318. /* initialize hardware */
  319. writel(0, priv->regs + SPI_IR_MASK_REG);
  320. /* clear pending interrupts */
  321. writel(SPI_IR_CLEAR_ALL, priv->regs + SPI_IR_STAT_REG);
  322. /* enable clk gate */
  323. setbits_32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_GATE_MASK);
  324. /* read default cs polarities */
  325. priv->cs_pols = readl(priv->regs + SPI_CTL_REG) &
  326. SPI_CTL_CS_POL_MASK;
  327. return 0;
  328. }
  329. U_BOOT_DRIVER(bcm63xx_hsspi) = {
  330. .name = "bcm63xx_hsspi",
  331. .id = UCLASS_SPI,
  332. .of_match = bcm63xx_hsspi_ids,
  333. .ops = &bcm63xx_hsspi_ops,
  334. .priv_auto_alloc_size = sizeof(struct bcm63xx_hsspi_priv),
  335. .child_pre_probe = bcm63xx_hsspi_child_pre_probe,
  336. .probe = bcm63xx_hsspi_probe,
  337. };