wm8994.c 21 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2012 Samsung Electronics
  4. * R. Chandrasekar <rcsekar@samsung.com>
  5. */
  6. #include <common.h>
  7. #include <audio_codec.h>
  8. #include <dm.h>
  9. #include <div64.h>
  10. #include <fdtdec.h>
  11. #include <i2c.h>
  12. #include <i2s.h>
  13. #include <log.h>
  14. #include <sound.h>
  15. #include <asm/gpio.h>
  16. #include <asm/io.h>
  17. #include <asm/arch/clk.h>
  18. #include <asm/arch/cpu.h>
  19. #include <asm/arch/sound.h>
  20. #include "wm8994.h"
  21. #include "wm8994_registers.h"
  22. /* defines for wm8994 system clock selection */
  23. #define SEL_MCLK1 0x00
  24. #define SEL_MCLK2 0x08
  25. #define SEL_FLL1 0x10
  26. #define SEL_FLL2 0x18
  27. /* fll config to configure fll */
  28. struct wm8994_fll_config {
  29. int src; /* Source */
  30. int in; /* Input frequency in Hz */
  31. int out; /* output frequency in Hz */
  32. };
  33. /* codec private data */
  34. struct wm8994_priv {
  35. enum wm8994_type type; /* codec type of wolfson */
  36. int revision; /* Revision */
  37. int sysclk[WM8994_MAX_AIF]; /* System clock frequency in Hz */
  38. int mclk[WM8994_MAX_AIF]; /* master clock frequency in Hz */
  39. int aifclk[WM8994_MAX_AIF]; /* audio interface clock in Hz */
  40. struct wm8994_fll_config fll[2]; /* fll config to configure fll */
  41. struct udevice *dev;
  42. };
  43. /* wm 8994 supported sampling rate values */
  44. static unsigned int src_rate[] = {
  45. 8000, 11025, 12000, 16000, 22050, 24000,
  46. 32000, 44100, 48000, 88200, 96000
  47. };
  48. /* op clock divisions */
  49. static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
  50. /* lr clock frame size ratio */
  51. static int fs_ratios[] = {
  52. 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
  53. };
  54. /* bit clock divisors */
  55. static int bclk_divs[] = {
  56. 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
  57. 640, 880, 960, 1280, 1760, 1920
  58. };
  59. /*
  60. * Writes value to a device register through i2c
  61. *
  62. * @param priv Private data for driver
  63. * @param reg reg number to be write
  64. * @param data data to be writen to the above registor
  65. *
  66. * @return int value 1 for change, 0 for no change or negative error code.
  67. */
  68. static int wm8994_i2c_write(struct wm8994_priv *priv, unsigned int reg,
  69. unsigned short data)
  70. {
  71. unsigned char val[2];
  72. val[0] = (unsigned char)((data >> 8) & 0xff);
  73. val[1] = (unsigned char)(data & 0xff);
  74. debug("Write Addr : 0x%04X, Data : 0x%04X\n", reg, data);
  75. return dm_i2c_write(priv->dev, reg, val, 2);
  76. }
  77. /*
  78. * Read a value from a device register through i2c
  79. *
  80. * @param priv Private data for driver
  81. * @param reg reg number to be read
  82. * @param data address of read data to be stored
  83. *
  84. * @return int value 0 for success, -1 in case of error.
  85. */
  86. static unsigned int wm8994_i2c_read(struct wm8994_priv *priv, unsigned int reg,
  87. unsigned short *data)
  88. {
  89. unsigned char val[2];
  90. int ret;
  91. ret = dm_i2c_read(priv->dev, reg, val, 1);
  92. if (ret != 0) {
  93. debug("%s: Error while reading register %#04x\n",
  94. __func__, reg);
  95. return -1;
  96. }
  97. *data = val[0];
  98. *data <<= 8;
  99. *data |= val[1];
  100. return 0;
  101. }
  102. /*
  103. * update device register bits through i2c
  104. *
  105. * @param priv Private data for driver
  106. * @param reg codec register
  107. * @param mask register mask
  108. * @param value new value
  109. *
  110. * @return int value 1 if change in the register value,
  111. * 0 for no change or negative error code.
  112. */
  113. static int wm8994_bic_or(struct wm8994_priv *priv, unsigned int reg,
  114. unsigned short mask, unsigned short value)
  115. {
  116. int change , ret = 0;
  117. unsigned short old, new;
  118. if (wm8994_i2c_read(priv, reg, &old) != 0)
  119. return -1;
  120. new = (old & ~mask) | (value & mask);
  121. change = (old != new) ? 1 : 0;
  122. if (change)
  123. ret = wm8994_i2c_write(priv, reg, new);
  124. if (ret < 0)
  125. return ret;
  126. return change;
  127. }
  128. /*
  129. * Sets i2s set format
  130. *
  131. * @param priv wm8994 information
  132. * @param aif_id Interface ID
  133. * @param fmt i2S format
  134. *
  135. * @return -1 for error and 0 Success.
  136. */
  137. static int wm8994_set_fmt(struct wm8994_priv *priv, int aif_id, uint fmt)
  138. {
  139. int ms_reg;
  140. int aif_reg;
  141. int ms = 0;
  142. int aif = 0;
  143. int aif_clk = 0;
  144. int error = 0;
  145. switch (aif_id) {
  146. case 1:
  147. ms_reg = WM8994_AIF1_MASTER_SLAVE;
  148. aif_reg = WM8994_AIF1_CONTROL_1;
  149. aif_clk = WM8994_AIF1_CLOCKING_1;
  150. break;
  151. case 2:
  152. ms_reg = WM8994_AIF2_MASTER_SLAVE;
  153. aif_reg = WM8994_AIF2_CONTROL_1;
  154. aif_clk = WM8994_AIF2_CLOCKING_1;
  155. break;
  156. default:
  157. debug("%s: Invalid audio interface selection\n", __func__);
  158. return -1;
  159. }
  160. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  161. case SND_SOC_DAIFMT_CBS_CFS:
  162. break;
  163. case SND_SOC_DAIFMT_CBM_CFM:
  164. ms = WM8994_AIF1_MSTR;
  165. break;
  166. default:
  167. debug("%s: Invalid i2s master selection\n", __func__);
  168. return -1;
  169. }
  170. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  171. case SND_SOC_DAIFMT_DSP_B:
  172. aif |= WM8994_AIF1_LRCLK_INV;
  173. case SND_SOC_DAIFMT_DSP_A:
  174. aif |= 0x18;
  175. break;
  176. case SND_SOC_DAIFMT_I2S:
  177. aif |= 0x10;
  178. break;
  179. case SND_SOC_DAIFMT_RIGHT_J:
  180. break;
  181. case SND_SOC_DAIFMT_LEFT_J:
  182. aif |= 0x8;
  183. break;
  184. default:
  185. debug("%s: Invalid i2s format selection\n", __func__);
  186. return -1;
  187. }
  188. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  189. case SND_SOC_DAIFMT_DSP_A:
  190. case SND_SOC_DAIFMT_DSP_B:
  191. /* frame inversion not valid for DSP modes */
  192. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  193. case SND_SOC_DAIFMT_NB_NF:
  194. break;
  195. case SND_SOC_DAIFMT_IB_NF:
  196. aif |= WM8994_AIF1_BCLK_INV;
  197. break;
  198. default:
  199. debug("%s: Invalid i2s frame inverse selection\n",
  200. __func__);
  201. return -1;
  202. }
  203. break;
  204. case SND_SOC_DAIFMT_I2S:
  205. case SND_SOC_DAIFMT_RIGHT_J:
  206. case SND_SOC_DAIFMT_LEFT_J:
  207. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  208. case SND_SOC_DAIFMT_NB_NF:
  209. break;
  210. case SND_SOC_DAIFMT_IB_IF:
  211. aif |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
  212. break;
  213. case SND_SOC_DAIFMT_IB_NF:
  214. aif |= WM8994_AIF1_BCLK_INV;
  215. break;
  216. case SND_SOC_DAIFMT_NB_IF:
  217. aif |= WM8994_AIF1_LRCLK_INV;
  218. break;
  219. default:
  220. debug("%s: Invalid i2s clock polarity selection\n",
  221. __func__);
  222. return -1;
  223. }
  224. break;
  225. default:
  226. debug("%s: Invalid i2s format selection\n", __func__);
  227. return -1;
  228. }
  229. error = wm8994_bic_or(priv, aif_reg, WM8994_AIF1_BCLK_INV |
  230. WM8994_AIF1_LRCLK_INV_MASK |
  231. WM8994_AIF1_FMT_MASK, aif);
  232. error |= wm8994_bic_or(priv, ms_reg, WM8994_AIF1_MSTR_MASK, ms);
  233. error |= wm8994_bic_or(priv, aif_clk, WM8994_AIF1CLK_ENA_MASK,
  234. WM8994_AIF1CLK_ENA);
  235. if (error < 0) {
  236. debug("%s: codec register access error\n", __func__);
  237. return -1;
  238. }
  239. return 0;
  240. }
  241. /*
  242. * Sets hw params FOR WM8994
  243. *
  244. * @param priv wm8994 information pointer
  245. * @param aif_id Audio interface ID
  246. * @param sampling_rate Sampling rate
  247. * @param bits_per_sample Bits per sample
  248. * @param Channels Channels in the given audio input
  249. *
  250. * @return -1 for error and 0 Success.
  251. */
  252. static int wm8994_hw_params(struct wm8994_priv *priv, int aif_id,
  253. uint sampling_rate, uint bits_per_sample,
  254. uint channels)
  255. {
  256. int aif1_reg;
  257. int aif2_reg;
  258. int bclk_reg;
  259. int bclk = 0;
  260. int rate_reg;
  261. int aif1 = 0;
  262. int aif2 = 0;
  263. int rate_val = 0;
  264. int id = aif_id - 1;
  265. int i, cur_val, best_val, bclk_rate, best;
  266. unsigned short reg_data;
  267. int ret = 0;
  268. switch (aif_id) {
  269. case 1:
  270. aif1_reg = WM8994_AIF1_CONTROL_1;
  271. aif2_reg = WM8994_AIF1_CONTROL_2;
  272. bclk_reg = WM8994_AIF1_BCLK;
  273. rate_reg = WM8994_AIF1_RATE;
  274. break;
  275. case 2:
  276. aif1_reg = WM8994_AIF2_CONTROL_1;
  277. aif2_reg = WM8994_AIF2_CONTROL_2;
  278. bclk_reg = WM8994_AIF2_BCLK;
  279. rate_reg = WM8994_AIF2_RATE;
  280. break;
  281. default:
  282. return -1;
  283. }
  284. bclk_rate = sampling_rate * 32;
  285. switch (bits_per_sample) {
  286. case 16:
  287. bclk_rate *= 16;
  288. break;
  289. case 20:
  290. bclk_rate *= 20;
  291. aif1 |= 0x20;
  292. break;
  293. case 24:
  294. bclk_rate *= 24;
  295. aif1 |= 0x40;
  296. break;
  297. case 32:
  298. bclk_rate *= 32;
  299. aif1 |= 0x60;
  300. break;
  301. default:
  302. return -1;
  303. }
  304. /* Try to find an appropriate sample rate; look for an exact match. */
  305. for (i = 0; i < ARRAY_SIZE(src_rate); i++)
  306. if (src_rate[i] == sampling_rate)
  307. break;
  308. if (i == ARRAY_SIZE(src_rate)) {
  309. debug("%s: Could not get the best matching samplingrate\n",
  310. __func__);
  311. return -1;
  312. }
  313. rate_val |= i << WM8994_AIF1_SR_SHIFT;
  314. /* AIFCLK/fs ratio; look for a close match in either direction */
  315. best = 0;
  316. best_val = abs((fs_ratios[0] * sampling_rate) - priv->aifclk[id]);
  317. for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
  318. cur_val = abs(fs_ratios[i] * sampling_rate - priv->aifclk[id]);
  319. if (cur_val >= best_val)
  320. continue;
  321. best = i;
  322. best_val = cur_val;
  323. }
  324. rate_val |= best;
  325. /*
  326. * We may not get quite the right frequency if using
  327. * approximate clocks so look for the closest match that is
  328. * higher than the target (we need to ensure that there enough
  329. * BCLKs to clock out the samples).
  330. */
  331. best = 0;
  332. for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
  333. cur_val = (priv->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
  334. if (cur_val < 0) /* BCLK table is sorted */
  335. break;
  336. best = i;
  337. }
  338. if (i == ARRAY_SIZE(bclk_divs)) {
  339. debug("%s: Could not get the best matching bclk division\n",
  340. __func__);
  341. return -1;
  342. }
  343. bclk_rate = priv->aifclk[id] * 10 / bclk_divs[best];
  344. bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
  345. if (wm8994_i2c_read(priv, aif1_reg, &reg_data) != 0) {
  346. debug("%s: AIF1 register read Failed\n", __func__);
  347. return -1;
  348. }
  349. if ((channels == 1) && ((reg_data & 0x18) == 0x18))
  350. aif2 |= WM8994_AIF1_MONO;
  351. if (priv->aifclk[id] == 0) {
  352. debug("%s:Audio interface clock not set\n", __func__);
  353. return -1;
  354. }
  355. ret = wm8994_bic_or(priv, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
  356. ret |= wm8994_bic_or(priv, aif2_reg, WM8994_AIF1_MONO, aif2);
  357. ret |= wm8994_bic_or(priv, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK,
  358. bclk);
  359. ret |= wm8994_bic_or(priv, rate_reg, WM8994_AIF1_SR_MASK |
  360. WM8994_AIF1CLK_RATE_MASK, rate_val);
  361. debug("rate vale = %x , bclk val= %x\n", rate_val, bclk);
  362. if (ret < 0) {
  363. debug("%s: codec register access error\n", __func__);
  364. return -1;
  365. }
  366. return 0;
  367. }
  368. /*
  369. * Configures Audio interface Clock
  370. *
  371. * @param priv wm8994 information pointer
  372. * @param aif Audio Interface ID
  373. *
  374. * @return -1 for error and 0 Success.
  375. */
  376. static int configure_aif_clock(struct wm8994_priv *priv, int aif)
  377. {
  378. int rate;
  379. int reg1 = 0;
  380. int offset;
  381. int ret;
  382. /* AIF(1/0) register adress offset calculated */
  383. if (aif-1)
  384. offset = 4;
  385. else
  386. offset = 0;
  387. switch (priv->sysclk[aif - 1]) {
  388. case WM8994_SYSCLK_MCLK1:
  389. reg1 |= SEL_MCLK1;
  390. rate = priv->mclk[0];
  391. break;
  392. case WM8994_SYSCLK_MCLK2:
  393. reg1 |= SEL_MCLK2;
  394. rate = priv->mclk[1];
  395. break;
  396. case WM8994_SYSCLK_FLL1:
  397. reg1 |= SEL_FLL1;
  398. rate = priv->fll[0].out;
  399. break;
  400. case WM8994_SYSCLK_FLL2:
  401. reg1 |= SEL_FLL2;
  402. rate = priv->fll[1].out;
  403. break;
  404. default:
  405. debug("%s: Invalid input clock selection [%d]\n",
  406. __func__, priv->sysclk[aif - 1]);
  407. return -1;
  408. }
  409. /* if input clock frequenct is more than 135Mhz then divide */
  410. if (rate >= WM8994_MAX_INPUT_CLK_FREQ) {
  411. rate /= 2;
  412. reg1 |= WM8994_AIF1CLK_DIV;
  413. }
  414. priv->aifclk[aif - 1] = rate;
  415. ret = wm8994_bic_or(priv, WM8994_AIF1_CLOCKING_1 + offset,
  416. WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
  417. reg1);
  418. if (aif == WM8994_AIF1)
  419. ret |= wm8994_bic_or(priv, WM8994_CLOCKING_1,
  420. WM8994_AIF1DSPCLK_ENA_MASK | WM8994_SYSDSPCLK_ENA_MASK,
  421. WM8994_AIF1DSPCLK_ENA | WM8994_SYSDSPCLK_ENA);
  422. else if (aif == WM8994_AIF2)
  423. ret |= wm8994_bic_or(priv, WM8994_CLOCKING_1,
  424. WM8994_SYSCLK_SRC | WM8994_AIF2DSPCLK_ENA_MASK |
  425. WM8994_SYSDSPCLK_ENA_MASK, WM8994_SYSCLK_SRC |
  426. WM8994_AIF2DSPCLK_ENA | WM8994_SYSDSPCLK_ENA);
  427. if (ret < 0) {
  428. debug("%s: codec register access error\n", __func__);
  429. return -1;
  430. }
  431. return 0;
  432. }
  433. /*
  434. * Configures Audio interface for the given frequency
  435. *
  436. * @param priv wm8994 information
  437. * @param aif_id Audio Interface
  438. * @param clk_id Input Clock ID
  439. * @param freq Sampling frequency in Hz
  440. *
  441. * @return -1 for error and 0 success.
  442. */
  443. static int wm8994_set_sysclk(struct wm8994_priv *priv, int aif_id, int clk_id,
  444. unsigned int freq)
  445. {
  446. int i;
  447. int ret = 0;
  448. priv->sysclk[aif_id - 1] = clk_id;
  449. switch (clk_id) {
  450. case WM8994_SYSCLK_MCLK1:
  451. priv->mclk[0] = freq;
  452. if (aif_id == 2) {
  453. ret = wm8994_bic_or(priv, WM8994_AIF1_CLOCKING_2,
  454. WM8994_AIF2DAC_DIV_MASK, 0);
  455. }
  456. break;
  457. case WM8994_SYSCLK_MCLK2:
  458. /* TODO: Set GPIO AF */
  459. priv->mclk[1] = freq;
  460. break;
  461. case WM8994_SYSCLK_FLL1:
  462. case WM8994_SYSCLK_FLL2:
  463. break;
  464. case WM8994_SYSCLK_OPCLK:
  465. /*
  466. * Special case - a division (times 10) is given and
  467. * no effect on main clocking.
  468. */
  469. if (freq) {
  470. for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
  471. if (opclk_divs[i] == freq)
  472. break;
  473. if (i == ARRAY_SIZE(opclk_divs)) {
  474. debug("%s frequency divisor not found\n",
  475. __func__);
  476. return -1;
  477. }
  478. ret = wm8994_bic_or(priv, WM8994_CLOCKING_2,
  479. WM8994_OPCLK_DIV_MASK, i);
  480. ret |= wm8994_bic_or(priv, WM8994_POWER_MANAGEMENT_2,
  481. WM8994_OPCLK_ENA,
  482. WM8994_OPCLK_ENA);
  483. } else {
  484. ret |= wm8994_bic_or(priv, WM8994_POWER_MANAGEMENT_2,
  485. WM8994_OPCLK_ENA, 0);
  486. }
  487. default:
  488. debug("%s Invalid input clock selection [%d]\n",
  489. __func__, clk_id);
  490. return -1;
  491. }
  492. ret |= configure_aif_clock(priv, aif_id);
  493. if (ret < 0) {
  494. debug("%s: codec register access error\n", __func__);
  495. return -1;
  496. }
  497. return 0;
  498. }
  499. /*
  500. * Initializes Volume for AIF2 to HP path
  501. *
  502. * @param priv wm8994 information
  503. * @returns -1 for error and 0 Success.
  504. *
  505. */
  506. static int wm8994_init_volume_aif2_dac1(struct wm8994_priv *priv)
  507. {
  508. int ret;
  509. /* Unmute AIF2DAC */
  510. ret = wm8994_bic_or(priv, WM8994_AIF2_DAC_FILTERS_1,
  511. WM8994_AIF2DAC_MUTE_MASK, 0);
  512. ret |= wm8994_bic_or(priv, WM8994_AIF2_DAC_LEFT_VOLUME,
  513. WM8994_AIF2DAC_VU_MASK | WM8994_AIF2DACL_VOL_MASK,
  514. WM8994_AIF2DAC_VU | 0xff);
  515. ret |= wm8994_bic_or(priv, WM8994_AIF2_DAC_RIGHT_VOLUME,
  516. WM8994_AIF2DAC_VU_MASK | WM8994_AIF2DACR_VOL_MASK,
  517. WM8994_AIF2DAC_VU | 0xff);
  518. ret |= wm8994_bic_or(priv, WM8994_DAC1_LEFT_VOLUME,
  519. WM8994_DAC1_VU_MASK | WM8994_DAC1L_VOL_MASK |
  520. WM8994_DAC1L_MUTE_MASK, WM8994_DAC1_VU | 0xc0);
  521. ret |= wm8994_bic_or(priv, WM8994_DAC1_RIGHT_VOLUME,
  522. WM8994_DAC1_VU_MASK | WM8994_DAC1R_VOL_MASK |
  523. WM8994_DAC1R_MUTE_MASK, WM8994_DAC1_VU | 0xc0);
  524. /* Head Phone Volume */
  525. ret |= wm8994_i2c_write(priv, WM8994_LEFT_OUTPUT_VOLUME, 0x12D);
  526. ret |= wm8994_i2c_write(priv, WM8994_RIGHT_OUTPUT_VOLUME, 0x12D);
  527. if (ret < 0) {
  528. debug("%s: codec register access error\n", __func__);
  529. return -1;
  530. }
  531. return 0;
  532. }
  533. /*
  534. * Initializes Volume for AIF1 to HP path
  535. *
  536. * @param priv wm8994 information
  537. * @returns -1 for error and 0 Success.
  538. *
  539. */
  540. static int wm8994_init_volume_aif1_dac1(struct wm8994_priv *priv)
  541. {
  542. int ret = 0;
  543. /* Unmute AIF1DAC */
  544. ret |= wm8994_i2c_write(priv, WM8994_AIF1_DAC_FILTERS_1, 0x0000);
  545. ret |= wm8994_bic_or(priv, WM8994_DAC1_LEFT_VOLUME,
  546. WM8994_DAC1_VU_MASK | WM8994_DAC1L_VOL_MASK |
  547. WM8994_DAC1L_MUTE_MASK, WM8994_DAC1_VU | 0xc0);
  548. ret |= wm8994_bic_or(priv, WM8994_DAC1_RIGHT_VOLUME,
  549. WM8994_DAC1_VU_MASK | WM8994_DAC1R_VOL_MASK |
  550. WM8994_DAC1R_MUTE_MASK, WM8994_DAC1_VU | 0xc0);
  551. /* Head Phone Volume */
  552. ret |= wm8994_i2c_write(priv, WM8994_LEFT_OUTPUT_VOLUME, 0x12D);
  553. ret |= wm8994_i2c_write(priv, WM8994_RIGHT_OUTPUT_VOLUME, 0x12D);
  554. if (ret < 0) {
  555. debug("%s: codec register access error\n", __func__);
  556. return -1;
  557. }
  558. return 0;
  559. }
  560. /*
  561. * Intialise wm8994 codec device
  562. *
  563. * @param priv wm8994 information
  564. *
  565. * @returns -1 for error and 0 Success.
  566. */
  567. static int wm8994_device_init(struct wm8994_priv *priv)
  568. {
  569. const char *devname;
  570. unsigned short reg_data;
  571. int ret;
  572. wm8994_i2c_write(priv, WM8994_SOFTWARE_RESET, WM8994_SW_RESET);
  573. ret = wm8994_i2c_read(priv, WM8994_SOFTWARE_RESET, &reg_data);
  574. if (ret < 0) {
  575. debug("Failed to read ID register\n");
  576. return ret;
  577. }
  578. if (reg_data == WM8994_ID) {
  579. devname = "WM8994";
  580. debug("Device registered as type %d\n", priv->type);
  581. priv->type = WM8994;
  582. } else {
  583. debug("Device is not a WM8994, ID is %x\n", ret);
  584. return -ENXIO;
  585. }
  586. ret = wm8994_i2c_read(priv, WM8994_CHIP_REVISION, &reg_data);
  587. if (ret < 0) {
  588. debug("Failed to read revision register: %d\n", ret);
  589. return ret;
  590. }
  591. priv->revision = reg_data;
  592. debug("%s revision %c\n", devname, 'A' + priv->revision);
  593. return 0;
  594. }
  595. static int wm8994_setup_interface(struct wm8994_priv *priv,
  596. enum en_audio_interface aif_id)
  597. {
  598. int ret;
  599. /* VMID Selection */
  600. ret = wm8994_bic_or(priv, WM8994_POWER_MANAGEMENT_1,
  601. WM8994_VMID_SEL_MASK | WM8994_BIAS_ENA_MASK, 0x3);
  602. /* Charge Pump Enable */
  603. ret |= wm8994_bic_or(priv, WM8994_CHARGE_PUMP_1, WM8994_CP_ENA_MASK,
  604. WM8994_CP_ENA);
  605. /* Head Phone Power Enable */
  606. ret |= wm8994_bic_or(priv, WM8994_POWER_MANAGEMENT_1,
  607. WM8994_HPOUT1L_ENA_MASK, WM8994_HPOUT1L_ENA);
  608. ret |= wm8994_bic_or(priv, WM8994_POWER_MANAGEMENT_1,
  609. WM8994_HPOUT1R_ENA_MASK, WM8994_HPOUT1R_ENA);
  610. if (aif_id == WM8994_AIF1) {
  611. ret |= wm8994_i2c_write(priv, WM8994_POWER_MANAGEMENT_2,
  612. WM8994_TSHUT_ENA | WM8994_MIXINL_ENA |
  613. WM8994_MIXINR_ENA | WM8994_IN2L_ENA |
  614. WM8994_IN2R_ENA);
  615. ret |= wm8994_i2c_write(priv, WM8994_POWER_MANAGEMENT_4,
  616. WM8994_ADCL_ENA | WM8994_ADCR_ENA |
  617. WM8994_AIF1ADC1R_ENA |
  618. WM8994_AIF1ADC1L_ENA);
  619. /* Power enable for AIF1 and DAC1 */
  620. ret |= wm8994_i2c_write(priv, WM8994_POWER_MANAGEMENT_5,
  621. WM8994_AIF1DACL_ENA |
  622. WM8994_AIF1DACR_ENA |
  623. WM8994_DAC1L_ENA | WM8994_DAC1R_ENA);
  624. } else if (aif_id == WM8994_AIF2) {
  625. /* Power enable for AIF2 and DAC1 */
  626. ret |= wm8994_bic_or(priv, WM8994_POWER_MANAGEMENT_5,
  627. WM8994_AIF2DACL_ENA_MASK | WM8994_AIF2DACR_ENA_MASK |
  628. WM8994_DAC1L_ENA_MASK | WM8994_DAC1R_ENA_MASK,
  629. WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA |
  630. WM8994_DAC1L_ENA | WM8994_DAC1R_ENA);
  631. }
  632. /* Head Phone Initialisation */
  633. ret |= wm8994_bic_or(priv, WM8994_ANALOGUE_HP_1,
  634. WM8994_HPOUT1L_DLY_MASK | WM8994_HPOUT1R_DLY_MASK,
  635. WM8994_HPOUT1L_DLY | WM8994_HPOUT1R_DLY);
  636. ret |= wm8994_bic_or(priv, WM8994_DC_SERVO_1,
  637. WM8994_DCS_ENA_CHAN_0_MASK |
  638. WM8994_DCS_ENA_CHAN_1_MASK , WM8994_DCS_ENA_CHAN_0 |
  639. WM8994_DCS_ENA_CHAN_1);
  640. ret |= wm8994_bic_or(priv, WM8994_ANALOGUE_HP_1,
  641. WM8994_HPOUT1L_DLY_MASK |
  642. WM8994_HPOUT1R_DLY_MASK | WM8994_HPOUT1L_OUTP_MASK |
  643. WM8994_HPOUT1R_OUTP_MASK |
  644. WM8994_HPOUT1L_RMV_SHORT_MASK |
  645. WM8994_HPOUT1R_RMV_SHORT_MASK, WM8994_HPOUT1L_DLY |
  646. WM8994_HPOUT1R_DLY | WM8994_HPOUT1L_OUTP |
  647. WM8994_HPOUT1R_OUTP | WM8994_HPOUT1L_RMV_SHORT |
  648. WM8994_HPOUT1R_RMV_SHORT);
  649. /* MIXER Config DAC1 to HP */
  650. ret |= wm8994_bic_or(priv, WM8994_OUTPUT_MIXER_1,
  651. WM8994_DAC1L_TO_HPOUT1L_MASK,
  652. WM8994_DAC1L_TO_HPOUT1L);
  653. ret |= wm8994_bic_or(priv, WM8994_OUTPUT_MIXER_2,
  654. WM8994_DAC1R_TO_HPOUT1R_MASK,
  655. WM8994_DAC1R_TO_HPOUT1R);
  656. if (aif_id == WM8994_AIF1) {
  657. /* Routing AIF1 to DAC1 */
  658. ret |= wm8994_i2c_write(priv, WM8994_DAC1_LEFT_MIXER_ROUTING,
  659. WM8994_AIF1DAC1L_TO_DAC1L);
  660. ret |= wm8994_i2c_write(priv, WM8994_DAC1_RIGHT_MIXER_ROUTING,
  661. WM8994_AIF1DAC1R_TO_DAC1R);
  662. /* GPIO Settings for AIF1 */
  663. ret |= wm8994_i2c_write(priv, WM8994_GPIO_1,
  664. WM8994_GPIO_DIR_OUTPUT |
  665. WM8994_GPIO_FUNCTION_I2S_CLK |
  666. WM8994_GPIO_INPUT_DEBOUNCE);
  667. ret |= wm8994_init_volume_aif1_dac1(priv);
  668. } else if (aif_id == WM8994_AIF2) {
  669. /* Routing AIF2 to DAC1 */
  670. ret |= wm8994_bic_or(priv, WM8994_DAC1_LEFT_MIXER_ROUTING,
  671. WM8994_AIF2DACL_TO_DAC1L_MASK,
  672. WM8994_AIF2DACL_TO_DAC1L);
  673. ret |= wm8994_bic_or(priv, WM8994_DAC1_RIGHT_MIXER_ROUTING,
  674. WM8994_AIF2DACR_TO_DAC1R_MASK,
  675. WM8994_AIF2DACR_TO_DAC1R);
  676. /* GPIO Settings for AIF2 */
  677. /* B CLK */
  678. ret |= wm8994_bic_or(priv, WM8994_GPIO_3, WM8994_GPIO_DIR_MASK |
  679. WM8994_GPIO_FUNCTION_MASK,
  680. WM8994_GPIO_DIR_OUTPUT);
  681. /* LR CLK */
  682. ret |= wm8994_bic_or(priv, WM8994_GPIO_4, WM8994_GPIO_DIR_MASK |
  683. WM8994_GPIO_FUNCTION_MASK,
  684. WM8994_GPIO_DIR_OUTPUT);
  685. /* DATA */
  686. ret |= wm8994_bic_or(priv, WM8994_GPIO_5, WM8994_GPIO_DIR_MASK |
  687. WM8994_GPIO_FUNCTION_MASK,
  688. WM8994_GPIO_DIR_OUTPUT);
  689. ret |= wm8994_init_volume_aif2_dac1(priv);
  690. }
  691. if (ret < 0)
  692. goto err;
  693. debug("%s: Codec chip setup ok\n", __func__);
  694. return 0;
  695. err:
  696. debug("%s: Codec chip setup error\n", __func__);
  697. return -1;
  698. }
  699. static int _wm8994_init(struct wm8994_priv *priv,
  700. enum en_audio_interface aif_id, int sampling_rate,
  701. int mclk_freq, int bits_per_sample,
  702. unsigned int channels)
  703. {
  704. int ret;
  705. ret = wm8994_setup_interface(priv, aif_id);
  706. if (ret < 0) {
  707. debug("%s: wm8994 codec chip init failed\n", __func__);
  708. return ret;
  709. }
  710. ret = wm8994_set_sysclk(priv, aif_id, WM8994_SYSCLK_MCLK1, mclk_freq);
  711. if (ret < 0) {
  712. debug("%s: wm8994 codec set sys clock failed\n", __func__);
  713. return ret;
  714. }
  715. ret = wm8994_hw_params(priv, aif_id, sampling_rate, bits_per_sample,
  716. channels);
  717. if (ret == 0) {
  718. ret = wm8994_set_fmt(priv, aif_id, SND_SOC_DAIFMT_I2S |
  719. SND_SOC_DAIFMT_NB_NF |
  720. SND_SOC_DAIFMT_CBS_CFS);
  721. }
  722. return ret;
  723. }
  724. static int wm8994_set_params(struct udevice *dev, int interface, int rate,
  725. int mclk_freq, int bits_per_sample, uint channels)
  726. {
  727. struct wm8994_priv *priv = dev_get_priv(dev);
  728. return _wm8994_init(priv, interface, rate, mclk_freq, bits_per_sample,
  729. channels);
  730. }
  731. static int wm8994_probe(struct udevice *dev)
  732. {
  733. struct wm8994_priv *priv = dev_get_priv(dev);
  734. priv->dev = dev;
  735. return wm8994_device_init(priv);
  736. }
  737. static const struct audio_codec_ops wm8994_ops = {
  738. .set_params = wm8994_set_params,
  739. };
  740. static const struct udevice_id wm8994_ids[] = {
  741. { .compatible = "wolfson,wm8994" },
  742. { }
  743. };
  744. U_BOOT_DRIVER(wm8994) = {
  745. .name = "wm8994",
  746. .id = UCLASS_AUDIO_CODEC,
  747. .of_match = wm8994_ids,
  748. .probe = wm8994_probe,
  749. .ops = &wm8994_ops,
  750. .priv_auto_alloc_size = sizeof(struct wm8994_priv),
  751. };