keystone_serdes.c 5.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * TI serdes driver for keystone2.
  4. *
  5. * (C) Copyright 2014
  6. * Texas Instruments Incorporated, <www.ti.com>
  7. */
  8. #include <errno.h>
  9. #include <common.h>
  10. #include <asm/ti-common/keystone_serdes.h>
  11. #include <linux/bitops.h>
  12. #define SERDES_CMU_REGS(x) (0x0000 + (0x0c00 * (x)))
  13. #define SERDES_LANE_REGS(x) (0x0200 + (0x200 * (x)))
  14. #define SERDES_COMLANE_REGS 0x0a00
  15. #define SERDES_WIZ_REGS 0x1fc0
  16. #define SERDES_CMU_REG_000(x) (SERDES_CMU_REGS(x) + 0x000)
  17. #define SERDES_CMU_REG_010(x) (SERDES_CMU_REGS(x) + 0x010)
  18. #define SERDES_COMLANE_REG_000 (SERDES_COMLANE_REGS + 0x000)
  19. #define SERDES_LANE_REG_000(x) (SERDES_LANE_REGS(x) + 0x000)
  20. #define SERDES_LANE_REG_028(x) (SERDES_LANE_REGS(x) + 0x028)
  21. #define SERDES_LANE_CTL_STATUS_REG(x) (SERDES_WIZ_REGS + 0x0020 + (4 * (x)))
  22. #define SERDES_PLL_CTL_REG (SERDES_WIZ_REGS + 0x0034)
  23. #define SERDES_RESET BIT(28)
  24. #define SERDES_LANE_RESET BIT(29)
  25. #define SERDES_LANE_LOOPBACK BIT(30)
  26. #define SERDES_LANE_EN_VAL(x, y, z) (x[y] | (z << 26) | (z << 10))
  27. #define SERDES_CMU_CFG_NUM 5
  28. #define SERDES_COMLANE_CFG_NUM 10
  29. #define SERDES_LANE_CFG_NUM 10
  30. struct serdes_cfg {
  31. u32 ofs;
  32. u32 val;
  33. u32 mask;
  34. };
  35. struct cfg_entry {
  36. enum ks2_serdes_clock clk;
  37. enum ks2_serdes_rate rate;
  38. struct serdes_cfg cmu[SERDES_CMU_CFG_NUM];
  39. struct serdes_cfg comlane[SERDES_COMLANE_CFG_NUM];
  40. struct serdes_cfg lane[SERDES_LANE_CFG_NUM];
  41. };
  42. /* SERDES PHY lane enable configuration value, indexed by PHY interface */
  43. static u32 serdes_cfg_lane_enable[] = {
  44. 0xf000f0c0, /* SGMII */
  45. 0xf0e9f038, /* PCSR */
  46. };
  47. /* SERDES PHY PLL enable configuration value, indexed by PHY interface */
  48. static u32 serdes_cfg_pll_enable[] = {
  49. 0xe0000000, /* SGMII */
  50. 0xee000000, /* PCSR */
  51. };
  52. /**
  53. * Array to hold all possible serdes configurations.
  54. * Combination for 5 clock settings and 6 baud rates.
  55. */
  56. static struct cfg_entry cfgs[] = {
  57. {
  58. .clk = SERDES_CLOCK_156P25M,
  59. .rate = SERDES_RATE_5G,
  60. .cmu = {
  61. {0x0000, 0x00800000, 0xffff0000},
  62. {0x0014, 0x00008282, 0x0000ffff},
  63. {0x0060, 0x00142438, 0x00ffffff},
  64. {0x0064, 0x00c3c700, 0x00ffff00},
  65. {0x0078, 0x0000c000, 0x0000ff00}
  66. },
  67. .comlane = {
  68. {0x0a00, 0x00000800, 0x0000ff00},
  69. {0x0a08, 0x38a20000, 0xffff0000},
  70. {0x0a30, 0x008a8a00, 0x00ffff00},
  71. {0x0a84, 0x00000600, 0x0000ff00},
  72. {0x0a94, 0x10000000, 0xff000000},
  73. {0x0aa0, 0x81000000, 0xff000000},
  74. {0x0abc, 0xff000000, 0xff000000},
  75. {0x0ac0, 0x0000008b, 0x000000ff},
  76. {0x0b08, 0x583f0000, 0xffff0000},
  77. {0x0b0c, 0x0000004e, 0x000000ff}
  78. },
  79. .lane = {
  80. {0x0004, 0x38000080, 0xff0000ff},
  81. {0x0008, 0x00000000, 0x000000ff},
  82. {0x000c, 0x02000000, 0xff000000},
  83. {0x0010, 0x1b000000, 0xff000000},
  84. {0x0014, 0x00006fb8, 0x0000ffff},
  85. {0x0018, 0x758000e4, 0xffff00ff},
  86. {0x00ac, 0x00004400, 0x0000ff00},
  87. {0x002c, 0x00100800, 0x00ffff00},
  88. {0x0080, 0x00820082, 0x00ff00ff},
  89. {0x0084, 0x1d0f0385, 0xffffffff}
  90. },
  91. },
  92. };
  93. static inline void ks2_serdes_rmw(u32 addr, u32 value, u32 mask)
  94. {
  95. writel(((readl(addr) & (~mask)) | (value & mask)), addr);
  96. }
  97. static void ks2_serdes_cfg_setup(u32 base, struct serdes_cfg *cfg, u32 size)
  98. {
  99. u32 i;
  100. for (i = 0; i < size; i++)
  101. ks2_serdes_rmw(base + cfg[i].ofs, cfg[i].val, cfg[i].mask);
  102. }
  103. static void ks2_serdes_lane_config(u32 base, struct serdes_cfg *cfg_lane,
  104. u32 size, u32 lane)
  105. {
  106. u32 i;
  107. for (i = 0; i < size; i++)
  108. ks2_serdes_rmw(base + cfg_lane[i].ofs + SERDES_LANE_REGS(lane),
  109. cfg_lane[i].val, cfg_lane[i].mask);
  110. }
  111. static int ks2_serdes_init_cfg(u32 base, struct cfg_entry *cfg, u32 num_lanes)
  112. {
  113. u32 i;
  114. ks2_serdes_cfg_setup(base, cfg->cmu, SERDES_CMU_CFG_NUM);
  115. ks2_serdes_cfg_setup(base, cfg->comlane, SERDES_COMLANE_CFG_NUM);
  116. for (i = 0; i < num_lanes; i++)
  117. ks2_serdes_lane_config(base, cfg->lane, SERDES_LANE_CFG_NUM, i);
  118. return 0;
  119. }
  120. static void ks2_serdes_cmu_comlane_enable(u32 base, struct ks2_serdes *serdes)
  121. {
  122. /* Bring SerDes out of Reset */
  123. ks2_serdes_rmw(base + SERDES_CMU_REG_010(0), 0x0, SERDES_RESET);
  124. if (serdes->intf == SERDES_PHY_PCSR)
  125. ks2_serdes_rmw(base + SERDES_CMU_REG_010(1), 0x0, SERDES_RESET);
  126. /* Enable CMU and COMLANE */
  127. ks2_serdes_rmw(base + SERDES_CMU_REG_000(0), 0x03, 0x000000ff);
  128. if (serdes->intf == SERDES_PHY_PCSR)
  129. ks2_serdes_rmw(base + SERDES_CMU_REG_000(1), 0x03, 0x000000ff);
  130. ks2_serdes_rmw(base + SERDES_COMLANE_REG_000, 0x5f, 0x000000ff);
  131. }
  132. static void ks2_serdes_pll_enable(u32 base, struct ks2_serdes *serdes)
  133. {
  134. writel(serdes_cfg_pll_enable[serdes->intf],
  135. base + SERDES_PLL_CTL_REG);
  136. }
  137. static void ks2_serdes_lane_reset(u32 base, u32 reset, u32 lane)
  138. {
  139. if (reset)
  140. ks2_serdes_rmw(base + SERDES_LANE_REG_028(lane),
  141. 0x1, SERDES_LANE_RESET);
  142. else
  143. ks2_serdes_rmw(base + SERDES_LANE_REG_028(lane),
  144. 0x0, SERDES_LANE_RESET);
  145. }
  146. static void ks2_serdes_lane_enable(u32 base,
  147. struct ks2_serdes *serdes, u32 lane)
  148. {
  149. /* Bring lane out of reset */
  150. ks2_serdes_lane_reset(base, 0, lane);
  151. writel(SERDES_LANE_EN_VAL(serdes_cfg_lane_enable, serdes->intf,
  152. serdes->rate_mode),
  153. base + SERDES_LANE_CTL_STATUS_REG(lane));
  154. /* Set NES bit if Loopback Enabled */
  155. if (serdes->loopback)
  156. ks2_serdes_rmw(base + SERDES_LANE_REG_000(lane),
  157. 0x1, SERDES_LANE_LOOPBACK);
  158. }
  159. int ks2_serdes_init(u32 base, struct ks2_serdes *serdes, u32 num_lanes)
  160. {
  161. int i;
  162. int ret = 0;
  163. for (i = 0; i < ARRAY_SIZE(cfgs); i++)
  164. if (serdes->clk == cfgs[i].clk && serdes->rate == cfgs[i].rate)
  165. break;
  166. if (i >= ARRAY_SIZE(cfgs)) {
  167. puts("Cannot find keystone SerDes configuration");
  168. return -EINVAL;
  169. }
  170. ks2_serdes_init_cfg(base, &cfgs[i], num_lanes);
  171. ks2_serdes_cmu_comlane_enable(base, serdes);
  172. for (i = 0; i < num_lanes; i++)
  173. ks2_serdes_lane_enable(base, serdes, i);
  174. ks2_serdes_pll_enable(base, serdes);
  175. return ret;
  176. }