serial_zynq.c 5.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2012 Michal Simek <monstr@monstr.eu>
  4. * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved.
  5. */
  6. #include <clk.h>
  7. #include <common.h>
  8. #include <debug_uart.h>
  9. #include <dm.h>
  10. #include <errno.h>
  11. #include <fdtdec.h>
  12. #include <log.h>
  13. #include <watchdog.h>
  14. #include <asm/io.h>
  15. #include <dm/device_compat.h>
  16. #include <linux/bitops.h>
  17. #include <linux/compiler.h>
  18. #include <serial.h>
  19. #include <linux/err.h>
  20. #define ZYNQ_UART_SR_TXACTIVE BIT(11) /* TX active */
  21. #define ZYNQ_UART_SR_TXFULL BIT(4) /* TX FIFO full */
  22. #define ZYNQ_UART_SR_RXEMPTY BIT(1) /* RX FIFO empty */
  23. #define ZYNQ_UART_CR_TX_EN BIT(4) /* TX enabled */
  24. #define ZYNQ_UART_CR_RX_EN BIT(2) /* RX enabled */
  25. #define ZYNQ_UART_CR_TXRST BIT(1) /* TX logic reset */
  26. #define ZYNQ_UART_CR_RXRST BIT(0) /* RX logic reset */
  27. #define ZYNQ_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */
  28. struct uart_zynq {
  29. u32 control; /* 0x0 - Control Register [8:0] */
  30. u32 mode; /* 0x4 - Mode Register [10:0] */
  31. u32 reserved1[4];
  32. u32 baud_rate_gen; /* 0x18 - Baud Rate Generator [15:0] */
  33. u32 reserved2[4];
  34. u32 channel_sts; /* 0x2c - Channel Status [11:0] */
  35. u32 tx_rx_fifo; /* 0x30 - FIFO [15:0] or [7:0] */
  36. u32 baud_rate_divider; /* 0x34 - Baud Rate Divider [7:0] */
  37. };
  38. struct zynq_uart_platdata {
  39. struct uart_zynq *regs;
  40. };
  41. /* Set up the baud rate */
  42. static void _uart_zynq_serial_setbrg(struct uart_zynq *regs,
  43. unsigned long clock, unsigned long baud)
  44. {
  45. /* Calculation results. */
  46. unsigned int calc_bauderror, bdiv, bgen;
  47. unsigned long calc_baud = 0;
  48. /* Covering case where input clock is so slow */
  49. if (clock < 1000000 && baud > 4800)
  50. baud = 4800;
  51. /* master clock
  52. * Baud rate = ------------------
  53. * bgen * (bdiv + 1)
  54. *
  55. * Find acceptable values for baud generation.
  56. */
  57. for (bdiv = 4; bdiv < 255; bdiv++) {
  58. bgen = clock / (baud * (bdiv + 1));
  59. if (bgen < 2 || bgen > 65535)
  60. continue;
  61. calc_baud = clock / (bgen * (bdiv + 1));
  62. /*
  63. * Use first calculated baudrate with
  64. * an acceptable (<3%) error
  65. */
  66. if (baud > calc_baud)
  67. calc_bauderror = baud - calc_baud;
  68. else
  69. calc_bauderror = calc_baud - baud;
  70. if (((calc_bauderror * 100) / baud) < 3)
  71. break;
  72. }
  73. writel(bdiv, &regs->baud_rate_divider);
  74. writel(bgen, &regs->baud_rate_gen);
  75. }
  76. /* Initialize the UART, with...some settings. */
  77. static void _uart_zynq_serial_init(struct uart_zynq *regs)
  78. {
  79. /* RX/TX enabled & reset */
  80. writel(ZYNQ_UART_CR_TX_EN | ZYNQ_UART_CR_RX_EN | ZYNQ_UART_CR_TXRST | \
  81. ZYNQ_UART_CR_RXRST, &regs->control);
  82. writel(ZYNQ_UART_MR_PARITY_NONE, &regs->mode); /* 8 bit, no parity */
  83. }
  84. static int _uart_zynq_serial_putc(struct uart_zynq *regs, const char c)
  85. {
  86. if (readl(&regs->channel_sts) & ZYNQ_UART_SR_TXFULL)
  87. return -EAGAIN;
  88. writel(c, &regs->tx_rx_fifo);
  89. return 0;
  90. }
  91. static int zynq_serial_setbrg(struct udevice *dev, int baudrate)
  92. {
  93. struct zynq_uart_platdata *platdata = dev_get_platdata(dev);
  94. unsigned long clock;
  95. int ret;
  96. struct clk clk;
  97. ret = clk_get_by_index(dev, 0, &clk);
  98. if (ret < 0) {
  99. dev_err(dev, "failed to get clock\n");
  100. return ret;
  101. }
  102. clock = clk_get_rate(&clk);
  103. if (IS_ERR_VALUE(clock)) {
  104. dev_err(dev, "failed to get rate\n");
  105. return clock;
  106. }
  107. debug("%s: CLK %ld\n", __func__, clock);
  108. ret = clk_enable(&clk);
  109. if (ret && ret != -ENOSYS) {
  110. dev_err(dev, "failed to enable clock\n");
  111. return ret;
  112. }
  113. _uart_zynq_serial_setbrg(platdata->regs, clock, baudrate);
  114. return 0;
  115. }
  116. static int zynq_serial_probe(struct udevice *dev)
  117. {
  118. struct zynq_uart_platdata *platdata = dev_get_platdata(dev);
  119. struct uart_zynq *regs = platdata->regs;
  120. u32 val;
  121. /* No need to reinitialize the UART if TX already enabled */
  122. val = readl(&regs->control);
  123. if (val & ZYNQ_UART_CR_TX_EN)
  124. return 0;
  125. _uart_zynq_serial_init(platdata->regs);
  126. return 0;
  127. }
  128. static int zynq_serial_getc(struct udevice *dev)
  129. {
  130. struct zynq_uart_platdata *platdata = dev_get_platdata(dev);
  131. struct uart_zynq *regs = platdata->regs;
  132. if (readl(&regs->channel_sts) & ZYNQ_UART_SR_RXEMPTY)
  133. return -EAGAIN;
  134. return readl(&regs->tx_rx_fifo);
  135. }
  136. static int zynq_serial_putc(struct udevice *dev, const char ch)
  137. {
  138. struct zynq_uart_platdata *platdata = dev_get_platdata(dev);
  139. return _uart_zynq_serial_putc(platdata->regs, ch);
  140. }
  141. static int zynq_serial_pending(struct udevice *dev, bool input)
  142. {
  143. struct zynq_uart_platdata *platdata = dev_get_platdata(dev);
  144. struct uart_zynq *regs = platdata->regs;
  145. if (input)
  146. return !(readl(&regs->channel_sts) & ZYNQ_UART_SR_RXEMPTY);
  147. else
  148. return !!(readl(&regs->channel_sts) & ZYNQ_UART_SR_TXACTIVE);
  149. }
  150. static int zynq_serial_ofdata_to_platdata(struct udevice *dev)
  151. {
  152. struct zynq_uart_platdata *platdata = dev_get_platdata(dev);
  153. platdata->regs = (struct uart_zynq *)dev_read_addr(dev);
  154. if (IS_ERR(platdata->regs))
  155. return PTR_ERR(platdata->regs);
  156. return 0;
  157. }
  158. static const struct dm_serial_ops zynq_serial_ops = {
  159. .putc = zynq_serial_putc,
  160. .pending = zynq_serial_pending,
  161. .getc = zynq_serial_getc,
  162. .setbrg = zynq_serial_setbrg,
  163. };
  164. static const struct udevice_id zynq_serial_ids[] = {
  165. { .compatible = "xlnx,xuartps" },
  166. { .compatible = "cdns,uart-r1p8" },
  167. { .compatible = "cdns,uart-r1p12" },
  168. { }
  169. };
  170. U_BOOT_DRIVER(serial_zynq) = {
  171. .name = "serial_zynq",
  172. .id = UCLASS_SERIAL,
  173. .of_match = zynq_serial_ids,
  174. .ofdata_to_platdata = zynq_serial_ofdata_to_platdata,
  175. .platdata_auto_alloc_size = sizeof(struct zynq_uart_platdata),
  176. .probe = zynq_serial_probe,
  177. .ops = &zynq_serial_ops,
  178. };
  179. #ifdef CONFIG_DEBUG_UART_ZYNQ
  180. static inline void _debug_uart_init(void)
  181. {
  182. struct uart_zynq *regs = (struct uart_zynq *)CONFIG_DEBUG_UART_BASE;
  183. _uart_zynq_serial_init(regs);
  184. _uart_zynq_serial_setbrg(regs, CONFIG_DEBUG_UART_CLOCK,
  185. CONFIG_BAUDRATE);
  186. }
  187. static inline void _debug_uart_putc(int ch)
  188. {
  189. struct uart_zynq *regs = (struct uart_zynq *)CONFIG_DEBUG_UART_BASE;
  190. while (_uart_zynq_serial_putc(regs, ch) == -EAGAIN)
  191. WATCHDOG_RESET();
  192. }
  193. DEBUG_UART_FUNCS
  194. #endif