serial_s5p.c 5.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2009 SAMSUNG Electronics
  4. * Minkyu Kang <mk7.kang@samsung.com>
  5. * Heungjun Kim <riverful.kim@samsung.com>
  6. *
  7. * based on drivers/serial/s3c64xx.c
  8. */
  9. #include <common.h>
  10. #include <dm.h>
  11. #include <errno.h>
  12. #include <fdtdec.h>
  13. #include <linux/compiler.h>
  14. #include <asm/io.h>
  15. #include <asm/arch/clk.h>
  16. #include <asm/arch/uart.h>
  17. #include <serial.h>
  18. #include <clk.h>
  19. DECLARE_GLOBAL_DATA_PTR;
  20. #define RX_FIFO_COUNT_SHIFT 0
  21. #define RX_FIFO_COUNT_MASK (0xff << RX_FIFO_COUNT_SHIFT)
  22. #define RX_FIFO_FULL (1 << 8)
  23. #define TX_FIFO_COUNT_SHIFT 16
  24. #define TX_FIFO_COUNT_MASK (0xff << TX_FIFO_COUNT_SHIFT)
  25. #define TX_FIFO_FULL (1 << 24)
  26. /* Information about a serial port */
  27. struct s5p_serial_platdata {
  28. struct s5p_uart *reg; /* address of registers in physical memory */
  29. u8 port_id; /* uart port number */
  30. };
  31. /*
  32. * The coefficient, used to calculate the baudrate on S5P UARTs is
  33. * calculated as
  34. * C = UBRDIV * 16 + number_of_set_bits_in_UDIVSLOT
  35. * however, section 31.6.11 of the datasheet doesn't recomment using 1 for 1,
  36. * 3 for 2, ... (2^n - 1) for n, instead, they suggest using these constants:
  37. */
  38. static const int udivslot[] = {
  39. 0,
  40. 0x0080,
  41. 0x0808,
  42. 0x0888,
  43. 0x2222,
  44. 0x4924,
  45. 0x4a52,
  46. 0x54aa,
  47. 0x5555,
  48. 0xd555,
  49. 0xd5d5,
  50. 0xddd5,
  51. 0xdddd,
  52. 0xdfdd,
  53. 0xdfdf,
  54. 0xffdf,
  55. };
  56. static void __maybe_unused s5p_serial_init(struct s5p_uart *uart)
  57. {
  58. /* enable FIFOs, auto clear Rx FIFO */
  59. writel(0x3, &uart->ufcon);
  60. writel(0, &uart->umcon);
  61. /* 8N1 */
  62. writel(0x3, &uart->ulcon);
  63. /* No interrupts, no DMA, pure polling */
  64. writel(0x245, &uart->ucon);
  65. }
  66. static void __maybe_unused s5p_serial_baud(struct s5p_uart *uart, uint uclk,
  67. int baudrate)
  68. {
  69. u32 val;
  70. val = uclk / baudrate;
  71. writel(val / 16 - 1, &uart->ubrdiv);
  72. if (s5p_uart_divslot())
  73. writew(udivslot[val % 16], &uart->rest.slot);
  74. else
  75. writeb(val % 16, &uart->rest.value);
  76. }
  77. #ifndef CONFIG_SPL_BUILD
  78. int s5p_serial_setbrg(struct udevice *dev, int baudrate)
  79. {
  80. struct s5p_serial_platdata *plat = dev->platdata;
  81. struct s5p_uart *const uart = plat->reg;
  82. u32 uclk;
  83. #ifdef CONFIG_CLK_EXYNOS
  84. struct clk clk;
  85. u32 ret;
  86. ret = clk_get_by_index(dev, 1, &clk);
  87. if (ret < 0)
  88. return ret;
  89. uclk = clk_get_rate(&clk);
  90. #else
  91. uclk = get_uart_clk(plat->port_id);
  92. #endif
  93. s5p_serial_baud(uart, uclk, baudrate);
  94. return 0;
  95. }
  96. static int s5p_serial_probe(struct udevice *dev)
  97. {
  98. struct s5p_serial_platdata *plat = dev->platdata;
  99. struct s5p_uart *const uart = plat->reg;
  100. s5p_serial_init(uart);
  101. return 0;
  102. }
  103. static int serial_err_check(const struct s5p_uart *const uart, int op)
  104. {
  105. unsigned int mask;
  106. /*
  107. * UERSTAT
  108. * Break Detect [3]
  109. * Frame Err [2] : receive operation
  110. * Parity Err [1] : receive operation
  111. * Overrun Err [0] : receive operation
  112. */
  113. if (op)
  114. mask = 0x8;
  115. else
  116. mask = 0xf;
  117. return readl(&uart->uerstat) & mask;
  118. }
  119. static int s5p_serial_getc(struct udevice *dev)
  120. {
  121. struct s5p_serial_platdata *plat = dev->platdata;
  122. struct s5p_uart *const uart = plat->reg;
  123. if (!(readl(&uart->ufstat) & RX_FIFO_COUNT_MASK))
  124. return -EAGAIN;
  125. serial_err_check(uart, 0);
  126. return (int)(readb(&uart->urxh) & 0xff);
  127. }
  128. static int s5p_serial_putc(struct udevice *dev, const char ch)
  129. {
  130. struct s5p_serial_platdata *plat = dev->platdata;
  131. struct s5p_uart *const uart = plat->reg;
  132. if (readl(&uart->ufstat) & TX_FIFO_FULL)
  133. return -EAGAIN;
  134. writeb(ch, &uart->utxh);
  135. serial_err_check(uart, 1);
  136. return 0;
  137. }
  138. static int s5p_serial_pending(struct udevice *dev, bool input)
  139. {
  140. struct s5p_serial_platdata *plat = dev->platdata;
  141. struct s5p_uart *const uart = plat->reg;
  142. uint32_t ufstat = readl(&uart->ufstat);
  143. if (input)
  144. return (ufstat & RX_FIFO_COUNT_MASK) >> RX_FIFO_COUNT_SHIFT;
  145. else
  146. return (ufstat & TX_FIFO_COUNT_MASK) >> TX_FIFO_COUNT_SHIFT;
  147. }
  148. static int s5p_serial_ofdata_to_platdata(struct udevice *dev)
  149. {
  150. struct s5p_serial_platdata *plat = dev->platdata;
  151. fdt_addr_t addr;
  152. addr = dev_read_addr(dev);
  153. if (addr == FDT_ADDR_T_NONE)
  154. return -EINVAL;
  155. plat->reg = (struct s5p_uart *)addr;
  156. plat->port_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
  157. "id", dev->seq);
  158. return 0;
  159. }
  160. static const struct dm_serial_ops s5p_serial_ops = {
  161. .putc = s5p_serial_putc,
  162. .pending = s5p_serial_pending,
  163. .getc = s5p_serial_getc,
  164. .setbrg = s5p_serial_setbrg,
  165. };
  166. static const struct udevice_id s5p_serial_ids[] = {
  167. { .compatible = "samsung,exynos4210-uart" },
  168. { }
  169. };
  170. U_BOOT_DRIVER(serial_s5p) = {
  171. .name = "serial_s5p",
  172. .id = UCLASS_SERIAL,
  173. .of_match = s5p_serial_ids,
  174. .ofdata_to_platdata = s5p_serial_ofdata_to_platdata,
  175. .platdata_auto_alloc_size = sizeof(struct s5p_serial_platdata),
  176. .probe = s5p_serial_probe,
  177. .ops = &s5p_serial_ops,
  178. };
  179. #endif
  180. #ifdef CONFIG_DEBUG_UART_S5P
  181. #include <debug_uart.h>
  182. static inline void _debug_uart_init(void)
  183. {
  184. struct s5p_uart *uart = (struct s5p_uart *)CONFIG_DEBUG_UART_BASE;
  185. s5p_serial_init(uart);
  186. s5p_serial_baud(uart, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE);
  187. }
  188. static inline void _debug_uart_putc(int ch)
  189. {
  190. struct s5p_uart *uart = (struct s5p_uart *)CONFIG_DEBUG_UART_BASE;
  191. while (readl(&uart->ufstat) & TX_FIFO_FULL);
  192. writeb(ch, &uart->utxh);
  193. }
  194. DEBUG_UART_FUNCS
  195. #endif