serial_mvebu_a3700.c 3.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016 Stefan Roese <sr@denx.de>
  4. */
  5. #include <common.h>
  6. #include <dm.h>
  7. #include <serial.h>
  8. #include <asm/io.h>
  9. struct mvebu_platdata {
  10. void __iomem *base;
  11. };
  12. /*
  13. * Register offset
  14. */
  15. #define UART_RX_REG 0x00
  16. #define UART_TX_REG 0x04
  17. #define UART_CTRL_REG 0x08
  18. #define UART_STATUS_REG 0x0c
  19. #define UART_BAUD_REG 0x10
  20. #define UART_POSSR_REG 0x14
  21. #define UART_STATUS_RX_RDY 0x10
  22. #define UART_STATUS_TXFIFO_FULL 0x800
  23. #define UART_CTRL_RXFIFO_RESET 0x4000
  24. #define UART_CTRL_TXFIFO_RESET 0x8000
  25. #define CONFIG_UART_BASE_CLOCK 25804800
  26. static int mvebu_serial_putc(struct udevice *dev, const char ch)
  27. {
  28. struct mvebu_platdata *plat = dev_get_platdata(dev);
  29. void __iomem *base = plat->base;
  30. while (readl(base + UART_STATUS_REG) & UART_STATUS_TXFIFO_FULL)
  31. ;
  32. writel(ch, base + UART_TX_REG);
  33. return 0;
  34. }
  35. static int mvebu_serial_getc(struct udevice *dev)
  36. {
  37. struct mvebu_platdata *plat = dev_get_platdata(dev);
  38. void __iomem *base = plat->base;
  39. while (!(readl(base + UART_STATUS_REG) & UART_STATUS_RX_RDY))
  40. ;
  41. return readl(base + UART_RX_REG) & 0xff;
  42. }
  43. static int mvebu_serial_pending(struct udevice *dev, bool input)
  44. {
  45. struct mvebu_platdata *plat = dev_get_platdata(dev);
  46. void __iomem *base = plat->base;
  47. if (readl(base + UART_STATUS_REG) & UART_STATUS_RX_RDY)
  48. return 1;
  49. return 0;
  50. }
  51. static int mvebu_serial_setbrg(struct udevice *dev, int baudrate)
  52. {
  53. struct mvebu_platdata *plat = dev_get_platdata(dev);
  54. void __iomem *base = plat->base;
  55. /*
  56. * Calculate divider
  57. * baudrate = clock / 16 / divider
  58. */
  59. writel(CONFIG_UART_BASE_CLOCK / baudrate / 16, base + UART_BAUD_REG);
  60. /*
  61. * Set Programmable Oversampling Stack to 0,
  62. * UART defaults to 16x scheme
  63. */
  64. writel(0, base + UART_POSSR_REG);
  65. return 0;
  66. }
  67. static int mvebu_serial_probe(struct udevice *dev)
  68. {
  69. struct mvebu_platdata *plat = dev_get_platdata(dev);
  70. void __iomem *base = plat->base;
  71. /* reset FIFOs */
  72. writel(UART_CTRL_RXFIFO_RESET | UART_CTRL_TXFIFO_RESET,
  73. base + UART_CTRL_REG);
  74. /* No Parity, 1 Stop */
  75. writel(0, base + UART_CTRL_REG);
  76. return 0;
  77. }
  78. static int mvebu_serial_ofdata_to_platdata(struct udevice *dev)
  79. {
  80. struct mvebu_platdata *plat = dev_get_platdata(dev);
  81. plat->base = dev_read_addr_ptr(dev);
  82. return 0;
  83. }
  84. static const struct dm_serial_ops mvebu_serial_ops = {
  85. .putc = mvebu_serial_putc,
  86. .pending = mvebu_serial_pending,
  87. .getc = mvebu_serial_getc,
  88. .setbrg = mvebu_serial_setbrg,
  89. };
  90. static const struct udevice_id mvebu_serial_ids[] = {
  91. { .compatible = "marvell,armada-3700-uart" },
  92. { }
  93. };
  94. U_BOOT_DRIVER(serial_mvebu) = {
  95. .name = "serial_mvebu",
  96. .id = UCLASS_SERIAL,
  97. .of_match = mvebu_serial_ids,
  98. .ofdata_to_platdata = mvebu_serial_ofdata_to_platdata,
  99. .platdata_auto_alloc_size = sizeof(struct mvebu_platdata),
  100. .probe = mvebu_serial_probe,
  101. .ops = &mvebu_serial_ops,
  102. };
  103. #ifdef CONFIG_DEBUG_MVEBU_A3700_UART
  104. #include <debug_uart.h>
  105. static inline void _debug_uart_init(void)
  106. {
  107. void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
  108. /* reset FIFOs */
  109. writel(UART_CTRL_RXFIFO_RESET | UART_CTRL_TXFIFO_RESET,
  110. base + UART_CTRL_REG);
  111. /* No Parity, 1 Stop */
  112. writel(0, base + UART_CTRL_REG);
  113. /*
  114. * Calculate divider
  115. * baudrate = clock / 16 / divider
  116. */
  117. writel(CONFIG_UART_BASE_CLOCK / 115200 / 16, base + UART_BAUD_REG);
  118. /*
  119. * Set Programmable Oversampling Stack to 0,
  120. * UART defaults to 16x scheme
  121. */
  122. writel(0, base + UART_POSSR_REG);
  123. }
  124. static inline void _debug_uart_putc(int ch)
  125. {
  126. void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
  127. while (readl(base + UART_STATUS_REG) & UART_STATUS_TXFIFO_FULL)
  128. ;
  129. writel(ch, base + UART_TX_REG);
  130. }
  131. DEBUG_UART_FUNCS
  132. #endif