x1205.c 4.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2007
  4. * Stefan Roese, DENX Software Engineering, sr@denx.de.
  5. *
  6. * based on a the Linux rtc-x1207.c driver which is:
  7. * Copyright 2004 Karen Spearel
  8. * Copyright 2005 Alessandro Zummo
  9. *
  10. * Information and datasheet:
  11. * http://www.intersil.com/cda/deviceinfo/0,1477,X1205,00.html
  12. */
  13. /*
  14. * Date & Time support for Xicor/Intersil X1205 RTC
  15. */
  16. /* #define DEBUG */
  17. #include <common.h>
  18. #include <command.h>
  19. #include <log.h>
  20. #include <rtc.h>
  21. #include <i2c.h>
  22. #define CCR_SEC 0
  23. #define CCR_MIN 1
  24. #define CCR_HOUR 2
  25. #define CCR_MDAY 3
  26. #define CCR_MONTH 4
  27. #define CCR_YEAR 5
  28. #define CCR_WDAY 6
  29. #define CCR_Y2K 7
  30. #define X1205_REG_SR 0x3F /* status register */
  31. #define X1205_REG_Y2K 0x37
  32. #define X1205_REG_DW 0x36
  33. #define X1205_REG_YR 0x35
  34. #define X1205_REG_MO 0x34
  35. #define X1205_REG_DT 0x33
  36. #define X1205_REG_HR 0x32
  37. #define X1205_REG_MN 0x31
  38. #define X1205_REG_SC 0x30
  39. #define X1205_REG_DTR 0x13
  40. #define X1205_REG_ATR 0x12
  41. #define X1205_REG_INT 0x11
  42. #define X1205_REG_0 0x10
  43. #define X1205_REG_Y2K1 0x0F
  44. #define X1205_REG_DWA1 0x0E
  45. #define X1205_REG_YRA1 0x0D
  46. #define X1205_REG_MOA1 0x0C
  47. #define X1205_REG_DTA1 0x0B
  48. #define X1205_REG_HRA1 0x0A
  49. #define X1205_REG_MNA1 0x09
  50. #define X1205_REG_SCA1 0x08
  51. #define X1205_REG_Y2K0 0x07
  52. #define X1205_REG_DWA0 0x06
  53. #define X1205_REG_YRA0 0x05
  54. #define X1205_REG_MOA0 0x04
  55. #define X1205_REG_DTA0 0x03
  56. #define X1205_REG_HRA0 0x02
  57. #define X1205_REG_MNA0 0x01
  58. #define X1205_REG_SCA0 0x00
  59. #define X1205_CCR_BASE 0x30 /* Base address of CCR */
  60. #define X1205_ALM0_BASE 0x00 /* Base address of ALARM0 */
  61. #define X1205_SR_RTCF 0x01 /* Clock failure */
  62. #define X1205_SR_WEL 0x02 /* Write Enable Latch */
  63. #define X1205_SR_RWEL 0x04 /* Register Write Enable */
  64. #define X1205_DTR_DTR0 0x01
  65. #define X1205_DTR_DTR1 0x02
  66. #define X1205_DTR_DTR2 0x04
  67. #define X1205_HR_MIL 0x80 /* Set in ccr.hour for 24 hr mode */
  68. static void rtc_write(int reg, u8 val)
  69. {
  70. i2c_write(CONFIG_SYS_I2C_RTC_ADDR, reg, 2, &val, 1);
  71. }
  72. /*
  73. * In the routines that deal directly with the x1205 hardware, we use
  74. * rtc_time -- month 0-11, hour 0-23, yr = calendar year-epoch
  75. * Epoch is initialized as 2000. Time is set to UTC.
  76. */
  77. int rtc_get(struct rtc_time *tm)
  78. {
  79. u8 buf[8];
  80. i2c_read(CONFIG_SYS_I2C_RTC_ADDR, X1205_CCR_BASE, 2, buf, 8);
  81. debug("%s: raw read data - sec=%02x, min=%02x, hr=%02x, "
  82. "mday=%02x, mon=%02x, year=%02x, wday=%02x, y2k=%02x\n",
  83. __FUNCTION__,
  84. buf[0], buf[1], buf[2], buf[3],
  85. buf[4], buf[5], buf[6], buf[7]);
  86. tm->tm_sec = bcd2bin(buf[CCR_SEC]);
  87. tm->tm_min = bcd2bin(buf[CCR_MIN]);
  88. tm->tm_hour = bcd2bin(buf[CCR_HOUR] & 0x3F); /* hr is 0-23 */
  89. tm->tm_mday = bcd2bin(buf[CCR_MDAY]);
  90. tm->tm_mon = bcd2bin(buf[CCR_MONTH]); /* mon is 0-11 */
  91. tm->tm_year = bcd2bin(buf[CCR_YEAR])
  92. + (bcd2bin(buf[CCR_Y2K]) * 100);
  93. tm->tm_wday = buf[CCR_WDAY];
  94. debug("%s: tm is secs=%d, mins=%d, hours=%d, "
  95. "mday=%d, mon=%d, year=%d, wday=%d\n",
  96. __FUNCTION__,
  97. tm->tm_sec, tm->tm_min, tm->tm_hour,
  98. tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
  99. return 0;
  100. }
  101. int rtc_set(struct rtc_time *tm)
  102. {
  103. int i;
  104. u8 buf[8];
  105. debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
  106. tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
  107. tm->tm_hour, tm->tm_min, tm->tm_sec);
  108. buf[CCR_SEC] = bin2bcd(tm->tm_sec);
  109. buf[CCR_MIN] = bin2bcd(tm->tm_min);
  110. /* set hour and 24hr bit */
  111. buf[CCR_HOUR] = bin2bcd(tm->tm_hour) | X1205_HR_MIL;
  112. buf[CCR_MDAY] = bin2bcd(tm->tm_mday);
  113. /* month, 1 - 12 */
  114. buf[CCR_MONTH] = bin2bcd(tm->tm_mon);
  115. /* year, since the rtc epoch*/
  116. buf[CCR_YEAR] = bin2bcd(tm->tm_year % 100);
  117. buf[CCR_WDAY] = tm->tm_wday & 0x07;
  118. buf[CCR_Y2K] = bin2bcd(tm->tm_year / 100);
  119. /* this sequence is required to unlock the chip */
  120. rtc_write(X1205_REG_SR, X1205_SR_WEL);
  121. rtc_write(X1205_REG_SR, X1205_SR_WEL | X1205_SR_RWEL);
  122. /* write register's data */
  123. for (i = 0; i < 8; i++)
  124. rtc_write(X1205_CCR_BASE + i, buf[i]);
  125. rtc_write(X1205_REG_SR, 0);
  126. return 0;
  127. }
  128. void rtc_reset(void)
  129. {
  130. /*
  131. * Nothing to do
  132. */
  133. }