m41t62.c 5.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2018
  4. * Lukasz Majewski, DENX Software Engineering, lukma@denx.de.
  5. *
  6. * (C) Copyright 2008
  7. * Stefan Roese, DENX Software Engineering, sr@denx.de.
  8. *
  9. * based on a the Linux rtc-m41t80.c driver which is:
  10. * Alexander Bigga <ab@mycable.de>, 2006 (c) mycable GmbH
  11. */
  12. /*
  13. * Date & Time support for STMicroelectronics M41T62
  14. */
  15. /* #define DEBUG */
  16. #include <common.h>
  17. #include <command.h>
  18. #include <dm.h>
  19. #include <log.h>
  20. #include <rtc.h>
  21. #include <i2c.h>
  22. #define M41T62_REG_SSEC 0
  23. #define M41T62_REG_SEC 1
  24. #define M41T62_REG_MIN 2
  25. #define M41T62_REG_HOUR 3
  26. #define M41T62_REG_WDAY 4
  27. #define M41T62_REG_DAY 5
  28. #define M41T62_REG_MON 6
  29. #define M41T62_REG_YEAR 7
  30. #define M41T62_REG_ALARM_MON 0xa
  31. #define M41T62_REG_ALARM_DAY 0xb
  32. #define M41T62_REG_ALARM_HOUR 0xc
  33. #define M41T62_REG_ALARM_MIN 0xd
  34. #define M41T62_REG_ALARM_SEC 0xe
  35. #define M41T62_REG_FLAGS 0xf
  36. #define M41T62_DATETIME_REG_SIZE (M41T62_REG_YEAR + 1)
  37. #define M41T62_ALARM_REG_SIZE \
  38. (M41T62_REG_ALARM_SEC + 1 - M41T62_REG_ALARM_MON)
  39. #define M41T62_SEC_ST (1 << 7) /* ST: Stop Bit */
  40. #define M41T62_ALMON_AFE (1 << 7) /* AFE: AF Enable Bit */
  41. #define M41T62_ALMON_SQWE (1 << 6) /* SQWE: SQW Enable Bit */
  42. #define M41T62_ALHOUR_HT (1 << 6) /* HT: Halt Update Bit */
  43. #define M41T62_FLAGS_AF (1 << 6) /* AF: Alarm Flag Bit */
  44. #define M41T62_FLAGS_BATT_LOW (1 << 4) /* BL: Battery Low Bit */
  45. #define M41T62_FEATURE_HT (1 << 0)
  46. #define M41T62_FEATURE_BL (1 << 1)
  47. #define M41T80_ALHOUR_HT (1 << 6) /* HT: Halt Update Bit */
  48. static void m41t62_update_rtc_time(struct rtc_time *tm, u8 *buf)
  49. {
  50. debug("%s: raw read data - sec=%02x, min=%02x, hr=%02x, "
  51. "mday=%02x, mon=%02x, year=%02x, wday=%02x, y2k=%02x\n",
  52. __FUNCTION__,
  53. buf[0], buf[1], buf[2], buf[3],
  54. buf[4], buf[5], buf[6], buf[7]);
  55. tm->tm_sec = bcd2bin(buf[M41T62_REG_SEC] & 0x7f);
  56. tm->tm_min = bcd2bin(buf[M41T62_REG_MIN] & 0x7f);
  57. tm->tm_hour = bcd2bin(buf[M41T62_REG_HOUR] & 0x3f);
  58. tm->tm_mday = bcd2bin(buf[M41T62_REG_DAY] & 0x3f);
  59. tm->tm_wday = buf[M41T62_REG_WDAY] & 0x07;
  60. tm->tm_mon = bcd2bin(buf[M41T62_REG_MON] & 0x1f);
  61. /* assume 20YY not 19YY, and ignore the Century Bit */
  62. /* U-Boot needs to add 1900 here */
  63. tm->tm_year = bcd2bin(buf[M41T62_REG_YEAR]) + 100 + 1900;
  64. debug("%s: tm is secs=%d, mins=%d, hours=%d, "
  65. "mday=%d, mon=%d, year=%d, wday=%d\n",
  66. __FUNCTION__,
  67. tm->tm_sec, tm->tm_min, tm->tm_hour,
  68. tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
  69. }
  70. static void m41t62_set_rtc_buf(const struct rtc_time *tm, u8 *buf)
  71. {
  72. debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
  73. tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
  74. tm->tm_hour, tm->tm_min, tm->tm_sec);
  75. /* Merge time-data and register flags into buf[0..7] */
  76. buf[M41T62_REG_SSEC] = 0;
  77. buf[M41T62_REG_SEC] =
  78. bin2bcd(tm->tm_sec) | (buf[M41T62_REG_SEC] & ~0x7f);
  79. buf[M41T62_REG_MIN] =
  80. bin2bcd(tm->tm_min) | (buf[M41T62_REG_MIN] & ~0x7f);
  81. buf[M41T62_REG_HOUR] =
  82. bin2bcd(tm->tm_hour) | (buf[M41T62_REG_HOUR] & ~0x3f) ;
  83. buf[M41T62_REG_WDAY] =
  84. (tm->tm_wday & 0x07) | (buf[M41T62_REG_WDAY] & ~0x07);
  85. buf[M41T62_REG_DAY] =
  86. bin2bcd(tm->tm_mday) | (buf[M41T62_REG_DAY] & ~0x3f);
  87. buf[M41T62_REG_MON] =
  88. bin2bcd(tm->tm_mon) | (buf[M41T62_REG_MON] & ~0x1f);
  89. /* assume 20YY not 19YY */
  90. buf[M41T62_REG_YEAR] = bin2bcd(tm->tm_year % 100);
  91. }
  92. #ifdef CONFIG_DM_RTC
  93. static int m41t62_rtc_get(struct udevice *dev, struct rtc_time *tm)
  94. {
  95. u8 buf[M41T62_DATETIME_REG_SIZE];
  96. int ret;
  97. ret = dm_i2c_read(dev, 0, buf, sizeof(buf));
  98. if (ret)
  99. return ret;
  100. m41t62_update_rtc_time(tm, buf);
  101. return 0;
  102. }
  103. static int m41t62_rtc_set(struct udevice *dev, const struct rtc_time *tm)
  104. {
  105. u8 buf[M41T62_DATETIME_REG_SIZE];
  106. int ret;
  107. ret = dm_i2c_read(dev, 0, buf, sizeof(buf));
  108. if (ret)
  109. return ret;
  110. m41t62_set_rtc_buf(tm, buf);
  111. ret = dm_i2c_write(dev, 0, buf, sizeof(buf));
  112. if (ret) {
  113. printf("I2C write failed in %s()\n", __func__);
  114. return ret;
  115. }
  116. return 0;
  117. }
  118. static int m41t62_rtc_reset(struct udevice *dev)
  119. {
  120. u8 val;
  121. /*
  122. * M41T82: Make sure HT (Halt Update) bit is cleared.
  123. * This bit is 0 in M41T62 so its save to clear it always.
  124. */
  125. int ret = dm_i2c_read(dev, M41T62_REG_ALARM_HOUR, &val, sizeof(val));
  126. val &= ~M41T80_ALHOUR_HT;
  127. ret |= dm_i2c_write(dev, M41T62_REG_ALARM_HOUR, &val, sizeof(val));
  128. return ret;
  129. }
  130. /*
  131. * Make sure HT bit is cleared. This bit is set on entering battery backup
  132. * mode, so do this before the first read access.
  133. */
  134. static int m41t62_rtc_probe(struct udevice *dev)
  135. {
  136. return m41t62_rtc_reset(dev);
  137. }
  138. static const struct rtc_ops m41t62_rtc_ops = {
  139. .get = m41t62_rtc_get,
  140. .set = m41t62_rtc_set,
  141. .reset = m41t62_rtc_reset,
  142. };
  143. static const struct udevice_id m41t62_rtc_ids[] = {
  144. { .compatible = "st,m41t62" },
  145. { .compatible = "st,m41t82" },
  146. { .compatible = "st,m41st87" },
  147. { .compatible = "microcrystal,rv4162" },
  148. { }
  149. };
  150. U_BOOT_DRIVER(rtc_m41t62) = {
  151. .name = "rtc-m41t62",
  152. .id = UCLASS_RTC,
  153. .of_match = m41t62_rtc_ids,
  154. .ops = &m41t62_rtc_ops,
  155. .probe = &m41t62_rtc_probe,
  156. };
  157. #else /* NON DM RTC code - will be removed */
  158. int rtc_get(struct rtc_time *tm)
  159. {
  160. u8 buf[M41T62_DATETIME_REG_SIZE];
  161. i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE);
  162. m41t62_update_rtc_time(tm, buf);
  163. return 0;
  164. }
  165. int rtc_set(struct rtc_time *tm)
  166. {
  167. u8 buf[M41T62_DATETIME_REG_SIZE];
  168. i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE);
  169. m41t62_set_rtc_buf(tm, buf);
  170. if (i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, buf,
  171. M41T62_DATETIME_REG_SIZE)) {
  172. printf("I2C write failed in %s()\n", __func__);
  173. return -1;
  174. }
  175. return 0;
  176. }
  177. void rtc_reset(void)
  178. {
  179. u8 val;
  180. /*
  181. * M41T82: Make sure HT (Halt Update) bit is cleared.
  182. * This bit is 0 in M41T62 so its save to clear it always.
  183. */
  184. i2c_read(CONFIG_SYS_I2C_RTC_ADDR, M41T62_REG_ALARM_HOUR, 1, &val, 1);
  185. val &= ~M41T80_ALHOUR_HT;
  186. i2c_write(CONFIG_SYS_I2C_RTC_ADDR, M41T62_REG_ALARM_HOUR, 1, &val, 1);
  187. }
  188. #endif /* CONFIG_DM_RTC */